Manuel d'utilisation / d'entretien du produit MB91401 du fabricant Fujitsu
Aller à la page of 72
FUJITSU SEMICONDUCT OR DA T A S H E E T 32-Bit Propr ietar y Microcontroller LSI Netw ork Security System MB91401 ■ ■ ■ ■ DESCRIPTION The MB91401 is a network security LSI incor porating a Fujitsu’ s 32-bit, FR-family RISC microcontroller with 10/ 100Base-T MA C Controller , encr yption function and authentication function.
MB91401 2 • F or DES-ECB/DES-CBC/3DES-ECB/3DES-CBC mode* • F or MD5/SHA-1/HMAC-MD5/HMA C-SHA-1 mode • DH group: f or 1 (MODP 768 bit) /2 (1024 bit) F or the encr yption/authentication macros, a software library is av ailable b y contacting the Fujitsu sales repre- sentativ e as required.
MB91401 3 (Continued) • • • • CARD Interface (CompactFlash) The CompactFlash interf ace is a memor y and I/O mode correspondence. It corresponds to the I/O of data such as not only the memor y card but also the comm unication cards.
MB91401 4 ■ ■ ■ ■ PIN ASSIGNMENT 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 71 136 137 138 139 140 141 142 143 144 145 146 147 148 149 1.
MB91401 5 ■ ■ ■ ■ PIN NUMBER T ABLE Pin Number Pin name Pin Number Pin name Pin Number Pin name Pin Number Pin name 1 VSS 61 UDP 121 EXD11 181 SDA 2 CFD15 62 CFWEX 122 EXD14 182 USBINS 3 ICLK 63 CFCE1X 123 CFCD2X 183 UDM 4 ICS0 64 CFIORDX 124 UCLKSEL 184 CFRE SET 5 TDI 65 CFA1 125 CFWAITX 185 CFREGX 6 UCLK48 66 CFA5 126 N.
MB91401 6 ■ ■ ■ ■ PIN DESCRIPTION XINI 1 TXCLK 1 INITXI 1 TXD3 to TXD0 4 NMIX 1 TXEN 1 INT7 to INT5 3 RXCLK 1 MDI2 to MDI0 3 RXER 1 RXD3 to RXD0 4 OSCEA 1 RXDV 1 OSCC 1 RXCRS 1 OSCEB 1 COL 1 M.
MB91401 7 SYSTEM (9 pin) OSCILLATOR (3 pin) PLL CONTROL (5 pin) Pin name Pin no. Po l a r i t y I/O Circuit Function/application XINI 8 IN D Clock input pin Input pin of clock generated in clock generator. 10 MHz to 50 MHz frequency can be input. INITXI 204 Nega- tive IN D Reset input pin This pin inputs a signal to initialize the LSI.
MB91401 8 ICE (9 pin) JTAG (5 pin) TEST (5 pin) Pin name Pin no. Po l a r i t y I/O Circuit Function/application BREAKI 76 IN D Emulator break request pin This pin inputs the emulator break request when an ICE is connected. ICS2 ICS1 ICS0 74 75 4 OUT F Emulator chip status pins These pins output the emulator status when an ICE is connected.
MB91401 9 UART (6 pin) MEMORY IF (66 pin) (Continued) Pin name Pin no. Po l a r i t y I/O Circuit Function/application SIN1 SIN0 85 15 IN D Serial data input pins Serial data input pin of UART built-in FR core. SOUT1 SOUT0 149 86 OUT F Serial data output pins Serial data output pin of UART built-in FR core.
MB91401 10 (Continued) Pin name Pin no. Po l a r i t y I/O Circuit Function/application D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 .
MB91401 11 ETHERNET MAC CONTROLLER (17 pin) Pin name Pin no. Po l a r i t y I/O Circuit Function/application RXCLK 48 IN D Clock input for reception pin MII sync signal during reception.
MB91401 12 EXTERNAL IF (23 pin) Pin name Pin no. Po l a r i t y I/O Circuit Function/application EXCSX 50 Nega- tive IN D External chip select input pin Chip select input pin from external host. EXA 116 IN D External address input pin Address input pin from external host.
MB91401 13 USB IF (5 pin) Pin name Pin no. Po l a r i t y I/O Circuit Function/application UDP 61 I/O C USB data D + (differential) pin I/O signal pin on the plus side of the USB data. Use the LSI with 25 Ω to 30 Ω (27 Ω recommended) external series load resistors, 1.
MB91401 14 CARD IF (41 pin) (Continued) Pin name Pin no. Po l a r i t y I/O Circuit Function/application CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD0 CFD0 2 73 72 1.
MB91401 15 (Continued) Pin name Pin no. Po l a r i t y I/O Circuit Function/application CFCD1X 58 Nega- tive IN E Card connection detect input pin : CFCD1X Checking connection pin of the socket and CompactFlash card. It is shown that the CompactFlash card was connected when this signal and CFCD2X are both input by “0”.
MB91401 16 I 2 C IF (2 pin) Power Supply/GND (39 pin) Pin name Pin no. Po l a r i t y I/O Circuit Function/application SDA 181 I/O B Serial data line input/output pin I 2 C bus data I/O pin SCL 59 I/O B Serial clock line input/output pin I 2 C bus clock I/O pin Pin name Pin no.
MB91401 17 ■ ■ ■ ■ I/O CIRCUIT TYPE (Continued) T ype Circuit Remarks A • With pull/down • CMOS level output • CMOS level input • Value of pull-down resistance = approx.
MB91401 18 (Continued) T ype Circuit Remarks D CMOS level input E • With pull-up • CMOS level input • Value of pull-up resistance = approx. 33 k Ω (Typ) F CMOS level output G Oscillation circuit Digital input Digital input Digital output Digital output Oscillation output Control Prelminary 2004.
MB91401 19 ■ ■ ■ ■ HANDLING DEVICES Preventing Latc h-up When a v oltage that is higher than V DDE and a v oltage that is lo w er than V SS are impressed to the input terminal and the output ter minal in CMOS IC or the voltage that e xceeds ratings between V DDE to V SS is impressed, the latch-up phenomenon might be caused.
MB91401 20 Figure When y ou share the power supply f or digital and for VCO T reatment of the un used pins Leaving un used input pins open results in a malfunction, so process the pull-up or pull-down. T reatment of OPEN pins Be sure to use open pins in open state.
MB91401 21 ■ ■ ■ ■ CONNECTED SPECIFICA TION OF MB91401 AND ICE Recommended type and circuit configuration of the em ulator interf ace connector mounting on the user system, attention when designing and wiring regulation are shown. When the flat cable is used, the combination of the connectors with housing should be selected.
MB91401 22 • Precaution when designing When e valuation MCU on the user system is oper ated in the state that the emulator is not connected, should be treated as f ollow each input ter minal of e valuation MCU connected with the emulator interf ace on the user system.
MB91401 23 JT A G The JT A G function is installed in this LSI. Note that the ter minal INITXI should be input in "L" when using JT A G. Notes when quar tz vibrator is mounted The cr ystal oscillation circuit built into this LSI operates b y the f ollowing compositions .
MB91401 24 • Reference Value It is necessar y to add C3/L depending on a basic wav e and the ov er tone characteristic of the oscillator of the 20 MHz to 30 MHz belt. Note : These ref erence values are standards . The constant changes according to the characteristic of the quar tz vibrator used.
MB91401 25 • • • • Notes as device T reatment of Un used Input Pins It causes the malfunction that the unused input terminal is made open, and do the processing such as 1 stack or 0 stacks .
MB91401 26 CPU • The instruction fetch is not done from D-b us, and does not set the code area on D-b us RAM. • Set neither stack area nor the v ector table on the instruction RAM.
MB91401 27 • External bus interface • When the bus width of the area set up as little endian is 32-bit, confine to w o rd (32-bit) access when accessing the rele vant area. • When enabling pref etch to the area set to the Little endian, giv e the access to the corresponding area as word (32 bits) access limitation.
MB91401 28 ■ ■ ■ ■ NO TES OF DEBUG Step ex ecution of RETI instruction In an environment where interrupts frequently occur during single-step e xecution, only the rele vant interrupt processing routines are e xecuted repeatedly during single-step e xecution of the RETI instruction.
MB91401 29 ■ ■ ■ ■ BLOCK DIA GRAM FR core : CPU , U-Timer , U ART , Timer , Interrupt controller , DMAC , Bit search, Exter nal interrupt, Memor y_IF , Data-RAM, Cache, Bus controller P er iph.
MB91401 30 ■ ■ ■ ■ MEMOR Y SP A CE • Memory space The FR f amily has 4 GByte of logical addresses (2 32 address) which can be linear ly accessed by the CPU .
MB91401 31 ■ ■ ■ ■ GENERAL PURPOSE REGISTERS Registers R0 to R15 are general-purpose registers. The registers are used as the accumulator and memor y access pointers f or CPU operations. Of these 16 registers, the registers listed belo w are intended for special applications , for which some instructions are enhanced.
MB91401 32 ■ ■ ■ ■ MODE SETTINGS The FR f amily uses the mode pins (MDI2 to MDI0) and the mode register (MODR) to set the operation mode. • • • • Mode Pins Three mode pins MDI[2], MDI[1], and MDI[0] are used to specify a mode v ector f etch or test mode.
MB91401 33 [bit1, bit0] WTH1, WTH0 (Bus width setting bits) These bits specify the bus width. The v alue of the bits is set in the DBW1 and DBW0 bits in A CR0 (CSO area). Set these bits to a v alue other than “11”. • • • • Operation mode In the operation mode , there are a bus mode and an access mode.
MB91401 34 ■ ■ ■ ■ I/O MAP This shows the location of the v ar ious peripheral resource registers in the memor y space. [How to read the tab le] Note : Initial v alues of register bits are rep.
MB91401 35 (Continued) Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000_0060 H SSR0 [R/W] 00001-00 SIDR0 [R/W] XXXXXXXX SCR0 [R/W] 00000100 SMR0 [R/W] 00--0-0- UART0 0000_0064 H UT.
MB91401 36 (Continued) Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000_0308 H to 0000_03E0 H Reserved 0000_03E4 H ICHRC [R/W] 0-000000 Instruction Cache 0000_03E8 H to 000.
MB91401 37 (Continued) (Continued) Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 0000_046C H ICR44[R/W] ---11111 ICR45[R/W] ---11111 ICR46[R/W] ---11111 ICR47[R/W] ---11111 Interrupt.
MB91401 38 (Continued) *1 : An initial v alue is a diff erent register at the reset lev el. The displa y is the one at the INIT lev el. *2 : An initial v alue is a diff erent register at the reset lev el. The displa y is due to the INIT lev el by INITX.
MB91401 39 (Continued) Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 010F_0000 H BSR[R] 00000000 BCR[R/W] 00000000 CCR[R/W] 10000000 ADR[R/W] 1XXXXXXX I 2 C 010F_0004 H DAR[R/W] XXXX.
MB91401 40 (Continued) * : The attribute is diff erent according to the bit. Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 0110_0028 H SMI_CMD[R/W] 00000000-00000000 SIM IF 0.
MB91401 41 Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 0114_0000 H EXIFRXDR 00000000-00000000 [R] 00000000-00000000 External IF 0114_0004 H EXIFTXDR 00000000-00000000 [W] 00000000-.
MB91401 42 (Continued) Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 0540_0000 H FIFO0out[R] XXXXXXXX-XXXXXXXX FIFO0in[W] XXXXXXXX-XXXXXXXX USB 0540_0004 H FIFO1[R] XXXXXXXX-XXXXXXXX.
MB91401 43 (Continued) Address Register Bloc k + + + + 0 + + + + 1 + + + + 2 + + + + 3 0540_0068 H ST2[R] XXXXXXXX-X0000000 ST3[R/W] XXXXXXXX-XXX00000 USB 0540_006C H ST4[R] XXXXX000-00000000 ST5[R/W].
MB91401 44 ■ ■ ■ ■ INTERR UPT VECT OR (Continued) Interrupt source Interrupt number Interrupt level Offset Ad dress of TBR default RN Decimal Hexa- decimal Reset 0 00 3FC H 000FFFFC H .
MB91401 45 (Continued) Interrupt source Interrupt number Interrupt level Offset Ad dress of TBR default RN Decimal Hexa- decimal DMAC3 (end, error) 34 22 ICR18 374 H 000FFF74 H DMAC4 (end, error) .
MB91401 46 (Continued) (2) NMI (Non Maskable Interrupt) NMIs hav e the highest prior ity among the interr upt sources handled by this module . An NMI is alwa ys selected whene ver other types of interrupt sources occur at the same time.
MB91401 47 ■ ■ ■ ■ ELECTRICAL CHARA CTERISTICS 1. Absolute Maxim um Ratings *1 : This parameter is based on VSS = PLL VSS = 0 V . *2 : Note that analog pow er supply voltage and input v oltage do not exceed VDDE + 0.3 V at po wer on. *3 : The maximum output current is the peak v alue for a single pin.
MB91401 48 2. Recommended Operating Conditions (VSS = PLL VSS = 0 V) W ARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor de vice. All of the de vice’ s electr ical characteristics are warranted when the de vice is operated within these ra nges.
MB91401 49 3. DC Characteristics • Other than USB (VSS = PLL VSS = 0 V) Pa r a m e t e r Symbol Pin Conditions Va l u e Unit Min T yp Max “H” level input voltage V IH 2.0 VDDE + 0.3 V “L” level input voltage V IL VSS − 0.
MB91401 50 • USB (VSS = PLL VSS = 0 V) *1 : <About the output shor t-circuit current> Output shor t-circuit current I OS is the maximum current that flows when the output pin is connected to V DDE or V SS (within the maximum rating) . The current is “the short-circuit current per differential output pin.
MB91401 51 USB Specification Revision 1.1 *1 : <Input Le vels V IH , V IL > The s witching threshold voltage of the USB I/O b uffer’ s single-end receiver is set within the r ange from V IL (Max) = 0.8 V to V IH (Min) = 2.0 V (TTL input standard) .
MB91401 52 *4 : <Output Le vels V CRS > The cross v oltage of the e xter nal differential output signals (D + and D − ) f alls within the range from 1.3 V to 2.0 V . *5 : < T er minations V TERM > V TERM indicates the pull-up v o ltage at the upstream por t.
MB91401 53 4. A C Characteristics The following measurement conditions depending on the supply voltage apply to the MB91401 unless otherwise specified. (1) Cloc k * : The clock frequency m ust be set to over 25 MHz f or the Ether net MAC interf ace to perf or m 100 Base communication.
MB91401 54 (2) Reset Note : tcp is inter nal CPU and clock cycle period f or per ipheral module. Pa r a m e t e r Symbol Pin Conditions Va l u e Unit Remarks Min Max Reset input time trstl INITXI Afte.
MB91401 55 (3) Normal memory access Note : tcycp is e xter nal memor y clock cycle period. P arameter Symbol Pin T ypical timing Va l u e Unit Remarks Min Max Address delay time tchav A23 to A0 MCLKO .
MB91401 56 (4) Ready input P arameter Symbol Pin T ypical timing Va l u e Unit Remarks Min Max RDY setup trdys RDY MCLKO ↑ 19 ns RDY hold trdyh RDY MCLKO ↑ − 1 ns MCLK O RD Y trdys trdyh trdys trdyh Prelminary 2004.
MB91401 57 (5) U ART Note : timcycp is operational cloc k per iod of peripheral module built-in FR70E core . P arameter Symbol Pin Conditions Va l u e Unit Remarks Min Max Serial clock cycle time tscy.
MB91401 58 • Internal shift clock mode • External shift clock mode SCK1, SCK0 SOUT1, SOUT0 SIN1, SIN0 tscyc tslov tivsh tshix V OL V OL V OH SCK1, SCK0 SOUT1, SOUT0 SIN1, SIN0 tslsh tslov tivsh tshix tshsl Prelminary 2004.
MB91401 59 (6) MII interface • Transmission P arameter Symbol Pin T ypical timing Va l u e Unit Remarks Min Max TXEN delay time tdel_txen TXEN TXCLK ↑ 01 5 n s TXD delay time tdel_txd TXD3 to TXD0.
MB91401 60 • Reception RXCLK RXDV RXD3 to RXD0 thd_rxdv tsu_rxdv tsu_rxd thd_rxdv 05 5 RXCLK RXDV RXD3 to RXD0 thd_rxdv tsu_rxdv tsu_rxd thd_rxdv 0 n n − 1 RXCLK RXER tsu_rxer tsu_rxer thd_rxer thd_rxer Prelminary 2004.
MB91401 61 (7) MDIO interface P arameter Symbol Pin typical timing Va l u e Unit Remarks Min Max MDIO setup time tsu_mdio MDIO MDCLK ↑ 10 ns MDIO Hold Time thd_mdio MDIO MDCLK ↑ 0 ns MDIO .
MB91401 62 (8) External IF • Read access Note : tcp is inter nal CPU and operational cloc k per iod for peripheral module . Pa r a m e t e r S y m b o l P i n Va l u e Unit Remarks Min Max EX Read C.
MB91401 63 • Write access Note : tcp is inter nal CPU and operational cloc k per iod for peripheral module . Pa r a m e t e r S y m b o l P i n Va l u e Unit Remarks Min Max EX Write Cycle time texw.
MB91401 64 (9) USB interface *1 : The A C characteristics of the USB interface conf or m to USB Specification Re vision 1.1. *2 : < Driver Characteristics TFR, TFF , TFRFM> These items specify the diff erential data signal r ise (tr ise) and f a ll (tf all) times.
MB91401 65 T × D + T × D − 3-State Full-speed Buffer Rs Rs 28 Ω to 44 Ω Equiv. Imped 28 Ω to 44 Ω Equiv. Imped CL = 50 pF CL = 50 pF Notes : • Driver output impedance 3 Ω to 19 Ω • Rs series resistance: 25 Ω to 30 Ω • Add a series resistor of preferably 27 Ω Prelminary 2004.
MB91401 66 (10) I 2 C interface • Input timing specification * : Initial V alue : I 2 C bus standards . • Output timing specification * : F or value m, ref er to Section 7.5.2.3 “Clock Control Register (CCR) in the I 2 C Interf ace Specifications.
MB91401 67 (11) Card IF • Read access Pa r a m e t e r S y m b o l P i n Va l u e Unit Remarks Min Max CF Read Cycle time tcfrc CFA10 to CFA0, CFCE2X, CFCE1X ns CFA to Data Valid tcfadv CFA10.
MB91401 68 • Write access Pa r a m e t e r S y m b o l P i n Va l u e Unit Remarks Min Max CF Write Cycle time tcfwc CFA10 to CFA0, CFCE2X, CFCE1X ns CFA to Data Setup time tcfads CFA10 to CF.
MB91401 69 ■ ■ ■ ■ ORDERING INFORMA TION P ar t number P ackage Remarks MB91401 240-pin plastic FBGA (BGA-240P-M01) Prelminary 2004.11.12.
MB91401 70 ■ ■ ■ ■ P A CKA GE DIMENSION 240-pin plastic FBGA (BGA-240P-M01) Note: The actual shape of coners may differ from the dimension. Dimensions in mm (inches). Note : The values in parentheses are reference values. C 1999 FUJITSU LIMITED B240001S-2C-2 10.
MB91401 71 MEMO Prelminary 2004.11.12.
MB91401 FUJITSU LIMITED F or fur ther inf or mation please contact: Japan FUJITSU LIMITED Marketing Division Electronic De vices Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome , Shinjuku-k u, T okyo 163-0721, Japan T el: +81-3-5322-3353 F ax: +81-3-5322-3386 http://ede vice.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Fujitsu MB91401 c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Fujitsu MB91401 - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Fujitsu MB91401, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Fujitsu MB91401 va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Fujitsu MB91401, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Fujitsu MB91401.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Fujitsu MB91401. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Fujitsu MB91401 ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
