Manuel d'utilisation / d'entretien du produit PLB PCI Full Bridge du fabricant Xilinx
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0 PLB PCI Full Bridge (v1.00a) DS508 March 21, 20 06 0 0 Product Specification DS508 March 21, 2006 www .xilinx.com 1 Product Specification © 2005 Xilinx, Inc. All rights r eserved. All Xilinx trademarks, re gistered trademarks, patents, and furth er disclaimers are as listed at http://www .
PLB PCI Full Bridge (v1.00 a) 2 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Features • Independent PLB and PCI clocks • 33 MHz, 32-bit PCI bus support • Utilizes two pairs of FIFOs to exploit the separate master and slave PL B IPIF modules .
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 3 Product Specification E AR L Y ACCESS default in al l transfers. Addr ess translation is performe d by high-order bit substitution.
PLB PCI Full Bridge (v1.00 a) 4 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS System Reset When the bridge is reset, both RST_N and PLB_reset must be simultaneously held at reset for at least twenty clock periods of the slowest clock.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 5 Product Specification E AR L Y ACCESS core. These documents detail the v3.0 core operatio n, including configuration cycles, and are available from Xilinx. As re quired by the LogiCORE v3.
PLB PCI Full Bridge (v1.00 a) 6 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Example 3 outlines the use of the PCIBAR parameter sets for the address translation of PCI addresses within the range of a given PCIBAR to a r emote PLB addr ess space .
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 7 Product Specification E AR L Y ACCESS As in example 1, it is assumed that the pa rameter C_INCLUDE_BAROFFSET_REG=0, ther efore the C_IPIFBAR2PCIBAR_N parameters define the addr ess translation.
PLB PCI Full Bridge (v1.00 a) 8 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Accessing the PLB PCI Bridge PCIBAR_1 with address 0x1235FEDC on the PCI bus yields 0xFE35FEDC on the PLB bus.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 9 Product Specification E AR L Y ACCESS G13 IPIF BAR 2 memory designator C_IPIF_SP ACE TYPE_2 0 = I/O space 1 = Memory space 1 integer.
PLB PCI Full Bridge (v1.00 a) 10 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS G27 IPIF BAR to which PCI BAR 0 is mapped C_PCIBAR2 IPIFBAR_0 V ector of leng th C_PLB_A WIDT.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 11 Product Specification E AR L Y ACCESS G40 PCI2IPIF FIFO occupancy le vel in double words that triggers the br idge to initiate an IPIF b urst write to remote PLB de vice C_TRIG_IPIF_ WRBURST_ OCC_LEVEL 2 to the lesser of 24 or the PCI2IPIF FIFO DEPTH-3.
PLB PCI Full Bridge (v1.00 a) 12 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS G50 Number of IDELA Y controllers instantiated. Ignored it not Vir tex-4 C_NUM_ IDELA YCTRL 2-6 (Vir tex-4 only) 2 integer G51 Includes IDELA Y primiti ve on GNT_N.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 13 Product Specification E AR L Y ACCESS G61 Include configuration functionality via IPIF transactions C_INCLUDE_ PCI_CONFIG 0 = Not included 1 = Included 1 integer G62 Number of IDSEL signals suppor te d C_NUM_ IDSEL 1 to 16 8 integer G63 PCI address bit that PC I v3.
PLB PCI Full Bridge (v1.00 a) 14 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS PLB PCI Bus Interface I/O Signals The I/O signals for the PLB PCI Bridge are li sted in Ta b l e 2 . The interfaces r eferenced in this table are shown in Figure 1 in the PLB PCI Bridge block diagram.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 15 Product Specification E AR L Y ACCESS P27 Sl_rdBT er m PLB Bus O P28 Sl_MBusy(0:C_PLB_NU M_MASTERS-1) PLB Bus O P29 Sl_MErr(0:C_PLB.
PLB PCI Full Bridge (v1.00 a) 16 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS P55 CBE[(C_PCI_DBUS_WI DTH/8)-1:0] PCI Bus I/O Ti me-multiplex ed bus command and byte enab l.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 17 Product Specification E AR L Y ACCESS The REQ_N_toArb f acilitates an interfa ce to an intern al (i.e., in the FPGA) pci arbiter . The v3.0 input buffer for GNT_N is removed. This allows an inte rnal connection to GNT_N when using an internal arbiter .
PLB PCI Full Bridge (v1.00 a) 18 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS P ort and P arameter Dependencies The dependencies between the IPI v3.0 Bridge design port (i.e., I/O signals) and parameters ar e shown in Ta b l e 1.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 19 Product Specification E AR L Y ACCESS G12 C_IPIFBAR2PCIBAR_2 G1, G10, G11 and G48 Meaningful only if G48 = 0 and G1>2. In this case only high-order bits that are the same in G10 and G11 are meaningful.
PLB PCI Full Bridge (v1.00 a) 20 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS G26 C_PCIBAR_NUM G27-G32 The set of PCI/v3.0 BAR-parameters of N = 0 to C_PCIBAR_NUM-1 are meaningful and the parameters of N = C_PCIBAR_NUM up to an d including 2 hav e no effect.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 21 Product Specification E AR L Y ACCESS G43 C_NUM_PCI_RETRIES_IN _WRITES G44 C_NUM_PCI_PRDS_BET WN_RETRIES_IN_ WRITES G45 C_NUM_IPIF_.
PLB PCI Full Bridge (v1.00 a) 22 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Suppor ted PCI Bus Commands The list of commands suppor ted by the LogiCORE PCI interface is pr ovided in Ta b l e 4 . G62 C_NUM_IDSEL G49 and G63 G61 and G63 If G61=0, G62 has no meaning.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 23 Product Specification E AR L Y ACCESS PLB PCI Bridge Register Descriptions The PLB PCI Bridge contains addr essable r egist ers for read/write operations as shown in Ta b l e 5 . The base addr ess for these r egisters is set by the ba se address parameter (C_BASEADDR).
PLB PCI Full Bridge (v1.00 a) 24 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Register and P a rameter Dependencies The addr essable registers in the PLB PCI Bridge depend on the parame ter settings shown in Ta b l e 6 .
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 25 Product Specification E AR L Y ACCESS Global Interrupt Ena ble Register De scription A global enable is provided to globally enable or disable interrupts from the PCI device. This bit is AND’d with the output to the interrupt controlle r .
PLB PCI Full Bridge (v1.00 a) 26 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Bridge Interrupt E nable Register Description The PLB PCI Bridge has interrupt enable featur es as described in IPSPEC 048 PLB Device Interrupt Architectur e .
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 27 Product Specification E AR L Y ACCESS PLB PCI Bridge Reset Register Description The IP Reset module is always instantiated in the PLB PCI Bridge. Details on the IPIF Reset modul e can be found in the Processor IP Reference Guide .
PLB PCI Full Bridge (v1.00 a) 28 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Configuration Address P ort Register Description The Configuration Addres s Port Register exists only if the bridge is configured with PCI host bridge configuration functionality (i.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 29 Product Specification E AR L Y ACCESS bus number . The highest subordinate bus number is also an 8-bit value.
PLB PCI Full Bridge (v1.00 a) 30 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS The example below shows how the IPIFBAR2PCIBAR_N r egisters assignments define translation of PLB addr esses within the range of a given IPIFBAR to PCI address space.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 31 Product Specification E AR L Y ACCESS W riting 0xFEDC00 00 to IPIFBAR2PCIBAR_1 High-Order Bit Register and then accessing the PLB PCI bridge IPIFBAR_1 with address 0xABCDF123 on th e PLB bus would yie ld 0xFEDC1123 on the PCI bus.
PLB PCI Full Bridge (v1.00 a) 32 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS PLB PCI T ransactions The following subsections discuss detai ls of the following types of transactions for the PLB PCI bridge to realize data thr oughputs as high as 132 MB/sec.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 33 Product Specification E AR L Y ACCESS For all the transactions listed above, the following design requir ements are specified: • Both PCI and PLB clocks will be independent glob al buf fers.
PLB PCI Full Bridge (v1.00 a) 34 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS • Address translations in both directions ar e perfor med by high-or der addres s bits substitution in the address vector before cr ossing t o the other bus do main.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 35 Product Specification E AR L Y ACCESS mode). • If the PCI tar get address space is IO-space, the 2 LSBs are passed unchanged fr om that presented on the PLB bus. If the PLB transaction is not a burs t (i.
PLB PCI Full Bridge (v1.00 a) 36 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS • If a SERR occurs during a vali d data phase on a burst transfer , the PLB PCI Bridge causes an IPIF timeout and a sserts the IPIF Master Read SERR in terrupt.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 37 Product Specification E AR L Y ACCESS Ta b l e 17 summarizes the abnormal cond itions with which a PCI targ et can respond and how the response is translated to the PLB master . T able 17: Response of PLB Master/v3.
PLB PCI Full Bridge (v1.00 a) 38 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS when an incomplete PCI transactions occur or wh en PCI err ors occur . Details of the abnormal terminations are discussed in a late r section. In these transactions, the v3.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 39 Product Specification E AR L Y ACCESS burst write data fr om the PLB to PCI beyond the valid IPIF BAR addr ess range. The PLB PCI Bridge does not support fast back-to-back PCI transactions.
PLB PCI Full Bridge (v1.00 a) 40 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS transaction. The PLB PCI Bridge performs r etrie s up to a parameterized number of times as described earlier for the condition of disconne cts with/without data.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 41 Product Specification E AR L Y ACCESS PCI Initiator Initiates a Re ad Request of a PLB Slave This section discusses the ope ration of a remote PCI initiator asserting both single and multiple read com ma nds to read d at a f rom a rem ot e P LB s la ve.
PLB PCI Full Bridge (v1.00 a) 42 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Furthermore, it is the responsibili ty of the PCI initiator to prope rly read data fr om non-prefetchable PLB slaves.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 43 Product Specification E AR L Y ACCESS If the PLB clock is sl ower , the data flow is a series of PCI transa ctions that are termina.
Ta b l e 1 9 : Response to PCI initiator doing a read of a re mote PLB sla ve that terminat es the transfer with an abnormal condition on PLB bus Abnormal condition Memory Read Memory Read Multiple SERR T arget ab or t by v3.0 core, but completes PLB transaction.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 45 Product Specification E AR L Y ACCESS number of double wor ds are written, the IPIF master burst writes starts a fter the PCI transaction ends. The bridge attempts to burst write all the data to the PLB slave device.
PLB PCI Full Bridge (v1.00 a) 46 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS defined number of re tries are not successful, the PC I interr upt will be strobed. Data in the write buffer is flushed when the PCI interrupt is s trobed.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 47 Product Specification E AR L Y ACCESS bridge is n ot used. As with M emory and IO data tr ansactions, byte addressing integrity is maintained in configuration transf ers across the bus.
T able 21: Results of v3.0 core Command Re gister con figuratio n by remote host bridge (PCI-side) and by self-configuration (PLB- side) Results in Command Register after write (PLB-side byte s wapped.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 49 Product Specification E AR L Y ACCESS to the Configuration Data Port register initiates a Configuration W rite transaction on the PCI bus. Determination of whether the read or write transf er is type 0 or type 1 is done automatically .
PLB PCI Full Bridge (v1.00 a) 50 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS subordinate buses. Device numbers are independen t for each PLB PCI bridge inst antiated, but bus numbering must be monotonically incr easing fo r all primary buses and their subor dinate buses.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 51 Product Specification E AR L Y ACCESS Design Debug The OBP PCI Bridge has a test vector output (PCI_mon itor) to facilitate system debug (i.
PLB PCI Full Bridge (v1.00 a) 52 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS The constraints ar e also implemented automatically in the EDK tool flow with any tool option that invokes bridge synthesi s.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 53 Product Specification E AR L Y ACCESS NET "*/RST_N" IOBDELAY = BOTH ; NET "*/AD<*>" IOBDELAY = BOTH ; NET.
PLB PCI Full Bridge (v1.00 a) 54 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS # TIMEGRP "PCI_PADS_D" OFFSET=OUT 11.0 00 AFTER "PCI_CLK" TIMEGRP "FAST_FFS" ; TIMEGRP "PCI_PADS_B" OFFSET=OUT 11.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 55 Product Specification E AR L Y ACCESS one IDELA YCTRl withou t LOC constraints, the tools w ill replicate the primitive throughout the design.
PLB PCI Full Bridge (v1.00 a) 56 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS The parameter C_IDELA YCTRL_LOC has the syntax of IDELA YCTRL_XNYM where N and M are coordinates and multiple entries are concatenated by "-" (i.
PLB PCI Full Bridge (v1.00a) DS508 March 21, 2006 www .xilinx.com 57 Product Specification E AR L Y ACCESS the ucf-file in the implementati on directory of the bridge dir ectory to verify that the constraints are included. Alternatively , the user can include all constraints in the top-level ucf-file.
PLB PCI Full Bridge (v1.00 a) 58 www .xilinx.com DS508 March 21, 2006 Prod uct Specification EARL Y ACCESS Reference Documents The following documents contain reference inform ation importa nt to understanding the PLB PCI Bridge design: • Processor IP Refe rence Guide • Xilinx LogiCO RE PCI Interface v3.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Xilinx PLB PCI Full Bridge c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Xilinx PLB PCI Full Bridge - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Xilinx PLB PCI Full Bridge, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Xilinx PLB PCI Full Bridge va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Xilinx PLB PCI Full Bridge, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Xilinx PLB PCI Full Bridge.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Xilinx PLB PCI Full Bridge. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Xilinx PLB PCI Full Bridge ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
