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TMS320C6472/TMS320TCI6486 DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) Module User's Guide Literature Number: SPRUEF8F March 2006 – Revised November 2010.
2 SPRUEF8F – March 2006 – Revised November 2010 Submit Documentation Feedback Copyright © 2006–2010, Texas Instruments Incorporated.
Preface ...................................................................................................................................... 10 1 Introduction ..........................................................................................
www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) ................. 86 4.12 MDIO User Access Register 0 (USERACCESS0) ................................................................ 87 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) .
www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) ............................................................. 141 5.44 MAC Address High Bytes Register (MACADDRHI) ............................................................. 142 5.45 MAC Index Register (MACINDEX) .
www.ti.com List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 12 2 Ethernet Configuration with MII Interface ..........................................................
www.ti.com 48 Receive Teardown Register (RXTEARDOWN) ...................................................................... 100 49 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) .............................................. 101 50 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) .
www.ti.com List of Tables 1 Serial Management Interface Pins ...................................................................................... 13 2 EMAC1_EN Pin Description .........................................................................
www.ti.com 47 MAC Input Vector Register (MACINVECTOR) Field Descriptions ................................................ 105 48 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) Field Descriptions .................................. 106 49 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) Field Descriptions .
Preface SPRUEF8F – March 2006 – Revised November 2010 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices.
User's Guide SPRUEF8F – March 2006 – Revised November 2010 C6472/TCI6486 EMAC/MDIO 1 Introduction This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320TCI6486/TMS320C6472 devices.
EMIC0 CPPIbuffer manager+ CPPIRAM0 EMAC0 DMA memory transfercontrol Peripheral bus MDIO EMAC1 CPPIbuffer manager+ CPPIRAM1 EMIC1 T oGEMs T oGEMs MII0/GMII0 RGMII0 RMII0 S3MII0 T oPHYs RGMII1 RMII1 S3MII1 DMA memory transfercontrol EMAC Control0 Module EMAC Control1 Module Introduction www.
www.ti.com Introduction The EMAC module provides an efficient interface between the TCI6486/C6472 core processor and the networked community. The EMAC supports 10Base-T (10 Mbits/sec) and 100Base-TX (.
Introduction www.ti.com Table 2. EMAC1_EN Pin Description (continued) Value Description 1 EMAC1 is enabled and used. Pulls on EMAC1 I/O are disabled (except RGMII pins) and the corresponding I/O buffers are powered up except RGMII output-only pins. NOTE: RGMII buffers are HSTL buffers with no internal pulls.
www.ti.com EMAC Functional Architecture 2 EMAC Functional Architecture This section discusses the architecture and basic function of the EMAC peripheral. 2.1 Clock Control The frequencies for the transmit and receive clocks are fixed by the IEEE 802.3 specification, as shown below: • 2.
EMAC Functional Architecture www.ti.com 2.1.3 GMII Clocking The GMII interface is available only on EMAC0 and requires two clock sources generated internally, the peripheral bus clock and the RFTCLK inputs to the EMAC module. SYSCLK14 is programmed to /4 for this interface to provide a 125-MHz clock to the RFTCLK input of EMAC.
www.ti.com EMAC Functional Architecture 2.3 System-Level Connections On the TCI6486/C6472 device, EMAC0 and EMAC1 support the following different types of interfaces to physical layer devices (PHYs) or switches. Each EMAC can be configured to only one interface at any given time.
MTCLK MTXD[3−0] MTXEN MCOL MCRS MRCLK MRXD[3−0] MRXDV MRXER MDCLK MDIO 2.5 MHZ or 25 MHz Physical layer device (PHY) System core EMAC MDIO T ransformer RJ-45 EMAC Functional Architecture www.
www.ti.com EMAC Functional Architecture Table 7. EMAC and MDIO Signals for MII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations. The MTXD and MTXEN signals are tied to this clock.
MDCLK MDIO RMTXD[1−0] RMTXEN RMCRSDV RMRXD[1−0] RMRXER Physical layer device (PHY) EMAC MDIO System core RMREFCLK RMREFCLK 50-MHz zero-delay clock buffer 50-MHz XO EMAC Functional Architecture www.
MTCLK MTXD[7−0] MTXEN MCOL MCRS MRCLK MRXD[7−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core T ransformer 2.5 MHz, 25 MHz, or 125 MHz RJ−45 EMAC MDIO GMTCLK www.ti.com EMAC Functional Architecture Table 8. EMAC and MDIO Signals for RMII Interface (continued) Signal Name I/O Description RMRXER I Receive error (RMRXER).
EMAC Functional Architecture www.ti.com Table 9. EMAC and MDIO Signals for GMII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations in 10/100 Mbps mode.
RGTXC RGTXD[3−0] RGTXCTL RGREFCLK RGRXC RGRXD[3−0] RGRXCTL RGMDCLK RGMDIO Physical layer device (PHY) System core T ransformer 2.5 MHz 25 MHz, or 125 MHz RJ−45 EMAC MDIO www.ti.com EMAC Functional Architecture Figure 5. Ethernet Configuration with RGMII Interface The RGMII interface is a reduced pin alternative to the GMII interface.
EMAC Functional Architecture www.ti.com Table 10. EMAC and MDIO Signals for RGMII Interface (continued) Signal Name I/O Description RGRXCTL I Receive control (RGRXCTL).
TX_CLK TXD TX_SYNC RX_CLK RXD RX_SYNC MDCLK MDIO EMAC MDIO System core Physical layer device (PHY) MHZ_125_CLK 125-MHz zero-delay clockbuffer 125-MHz XO www.
EMAC Functional Architecture www.ti.com Table 11 summarizes the individual EMAC and MDIO signals for the S3MII interface. Table 11. EMAC and MDIO Signals for S3MII Interface Signal Name I/O Description TX_CLK O Transmit clock. The transmit clock is a continuous clock that provides the timing reference for transmit operations.
TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #1 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #2 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #n 125-MHz zero-delay c.
TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #1 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #2 TXD TX_SYNC TX_CLK RXD RX_SYNC RX_CLK MHZ_125_CLK Device #n 125-MHz zero-delay c.
Preamble SFD Destination Source Len Data 7 1 6 6 2 46 − (RXMAXLEN - 18) 4 FCS Number of bytes Legend: SFD = Start Frame Delimiter; FCS = Frame Check Sequence (CRC) www.ti.com EMAC Functional Architecture 2.4 Ethernet Protocol Overview Ethernet provides a reliable, connectionless service to a networking application.
EMAC Functional Architecture www.ti.com 2.4.2 Multiple Access Protocol Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame.
www.ti.com EMAC Functional Architecture 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors The buffer descriptor is a central part of the EMAC module. It determines how the application software describes ethernet packets to be sent and empty buffers to be filled with incoming packet data.
SOP | EOP 60 0 60 pBuffer pNext Packet A 60 bytes 0 SOP Packet B Fragment 1 512 bytes 512 1514 pBuffer pNext EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuffer −−− 500 pNext −−− pBuffer pNext Packet B Fragment 2 502 bytes SOP | EOP 0 Packet C 1514 bytes 1514 pBuffer pNext (NULL) 1514 EMAC Functional Architecture www.
www.ti.com EMAC Functional Architecture To add a descriptor or a linked list of descriptors to an EMAC descriptor queue for the first time, the software application writes the pointer to the descriptor or first descriptor of a list to the corresponding HDP register.
EMAC Functional Architecture www.ti.com 2.5.4 Transmit Buffer Descriptor Format A transmit (TX) buffer descriptor ( Figure 12 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure.
www.ti.com EMAC Functional Architecture 2.5.4.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue. The pointer creates a linked list of buffer descriptors.
EMAC Functional Architecture www.ti.com 2.5.4.7 End-of-Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start-of-packet (SOP) and EOP flags are set.
www.ti.com EMAC Functional Architecture 2.5.5 Receive Buffer Descriptor Format A receive (RX) buffer descriptor ( Figure 13 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by a C structure.
EMAC Functional Architecture www.ti.com 2.5.5.1 Next Descriptor Pointer The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the receive queue. The pointer creates a linked list of buffer descriptors.
www.ti.com EMAC Functional Architecture 2.5.5.7 End-of-Packet (EOP) Flag When set, this flag indicates that the descriptor points to the last packet buffer for a given packet. For a single fragment packet, both the start-of-packet (SOP) and EOP flags are set.
EMAC Functional Architecture www.ti.com 2.5.5.16 Control Flag The EMAC sets this flag in the SOP buffer descriptor if the received packet is an EMAC control frame and was not discarded because the RXCMFEN bit was set in the RXMBPENABLE register. 2.5.5.
TXpacerandinterruptcombiner RXpacerandinterruptcombiner MACTXINT0 MACRXINT0 Commoninterruptcombiner MACINT0 TXpacerandinterruptcombiner MACTXINT1 RXpacer.
Pacingblock T imed- delaySM DIV_NEXT DivideSM EVT_TIMED EVT_DIV EVT_OUT PS_TICK EVT_IN EMAC Functional Architecture www.ti.com 2.7.1 Pacing Block In simple terms, interrupt pacing represents delaying the initial EMAC events to CPU interrupt based on certain criteria.
W aiting Delay T ime=0 T ime=0 Output EVT_PULSE=0 && DIV_NEXT=1 EVT_PULSE=1&& TIME< TIME_CFG EVT_PULSE=1&& DIV_NEXT=1 PS_TICK=1&& TIME< TIME_CFG &a.
W aiting Count Output EVT_PULSE=0(or)EVT_PULSE=1&& CNT >=CNT_CFG&& TIME_CFGI=0 Increment CNT CNT=1 EVT_PULSE=0 &&CR=0 EVT_PULSE=0 && CR=1 EVT_PU.
Pacingblock TXEVT[0] Pacingblock TXEVT[1] EW_INTCTL[8] EW_INTCTL[9] Pacingblock TXEVT[2] Pacingblock TXEVT[3] EW_INTCTL[10] EW_INTCTL[1 1] Pacingblock TXEVT[4] Pacingblock TXEVT[5] E.
Pacingblock RXEVT[0] Pacingblock RXEVT[1] EW_INTCTL[16] EW_INTCTL[17] Pacingblock RXEVT[2] Pacingblock RXEVT[3] EW_INTCTL[18] EW_INTCTL[19] Pacingblock RXEVT[4] Pacingblock RXEVT[5] .
EW_INTCTL[1] EW_INTCTL[2] EW_INTCTL[3] EW_INTCTL[4] EW_INTCTL[4:1] MACINT Commoninterruptcombinerblock HOST ST A T MDIO_LINT MDIO_USER www.ti.
EMIC module Control registers andlogic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface PHY polling MDCLK MDIO LINKINT Configurationbus EMAC Functional Architecture www.ti.com Figure 21. MDIO Module Block Diagram 2.8.1.
www.ti.com EMAC Functional Architecture 2.8.2 MDIO Module Operational Overview The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and control up to two Ethernet PHYs, using a shared two-wired bus.
EMAC Functional Architecture www.ti.com 2.8.2.2 Writing Data to a PHY Register The MDIO module includes a user access register (USERACCESS n ) to directly access a specified PHY device. To write a PHY register, perform the following: 1. Ensure that the GO bit in the USERACCESS n register is cleared.
www.ti.com EMAC Functional Architecture The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it does not follow the procedure outlined in Section 2.
Clockand resetlogic Receive DMA engine Interrupt controller T ransmit DMA engine Control registers EMIC Receive FIFO MAC receiver State RAM Statistics T ransmit FIFO MAC transmitter Receive addr.
www.ti.com EMAC Functional Architecture can be sent to only a single channel. • The transmit path: – Transmit DMA engine The transmit DMA engine performs the data transfer between the device internal or external memory and the transmit FIFO. It interfaces to the processor through the bus arbiter in the CPPI buffer manager.
EMAC Functional Architecture www.ti.com An interrupt is issued to the CPU whenever a transmit or receive operation has completed. However, it is not necessary for the CPU to service the interrupt while there are additional resources available.
www.ti.com EMAC Functional Architecture Receive buffer flow control is triggered when the number of free buffers in any enabled receive channel (RX n FREEBUFFER) is less than or equal to the channel flow control threshold register (RX n FLOWTHRESH) value.
EMAC Functional Architecture www.ti.com • Zero padding to 64-byte data length (EMAC transmits only 64-byte pause frames). • The 32-bit frame-check sequence (CRC word). All quantities are hexadecimal and are transmitted most-significant-byte first.
www.ti.com EMAC Functional Architecture 2.10.2.5 Back Off The EMAC implements the 802.3 binary exponential back-off algorithm. 2.10.2.6 Transmit Flow Control When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any further frames.
EMAC Functional Architecture www.ti.com 2.10.2.7 Speed, Duplex, and Pause Frame Support The MAC can operate in half-duplex or full-duplex mode at 10 Mbps or 100 Mbps, and can operate in full duplex only in 1000 Mbps. Pause frame support is included in 10/100/1000 Mbps modes as configured by the host.
www.ti.com EMAC Functional Architecture A MAC address location in RAM is 53 bits wide and consists of: • 48 bits of the MAC address • 3 bits for the channel to which a valid address match will be transferred. The channel is a don't care if the MATCHFILT bit is cleared.
EMAC Functional Architecture www.ti.com 2.11.6 Receive Channel Teardown The host commands a receive channel teardown by writing the channel number to the RXTEARDOWN register. When a teardown command is issued to an enabled receive channel, the following occurs: • Any current frame in reception completes normally.
www.ti.com EMAC Functional Architecture 2.11.8 Promiscuous Receive Mode When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLE register, non-address matching frames that would normally be filtered are transferred to the promiscuous channel.
EMAC Functional Architecture www.ti.com Table 14. Receive Frame Treatment Summary (continued) Address RXMBPENABLE Bits Match RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame Treatment 1 X 1 1 0 Proper/oversize/jabber/code/align/CRC data and control frames transferred to address match channel.
www.ti.com EMAC Functional Architecture • Initialize the TX n HDP registers to zero. • Enable the desired transmit interrupts using the TXINTMASKSET and TXINTMASKCLEAR registers. • Set the appropriate configuration bits in the MACCONTROL register.
EMAC Functional Architecture www.ti.com For example, for 1000-Mbps operation, these restrictions translate into the following rules: • For the short-term average, each 64-byte memory read/write request from the EMAC must be serviced in no more than 0.
www.ti.com EMAC Functional Architecture 2.16 Initialization 2.16.1 Enabling the EMAC/MDIO Peripheral When the device is powered on, the EMAC peripheral is disabled. Prior to EMAC-specific initialization, the EMAC must be enabled; otherwise its registers cannot be written, and the reads will all return a value of zero.
EMAC Functional Architecture www.ti.com If the MDIO module must operate on an interrupt basis, the interrupts can be enabled at this time using the USERINTMASKSET register for register access and the USERPHYSEL n register if a target PHY is already known.
www.ti.com EMAC Functional Architecture Configuration register (EMACCFG), found at device level. 20. Enable the device interrupt in EW_INTCTL. 2.17 Interrupt Support 2.
EMAC Functional Architecture www.ti.com Upon interrupt reception, the CPU processes one or more packets from the buffer chain and then acknowledges one or more interrupt(s) by writing the address of the last buffer descriptor processed to the queue's associated RX completion pointer in the receive DMA state RAM.
www.ti.com EMAC Functional Architecture 2.17.2.1 Link Change Interrupt The MDIO module asserts a link change interrupt (LINKINT) if there is a change in the link state of the PHY corresponding to the address in the PHYADRMON bits in the USERPHYSEL n register, and if the LINKINTENB bit is also set in USERPHYSEL n .
EMAC Functional Architecture www.ti.com When the emulation suspend state is entered, the EMAC will stop processing receive and transmit frames at the next frame boundary. Any frame currently in reception or transmission will be completed normally without suspension.
www.ti.com EMIC Module Registers 3 EMIC Module Registers 3.1 EW_INTCTL Registers There are six EW_INTCTL registers (one per C64x+ megamodule). These registers, shown in Figure 23 , reside in the configuration space of the respective Ethernet wrappers.
EMIC Module Registers www.ti.com Figure 24. RPCFG Register 31 28 27 16 Reserved TIME_CFG 0000 R/W-0000 0000 1 5 87 43210 CNT_CFG Reserved TU CU TR CR R/W-0000 0000 0000 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 17.
www.ti.com EMIC Module Registers 3.2.2 RPSTAT Registers There are eight RPSTAT registers (RPSTAT0 thru RPSTAT7), one per receive event. This register configuration is common to all C64x+ megamodules. The RPSTAT register details are shown in Figure 25 and described in Table 18 .
EMIC Module Registers www.ti.com 3.3 TPIC Registers 3.3.1 TPCFG Registers There are eight TPCFG registers (TPCFG0 through TPCFG7), one per transmit event. This register configuration is common to all C64x+ megamodules. The TPCFG register details are shown in Figure 26 and described in Table 19 .
www.ti.com EMIC Module Registers 3.3.2 TPSTAT Registers There are eight TPSTAT registers (TPSTAT0 through TPSTAT7), one per transmit event. This register configuration is common to all C64x+mega modules. The TPSTAT register details are shown in Figure 27 and described in Table 20 .
MDIO Registers www.ti.com 4 MDIO Registers 4.1 Introduction Table 21 lists the memory-mapped registers for the Management Data Input/Output (MDIO). For the memory address of these registers, see the T.
www.ti.com MDIO Registers 4.2 MDIO Version Register (VERSION) The MDIO version register (VERSION) is shown in Figure 29 and described in Table 22 . Figure 29. MDIO Version Register (VERSION) 31 16 MODID R-7 15 8 7 0 REVMAJ REVMIN R-1 R-3 LEGEND: R = Read only; R/W = Read/Write; - n = value after reset Table 22.
MDIO Registers www.ti.com 4.3 MDIO Control Register (CONTROL) The MDIO control register (CONTROL) is shown in Figure 30 and described in Table 23 . Figure 30.
www.ti.com MDIO Registers 4.4 PHY Acknowledge Status Register (ALIVE) The PHY acknowledge status register (ALIVE) is shown in Figure 31 and described in Table 24 . Figure 31. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to clear; - n = value after reset Table 24.
MDIO Registers www.ti.com 4.5 PHY Link Status Register (LINK) The PHY link status register (LINK) is shown in Figure 32 and described in Table 25 . Figure 32. PHY Link Status Register (LINK) 31 16 LINK R-0 15 0 LINK R-0 LEGEND: R = Read only; - n = value after reset Table 25.
www.ti.com MDIO Registers 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 33 and described in Table 26 .
MDIO Registers www.ti.com 4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 34 and described in Table 27 .
www.ti.com MDIO Registers 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 35 and described in Table 28 .
MDIO Registers www.ti.com 4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 36 and described in Table 29 .
www.ti.com MDIO Registers 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 37 and described in Table 30 .
MDIO Registers www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 38 and described in Table 31 .
www.ti.com MDIO Registers 4.12 MDIO User Access Register 0 (USERACCESS0) The MDIO user access register 0 (USERACCESS0) is shown in Figure 39 and described in Table 32 .
MDIO Registers www.ti.com 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 40 and described in Table 33 .
www.ti.com MDIO Registers 4.14 MDIO User Access Register 1 (USERACCESS1) The MDIO user access register 1 (USERACCESS1) is shown in Figure 41 and described in Table 34 .
MDIO Registers www.ti.com 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 42 and described in Table 35 .
www.ti.com EMAC Port Registers 5 EMAC Port Registers Table 36 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC). For the memory address of these registers, see the TMS3.
EMAC Port Registers www.ti.com Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description See 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.28 160h MACCONTROL MAC Control Register Section 5.
www.ti.com EMAC Port Registers Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description See 65Ch TX7CP Transmit Channel 7 Completion Pointer (Interrupt Section 5.48 Acknowledge) Register 660h RX0CP Receive Channel 0 Completion Pointer (Interrupt Section 5.
EMAC Port Registers www.ti.com Table 36. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description See 27Ch FRAME1024TUP Transmit and Receive 1024 to RXMAXLEN Octet Frames Section 5.50.32 Register 280h NETOCTETS Network Octet Frames Register Section 5.
www.ti.com EMAC Port Registers 5.1 Transmit Identification and Version Register (TXIDVER) The transmit identification and version register (TXIDVER) is shown in Figure 43 and described in Table 37 .
EMAC Port Registers www.ti.com 5.2 Transmit Control Register (TXCONTROL) The transmit control register (TXCONTROL) is shown in Figure 44 and described in Table 38 . Figure 44. Transmit Control Register (TXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved TXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 38.
www.ti.com EMAC Port Registers 5.3 Transmit Teardown Register (TXTEARDOWN) The transmit teardown register (TXTEARDOWN) is shown in Figure 45 and described in Table 39 .
EMAC Port Registers www.ti.com 5.4 Receive Identification and Version Register (RXIDVER) The receive identification and version register (RXIDVER) is shown in Figure 46 and described in Table 40 .
www.ti.com EMAC Port Registers 5.5 Receive Control Register (RXCONTROL) The receive control register (RXCONTROL) is shown in Figure 47 and described in Table 41 . Figure 47. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 41.
EMAC Port Registers www.ti.com 5.6 Receive Teardown Register (RXTEARDOWN) The receive teardown register (RXTEARDOWN) is shown in Figure 48 and described in Table 42 .
www.ti.com EMAC Port Registers 5.7 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 49 and described in Table 43 .
EMAC Port Registers www.ti.com 5.8 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) The transmit interrupt status (masked) register (TXINTSTATMASKED) is shown in Figure 50 and described in Table 44 .
www.ti.com EMAC Port Registers 5.9 Transmit Interrupt Mask Set Register (TXINTMASKSET) The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 51 and described in Table 45 .
EMAC Port Registers www.ti.com 5.10 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 52 and described in Table 46 .
www.ti.com EMAC Port Registers 5.11 MAC Input Vector Register (MACINVECTOR) The MAC input vector register (MACINVECTOR) is shown in Figure 53 and described in Table 47 .
EMAC Port Registers www.ti.com 5.12 MAC End-of-Interrupt Vector Register (MACEOIVECTOR) The MAC end-of-interrupt vector register (MACEOIVECTOR) is shown in Figure 54 and described in Table 48 .
www.ti.com EMAC Port Registers 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) The receive interrupt status (unmasked) register (RXINTSTATRAW) is shown in Figure 55 and described in Table 49 .
EMAC Port Registers www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 56 and described in Table 50 .
www.ti.com EMAC Port Registers 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 57 and described in Table 51 .
EMAC Port Registers www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 58 and described in Table 52 .
www.ti.com EMAC Port Registers 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 59 and described in Table 53 .
EMAC Port Registers www.ti.com 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 60 and described in Table 54 .
www.ti.com EMAC Port Registers 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 61 and described in Table 55 .
EMAC Port Registers www.ti.com 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 62 and described in Table 56 .
www.ti.com EMAC Port Registers 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 63 and described in Table 57 . Figure 63.
EMAC Port Registers www.ti.com Table 57. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory.
www.ti.com EMAC Port Registers Table 57. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 2-0 RXMULTCH 0-3h Rece.
EMAC Port Registers www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) The receive unicast enable set register (RXUNICASTSET) is shown in Figure 64 and described in Table 58 .
www.ti.com EMAC Port Registers 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 65 and described in Table 59 .
EMAC Port Registers www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) The receive maximum length register (RXMAXLEN) is shown in Figure 66 and described in Table 60 . Figure 66. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 60.
www.ti.com EMAC Port Registers 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 67 and described in Table 61 .
EMAC Port Registers www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 68 and described in Table 62 .
www.ti.com EMAC Port Registers 5.27 Receive Channel 0-7 Flow Control Threshold Register (RX n FLOWTHRESH) The receive channel 0-7 flow control threshold register (RX n FLOWTHRESH) is shown in Figure 69 and described in Table 63 .
EMAC Port Registers www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 70 and described in Table 64 .
www.ti.com EMAC Port Registers 5.29 MAC Control Register (MACCONTROL) The MAC control register (MACCONTROL) is shown in Figure 71 and described in Table 65 .
EMAC Port Registers www.ti.com Table 65. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 12 RXFIFOFLOWEN Receive FIFO flow control enable 0 Receive flow control disabled. For full-duplex mode, no outgoing pause frames are sent.
www.ti.com EMAC Port Registers 5.30 MAC Status Register (MACSTATUS) The MAC status register (MACSTATUS) is shown in Figure 72 and described in Table 66 .
EMAC Port Registers www.ti.com Table 66. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 15-12 RXERRCODE Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error.
www.ti.com EMAC Port Registers 5.31 Emulation Control Register (EMCONTROL) The emulation control register (EMCONTROL) is shown in Figure 73 and described in Table 67 .
EMAC Port Registers www.ti.com 5.32 FIFO Control Register (FIFOCONTROL) The FIFO control register (FIFOCONTROL) is shown in Figure 74 and described in Table 68 .
www.ti.com EMAC Port Registers 5.33 MAC Configuration Register (MACCONFIG) The MAC configuration register (MACCONFIG) is shown in Figure 75 and described in Table 69 .
EMAC Port Registers www.ti.com 5.34 Soft Reset Register (SOFTRESET) The soft reset register (SOFTRESET) is shown in Figure 76 and described in Table 70 . Figure 76. Soft Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 70.
www.ti.com EMAC Port Registers 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 77 and described in Table 71 .
EMAC Port Registers www.ti.com 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) The MAC source address high bytes register (MACSRCADDRHI) is shown in Figure 78 and described in Table 72 .
www.ti.com EMAC Port Registers 5.37 MAC Hash Address Register 1 (MACHASH1) The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
EMAC Port Registers www.ti.com 5.38 MAC Hash Address Register 2 (MACHASH2) The MAC hash address register 2 (MACHASH2) is shown in Figure 80 and described in Table 74 . Figure 80. MAC Hash Address Register 2 (MACHASH2) 31 16 MACHASH2 R/W-0 15 0 MACHASH2 R/W-0 LEGEND: R/W = Read/Write; - n = value after reset Table 74.
www.ti.com EMAC Port Registers 5.39 Back Off Test Register (BOFFTEST) The back off test register (BOFFTEST) is shown in Figure 81 and described in Table 75 .
EMAC Port Registers www.ti.com 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) The transmit pacing algorithm test register (TPACETEST) is shown in Figure 82 and described in Table 76 .
www.ti.com EMAC Port Registers 5.41 Receive Pause Timer Register (RXPAUSE) The receive pause timer register (RXPAUSE) is shown in Figure 83 and described in Table 77 . Figure 83. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 77.
EMAC Port Registers www.ti.com 5.42 Transmit Pause Timer Register (TXPAUSE) The transmit pause timer register (TXPAUSE) is shown in Figure 84 and described in Table 78 . Figure 84. Transmit Pause Timer Register (TXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 78.
www.ti.com EMAC Port Registers 5.43 MAC Address Low Bytes Register (MACADDRLO) The MAC address low bytes register (MACADDRLO) is shown in Figure 85 and described in Table 79 .
EMAC Port Registers www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) The MAC address high bytes register (MACADDRHI) is shown in Figure 86 and described in Table 80 .
www.ti.com EMAC Port Registers 5.45 MAC Index Register (MACINDEX) The MAC index register (MACINDEX) is shown in Figure 87 and described in Table 81 . Figure 87. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 5 4 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 81.
EMAC Port Registers www.ti.com 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) The transmit channel 0-7 DMA head descriptor pointer register (TX n HDP) is shown in Figure 88 and described in Table 82 .
www.ti.com EMAC Port Registers 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) The receive channel 0-7 DMA head descriptor pointer register (RX n HDP) is shown in Figure 89 and described in Table 83 .
EMAC Port Registers www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TX n CP) The transmit channel 0-7 completion pointer register (TX n CP) is shown in Figure 90 and described in Table 84 .
www.ti.com EMAC Port Registers 5.49 Receive Channel 0-7 Completion Pointer Register (RX n CP) The receive channel 0-7 completion pointer register (RX n CP) is shown in Figure 91 and described in Table 85 .
EMAC Port Registers www.ti.com 5.50 Network Statistics Registers The EMAC has a set of statistics that record events associated with frame traffic. The statistics values are cleared to zero 38 clocks after the rising edge of reset. When the GMIIEN bit in the MACCONTROL register is set, all statistics registers are write-to-decrement.
www.ti.com EMAC Port Registers 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) The total number of good multicast frames received on the EMAC.
EMAC Port Registers www.ti.com 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) The total number of oversized frames received on the EMAC. An oversized frame is defined as having all of the foll.
www.ti.com EMAC Port Registers 5.50.11 Filtered Receive Frames Register (RXFILTERED) The total number of frames received on the EMAC that the EMAC address matching process indicated should be discarded.
EMAC Port Registers www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) The total number of good broadcast frames transmitted on the EMAC.
www.ti.com EMAC Port Registers • Was any size • Had no carrier loss and no underrun • Experienced one collision before successful transmission. The collision was not late.
EMAC Port Registers www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) The total number of frames on the EMAC that experienced carrier loss.
www.ti.com EMAC Port Registers 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) The total number of 256-byte to 511-byte frames received and transmitted on the EMAC.
EMAC Port Registers www.ti.com 5.50.34 Receive FIFO or DMA Start-of-Frame Overruns Register (RXSOFOVERRUNS) The total number of frames received on the EMAC that had either a FIFO or DMA start-of-frame (SOF) overrun.
www.ti.com Appendix A Glossary Broadcast MAC Address— A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast.
Appendix A www.ti.com Jumbo Packets— Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes. For the C64x+ devices, it is recommended not to use packets exceeding 35K in length.
www.ti.com Appendix B Revision History This revision history highlights the technical changes made to the document in this revision. Table 87. EMAC/MDIO Revision History See Additions/Modifications/De.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Texas Instruments TMS320TCI6486 c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Texas Instruments TMS320TCI6486 - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Texas Instruments TMS320TCI6486, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Texas Instruments TMS320TCI6486 va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Texas Instruments TMS320TCI6486, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Texas Instruments TMS320TCI6486.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Texas Instruments TMS320TCI6486. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Texas Instruments TMS320TCI6486 ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
