Manuel d'utilisation / d'entretien du produit TMS320C645x DSP du fabricant Texas Instruments
Aller à la page of 148
TMS320C645x DSP Ethernet Media Access Controller (EMAC)/ Management Data Input/Output (MDIO) User's Guide Literature Number: SPRU975B August 2006.
2 SPRU975B – August 2006 Submit Documentation Feedback.
Contents Preface .............................................................................................................................. 10 1 Introduction .........................................................................................
4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) .................................................... 80 5 EMAC Port Registers ................................................................................................. 81 5.1 Introduction ....
5.48 Transmit Channel 0-7 Completion Pointer Register (TX n CP) ........................................... 134 5.49 Receive Channel 0-7 Completion Pointer Register (RX n CP) ........................................... 135 5.50 Network Statistics Registers .
List of Figures 1 EMAC and MDIO Block Diagram ........................................................................................ 12 2 Ethernet Configuration with MII Interface .....................................................................
53 Receive Buffer Offset Register (RXBUFFEROFFSET) .............................................................. 109 54 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) .............................. 110 55 Receive Channel n Flow Control Threshold Register (RX n FLOWTHRESH) .
List of Tables 1 Interface Selection Pins ................................................................................................... 16 2 EMAC and MDIO Signals for MII Interface ................................................................
50 Receive Unicast Enable Set Register (RXUNICASTSET) Field Descriptions .................................... 106 51 Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions ....................................... 107 52 Receive Maximum Length Register (RXMAXLEN) Field Descriptions .
Preface SPRU975B – August 2006 Read This First About This Manual This document provides a functional description of the Ethernet Media Access Controller (EMAC) and Physical layer (PHY) device Management Data Input/Output (MDIO) module integrated with TMS320C645x devices.
1 Introduction 1.1 Purpose of the Peripheral 1.2 Features User's Guide SPRU975B – August 2006 Ethernet Media Access Controller (EMAC)/Management Data Input/Output (MDIO) This document provides .
www.ti.com 1.3 Functional Block Diagram Configuration bus DMA memory transfer controller Peripheral bus EMAC control module EMAC module MDIO module MII MDIO bus EMAC/MDIO interrupt Interrupt controlle.
www.ti.com 1.4 Industry Standard(s) Compliance Statement Introduction The EMAC peripheral conforms to the IEEE 802.3 standard, describing the “Carrier Sense Multiple Access with Collision Detection (CSMA/CD) Access Method and Physical Layer” specifications.
www.ti.com 2 EMAC Functional Architecture 2.1 Clock Control 2.1.1 MII Clocking 2.1.2 RMII Clocking 2.1.3 GMII Clocking EMAC Functional Architecture This chapter discusses the architecture and basic function of the EMAC peripheral. The frequencies for the transmit and receive clocks are fixed by the IEEE 802.
www.ti.com 2.1.4 RGMII Clocking 2.2 Memory Map EMAC Functional Architecture For timing purposes, data in 10/100 mode is transmitted and received with reference to MTCLK and MRCLK, respectively. For 1000 Mbps mode, receive timing is the same, but transmit is relative to GMTCLK.
www.ti.com 2.3 System Level Connections 2.3.1 Media Independent Interface (MII) Connections MTCLK MTXD[3−0] MTXEN MCOL MCRS MRCLK MRXD[3−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.
www.ti.com EMAC Functional Architecture Table 2 summarizes the individual EMAC and MDIO signals for the MII interface. For more information, refer to either the IEEE 802.3 standard or ISO/IEC 8802-3:2000(E). The EMAC module does not include a transmit error (MTXER) pin.
www.ti.com 2.3.2 Reduced Media Independent Interface (RMII) Connections MTXD[1−0] MTXEN MCRSDV MREFCLK MRXD[1−0] MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer RJ−45 EMAC MDIO EMAC Functional Architecture Figure 3 shows a device with integrated EMAC and MDIO interfaced via a RMII connection.
www.ti.com EMAC Functional Architecture The RMII interface has the same functionality as the MII, but it does so with a reduced number of pins, thus lowering the total cost for an application. In devices incorporating many PHY interfaces such as switches, the number of pins can add significant cost as the port counts increase.
www.ti.com 2.3.3 Gigabit Media Independent Interface (GMII) Connections MTCLK MTXD[7−0] MTXEN MCOL MCRS MRCLK MRXD[7−0] MRXDV MRXER MDCLK MDIO Physical layer device (PHY) System core Transformer 2.
www.ti.com EMAC Functional Architecture Table 4 summarizes the individual EMAC and MDIO signals for the GMII interface. Table 4. EMAC and MDIO Signals for GMII Interface Signal Name I/O Description MTCLK I Transmit clock (MTCLK). The transmit clock is a continuous clock that provides the timing reference for transmit operations in 10/100 Mbps mode.
www.ti.com 2.3.4 Reduced Gigabit Media Independent Interface (RGMII) Connections TXC TXD[3−0] TXCTL REFCLK RXC RXD[3−0] RXCTL MDCLK MDIO Physical layer device (PHY) System core Transformer 2.
www.ti.com EMAC Functional Architecture Table 5 summarizes the individual EMAC and MDIO signals for the RGMII interface. Table 5. EMAC and MDIO Signals for RGMII Interface Signal Name I/O Description TXC O Transmit clock (TXC). The transmit clock is a continuous clock that provides the timing reference for transmit operations.
www.ti.com 2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame Format Preamble SFD Destination Source Len Data 7 1 6 6 2 46 − (RXMAXLEN - 18) 4 FCS Number of bytes Legend: SFD=Start Frame Delimiter; FCS=Frame Check Sequence (CRC) EMAC Functional Architecture Ethernet provides an unreliable, connectionless service to a networking application.
www.ti.com 2.4.2 Multiple Access Protocol EMAC Functional Architecture Nodes in an ethernet local area network are interconnected by a broadcast channel. As a result, when an EMAC port transmits a frame, all of the adapters on the local network receive the frame.
www.ti.com 2.5 Programming Interface 2.5.1 Packet Buffer Descriptors EMAC Functional Architecture The buffer descriptor is a central part of the EMAC module. It determines how the application software describes ethernet packets to be sent and empty buffers to be filled with incoming packet data.
www.ti.com SOP | EOP 60 0 60 pBuf fer pNext Packet A 60 bytes 0 SOP Fragment 1 Packet B 512 1514 pBuf fer pNext 512 bytes EOP 0 0 −−− Packet B Fragment 3 500 bytes 502 pBuf fer −−− 500 pNe.
www.ti.com 2.5.2 Transmit and Receive Descriptor Queues EMAC Functional Architecture The EMAC module processes descriptors in linked list chains ( Section 2.5.1 ). The lists controlled by the EMAC are maintained by the application software via the head descriptor pointer (HDP) registers.
www.ti.com 2.5.3 Transmit and Receive EMAC Interrupts EMAC Functional Architecture The EMAC processes descriptors in linked list chains ( Section 2.5.1 ), using the linked list queue mechanism ( Section 2.5.2 ). The EMAC synchronizes the descriptor list processing by using interrupts to the software application.
www.ti.com 2.5.4 Transmit Buffer Descriptor Format EMAC Functional Architecture A transmit (TX) buffer descriptor ( Figure 9 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure.
www.ti.com 2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length 2.5.4.5 Packet Length 2.5.4.6 Start of Packet (SOP) Flag EMAC Functional Architecture The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the transmit queue.
www.ti.com 2.5.4.7 End of Packet (EOP) Flag 2.5.4.8 Ownership (OWNER) Flag 2.5.4.9 End of Queue (EOQ) Flag 2.5.4.10 Teardown Complete (TDOWNCMPLT) Flag 2.5.4.11 Pass CRC (PASSCRC) Flag EMAC Functional Architecture When set, this flag indicates that the descriptor points to the last packet buffer for a given packet.
www.ti.com 2.5.5 Receive Buffer Descriptor Format EMAC Functional Architecture A receive (RX) buffer descriptor ( Figure 10 ) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 2 shows the receive descriptor described by a C structure.
www.ti.com 2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer 2.5.5.3 Buffer Offset 2.5.5.4 Buffer Length 2.5.5.5 Packet Length EMAC Functional Architecture The next descriptor pointer indicates the 32-bit word aligned memory address of the next buffer descriptor in the receive queue.
www.ti.com 2.5.5.6 Start of Packet (SOP) Flag 2.5.5.7 End of Packet (EOP) Flag 2.5.5.8 Ownership (OWNER) Flag 2.5.5.9 End of Queue (EOQ) Flag 2.5.5.10 Teardown Complete (TDOWNCMPLT) Flag 2.
www.ti.com 2.5.5.14 Fragment Flag 2.5.5.15 Undersized Flag 2.5.5.16 Control Flag 2.5.5.17 Overrun Flag 2.5.5.18 Code Error (CODEERROR) Flag 2.5.5.19 Alignment Error (ALIGNERROR) Flag 2.
www.ti.com 2.6 EMAC Control Module Arbiter and bus switches CPU DMA Controllers 8K byte descriptor memory Configuration registers Interrupt logic Single interrupt to CPU EMAC interrupts MDIO interrupts Configuration bus T ransmit and Receive 2.6.1 Internal Memory 2.
www.ti.com 2.6.3 Interrupt Control 2.7 Management Data Input/Output (MDIO) Module 2.7.1 MDIO Module Components EMAC Functional Architecture The EMAC control module combines the multiple interrupt conditions generated by the EMAC and MDIO modules into a single interrupt signal that is mapped to a CPU interrupt via the CPU interrupt controller.
www.ti.com EMAC control module Control registers and logic PHY monitoring Peripheral clock MDIO clock generator USERINT MDIO interface polling PHY MDCLK MDIO LINKINT Configuration bus 2.7.1.1 MDIO Clock Generator 2.7.1.2 Global PHY Detection and Link State Monitoring 2.
www.ti.com 2.7.2 MDIO Module Operational Overview 2.7.2.1 Initializing the MDIO Module EMAC Functional Architecture The MDIO module implements the 802.3 serial management interface to simultaneously interrogate and control up to two Ethernet PHYs, using a shared two-wired bus.
www.ti.com 2.7.2.2 Writing Data to a PHY Register 2.7.2.3 Reading Data From a PHY Register 2.7.2.4 Example of MDIO Register Access Code EMAC Functional Architecture The MDIO module includes a user access register (USERACCESS n ) to directly access a specified PHY device.
www.ti.com EMAC Functional Architecture The implementation of these macros using the register layer Chip Support Library (CSL) is shown in Example 3 (USERACCESS0 is assumed). Note that this implementation does not check the ACK bit on PHY register reads; in other words, it does not follow the procedure outlined in Section 2.
www.ti.com 2.8 EMAC Module 2.8.1 EMAC Module Components Clock and reset logic Receive DMA engine Interrupt controller Transmit DMA engine Control registers Configuration bus EMAC control module Configuration bus RAM State FIFO Receive FIFO Transmit MAC transmitter Statistics receiver MAC SYNC MII RMII GMII RGMII address Receive 2.
www.ti.com 2.8.1.3 MAC Receiver 2.8.1.4 Receive Address 2.8.1.5 Transmit DMA Engine 2.8.1.6 Transmit FIFO 2.8.1.7 MAC Transmitter 2.8.1.8 Statistics Logic 2.
www.ti.com 2.8.1.12 Clock and Reset Logic 2.8.2 EMAC Module Operational Overview EMAC Functional Architecture The clock and reset sub-module generates all the clocks and resets for the EMAC peripheral. After reset, initialization, and configuration of the EMAC, the application software running on the host may initiate transmit operations.
www.ti.com 2.9 Media Independent Interfaces 2.9.1 Data Reception 2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval 2.9.1.3 Receive Flow Control EMAC Functional Architecture The EMAC support.
www.ti.com 2.9.1.4 Collision-Based Receive Buffer Flow Control 2.9.1.5 IEEE 802.3X Based Receive Buffer Flow Control EMAC Functional Architecture Collision-based receive buffer flow control provides a means of preventing frame reception when the EMAC is operating in half-duplex mode (FULLDUPLEX bit is cleared in MACCONTROL register).
www.ti.com 2.9.2 Data Transmission 2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization (APO) 2.9.2.4 Interpacket-Gap (IPG) Enforcement 2.9.2.5 Back Off EMAC Functional Architecture The EMAC passes data to the PHY from the transmit FIFO (when enabled).
www.ti.com 2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support EMAC Functional Architecture When enabled, incoming pause frames are acted upon to prevent the EMAC from transmitting any further frames. Incoming pause frames are only acted upon when the FULLDUPLEX and TXFLOWEN bits in the MACCONTROL register are set.
www.ti.com 2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration 2.10.2 Receive Channel Enabling EMAC Functional Architecture To configure the receive DMA for operation, the host must pe.
www.ti.com 2.10.3 Receive Channel Addressing 2.10.4 Hardware Receive QOS Support EMAC Functional Architecture The receive address block can store up to 32 addresses to be filtered or matched. Before enabling packet reception, all the address RAM locations should be initialized, including locations to be unused.
www.ti.com 2.10.5 Host Free Buffer Tracking 2.10.6 Receive Channel Teardown 2.10.7 Receive Frame Classification EMAC Functional Architecture The host must track free buffers for each enabled channel (including unicast, multicast, broadcast, and promiscuous) if receive QOS or receive flow control is used.
www.ti.com 2.10.8 Promiscuous Receive Mode EMAC Functional Architecture When the promiscuous receive mode is enabled by setting the RXCAFEN bit in the RXMBPENABLE register, non-address matching frames that would normally be filtered are transferred to the promiscuous channel.
www.ti.com 2.10.9 Receive Overrun EMAC Functional Architecture Table 8. Receive Frame Treatment Summary (continued) RXMBPENABLE Bits ADDRESS MATCH RXCAFEN RXCEFEN RXCMFEN RXCSFEN Frame treatment 1 X 1 0 1 Proper/oversize/jabber/fragment/undersized/cod e/align/CRC data frames transferred to address match channel.
www.ti.com 2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration 2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency EMAC Functional Architecture The transmit DMA is an eight channel interface.
www.ti.com 2.13 Transfer Node Priority 2.14 Reset Considerations 2.14.1 Software Reset Considerations 2.14.2 Hardware Reset Considerations EMAC Functional Architecture Latency to system’s internal and external RAM can be controlled through the use of the transfer node priority allocation register in the C645x devices.
www.ti.com 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization EMAC Functional Architecture When the device is powered on, the EMAC peripheral is disabled.
www.ti.com 2.15.3 MDIO Module Initialization EMAC Functional Architecture Example 4. EMAC Control Module Initialization Code Uint32 tmpval; /* // Globally disable EMAC/MDIO interrupts in the control m.
www.ti.com 2.15.4 EMAC Module Initialization EMAC Functional Architecture The EMAC module sends and receives data packets over the network by maintaining up to 8 transmit and receive descriptor queues. The EMAC module configuration must also be kept current based on the PHY negotiation results returned from the MDIO module.
www.ti.com 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Transmit Packet Completion Interrupts EMAC Functional Architecture The EMAC/MDIO generates 18 interrupt even.
www.ti.com 2.16.1.2 Receive Packet Completion Interrupts 2.16.1.3 Statistics Interrupt EMAC Functional Architecture The receive DMA engine has eight channels, and each channel has a corresponding interrupt (RXPEND n ). The receive interrupts are level interrupts that remain asserted until cleared by the CPU.
www.ti.com 2.16.1.4 Host Error Interrupt 2.16.2 MDIO Module Interrupt Events and Requests 2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt EMAC Functional Architecture The host.
www.ti.com 2.16.3 Proper Interrupt Processing 2.16.4 Interrupt Multiplexing 2.17 Power Management 2.18 Emulation Considerations EMAC Functional Architecture All the interrupts signaled from the EMAC and MDIO modules are level-driven. If they remain active, their level remains constant.
www.ti.com 3 EMAC Control Module Registers 3.1 Introduction 3.2 EMAC Control Module Interrupt Control Register (EWCTL) EMAC Control Module Registers Table 11 lists the memory-mapped registers for the EMAC Control Module. See the device-specific data manual for the memory address of these registers.
www.ti.com 3.3 EMAC Control Module Interrupt Timer Count Register (EWINTTCNT) EMAC Control Module Registers The EMAC control module interrupt timer count register (EWINTTCNT) is used to control the generation of back-to-back interrupts from the EMAC and MDIO modules.
www.ti.com 4 MDIO Registers 4.1 Introduction MDIO Registers Table 14 lists the memory-mapped registers for the Management Data Input/Output (MDIO). See the device-specific data manual for the memory address of these registers.
www.ti.com 4.2 MDIO Version Register (VERSION) MDIO Registers The MDIO version register (VERSION) is shown in Figure 16 and described in Table 15 . Figure 16. MDIO Version Register (VERSION) 31 16 MODID R-7 15 8 7 0 REVMAJ REVMIN R-1 R-3 LEGEND: R = Read only; R/W = Read/Write; - n = value after reset Table 15.
www.ti.com 4.3 MDIO Control Register (CONTROL) MDIO Registers The MDIO control register (CONTROL) is shown in Figure 17 and described in Table 16 . Figure 17.
www.ti.com 4.4 PHY Acknowledge Status Register (ALIVE) MDIO Registers The PHY acknowledge status register (ALIVE) is shown in Figure 18 and described in Table 17 . Figure 18. PHY Acknowledge Status Register (ALIVE) 31 16 ALIVE R/WC-0 15 0 ALIVE R/WC-0 LEGEND: R/W = Read/Write; R/WC = Read/Write 1 to clear; - n = value after reset Table 17.
www.ti.com 4.5 PHY Link Status Register (LINK) MDIO Registers The PHY link status register (LINK) is shown in Figure 19 and described in Table 18 . Figure 19. PHY Link Status Register (LINK) 31 16 LINK R-0 15 0 LINK R-0 LEGEND: R = Read only; - n = value after reset Table 18.
www.ti.com 4.6 MDIO Link Status Change Interrupt (Unmasked) Register (LINKINTRAW) MDIO Registers The MDIO link status change interrupt (unmasked) register (LINKINTRAW) is shown in Figure 20 and described in Table 19 .
www.ti.com 4.7 MDIO Link Status Change Interrupt (Masked) Register (LINKINTMASKED) MDIO Registers The MDIO link status change interrupt (masked) register (LINKINTMASKED) is shown in Figure 21 and described in Table 20 .
www.ti.com 4.8 MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW) MDIO Registers The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 22 and described in Table 21 .
www.ti.com 4.9 MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED) MDIO Registers The MDIO user command complete interrupt (Masked) register (USERINTMASKED) is shown in Figure 23 and described in Table 22 .
www.ti.com 4.10 MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET) MDIO Registers The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 24 and described in Table 23 .
www.ti.com 4.11 MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR) MDIO Registers The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 25 and described in Table 24 .
www.ti.com 4.12 MDIO User Access Register 0 (USERACCESS0) MDIO Registers The MDIO user access register 0 (USERACCESS0) is shown in Figure 26 and described in Table 25 .
www.ti.com 4.13 MDIO User PHY Select Register 0 (USERPHYSEL0) MDIO Registers The MDIO user PHY select register 0 (USERPHYSEL0) is shown in Figure 27 and described in Table 26 .
www.ti.com 4.14 MDIO User Access Register 1 (USERACCESS1) MDIO Registers The MDIO user access register 1 (USERACCESS1) is shown in Figure 28 and described in Table 27 .
www.ti.com 4.15 MDIO User PHY Select Register 1 (USERPHYSEL1) MDIO Registers The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 29 and described in Table 28 .
www.ti.com 5 EMAC Port Registers 5.1 Introduction EMAC Port Registers Table 29 lists the memory-mapped registers for the Ethernet Media Access Controller (EMAC).
www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 15Ch RX7FREEBUFFER Receive Channel 7 Free Buffer Count Register Section 5.28 160h MACCONTROL MAC Control Register Section 5.
www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 658h TX6CP Transmit Channel 6 Completion Pointer (Interrupt Section 5.48 Acknowledge) Register 65Ch TX7CP Transmit Channel 7 Completion Pointer (Interrupt Section 5.
www.ti.com EMAC Port Registers Table 29. Ethernet Media Access Controller (EMAC) Registers (continued) Offset Acronym Register Description Section 270h FRAME128T255 Transmit and Receive 128 to 255 Octet Frames Register Section 5.50.29 274h FRAME256T511 Transmit and Receive 256 to 511 Octet Frames Register Section 5.
www.ti.com 5.2 Transmit Identification and Version Register (TXIDVER) EMAC Port Registers The transmit identification and version register (TXIDVER) is shown in Figure 30 and described in Table 30 .
www.ti.com 5.3 Transmit Control Register (TXCONTROL) EMAC Port Registers The transmit control register (TXCONTROL) is shown in Figure 31 and described in Table 31 . Figure 31. Transmit Control Register (TXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved TXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 31.
www.ti.com 5.4 Transmit Teardown Register (TXTEARDOWN) EMAC Port Registers The transmit teardown register (TXTEARDOWN) is shown in Figure 32 and described in Table 32 . Figure 32. Transmit Teardown Register (TXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved TXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 32.
www.ti.com 5.5 Receive Identification and Version Register (RXIDVER) EMAC Port Registers The receive identification and version register (RXIDVER) is shown in Figure 33 and described in Table 33 .
www.ti.com 5.6 Receive Control Register (RXCONTROL) EMAC Port Registers The receive control register (RXCONTROL) is shown in Figure 34 and described in Table 34 . Figure 34. Receive Control Register (RXCONTROL) 31 16 Reserved R-0 15 1 0 Reserved RXEN R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 34.
www.ti.com 5.7 Receive Teardown Register (RXTEARDOWN) EMAC Port Registers The receive teardown register (RXTEARDOWN) is shown in Figure 35 and described in Table 35 . Figure 35. Receive Teardown Register (RXTEARDOWN) 31 16 Reserved R-0 15 3 2 0 Reserved RXTDNCH R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 35.
www.ti.com 5.8 Transmit Interrupt Status (Unmasked) Register (TXINTSTATRAW) EMAC Port Registers The transmit interrupt status (unmasked) register (TXINTSTATRAW) is shown in Figure 36 and described in Table 36 .
www.ti.com 5.9 Transmit Interrupt Status (Masked) Register (TXINTSTATMASKED) EMAC Port Registers The transmit interrupt status (Masked) register (TXINTSTATMASKED) is shown in Figure 37 and described in Table 37 .
www.ti.com 5.10 Transmit Interrupt Mask Set Register (TXINTMASKSET) EMAC Port Registers The transmit interrupt mask set register (TXINTMASKSET) is shown in Figure 38 and described in Table 38 .
www.ti.com 5.11 Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) EMAC Port Registers The transmit interrupt mask clear register (TXINTMASKCLEAR) is shown in Figure 39 and described in Table 39 .
www.ti.com 5.12 MAC Input Vector Register (MACINVECTOR) EMAC Port Registers The MAC input vector register (MACINVECTOR) is shown in Figure 40 and described in Table 40 .
www.ti.com 5.13 Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) EMAC Port Registers The receive interrupt status (Unmasked) register (RXINTSTATRAW) is shown in Figure 41 and described in Table 41 .
www.ti.com 5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) EMAC Port Registers The receive interrupt status (Masked) register (RXINTSTATMASKED) is shown in Figure 42 and described in Table 42 .
www.ti.com 5.15 Receive Interrupt Mask Set Register (RXINTMASKSET) EMAC Port Registers The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 43 and described in Table 43 .
www.ti.com 5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) EMAC Port Registers The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 44 and described in Table 44 .
www.ti.com 5.17 MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) EMAC Port Registers The MAC interrupt status (unmasked) register (MACINTSTATRAW) is shown in Figure 45 and described in Table 45 .
www.ti.com 5.18 MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) EMAC Port Registers The MAC interrupt status (masked) register (MACINTSTATMASKED) is shown in Figure 46 and described in Table 46 .
www.ti.com 5.19 MAC Interrupt Mask Set Register (MACINTMASKSET) EMAC Port Registers The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 47 and described in Table 47 .
www.ti.com 5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) EMAC Port Registers The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 48 and described in Table 48 .
www.ti.com 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) EMAC Port Registers The receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) is shown in Figure 49 and described in Table 49 . Figure 49.
www.ti.com EMAC Port Registers Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (continued) Bit Field Value Description 22 RXCEFEN Receive copy error frames enable bit. Enables frames containing errors to be transferred to memory.
www.ti.com 5.22 Receive Unicast Enable Set Register (RXUNICASTSET) EMAC Port Registers Table 49. Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) Field Descriptions (conti.
www.ti.com 5.23 Receive Unicast Clear Register (RXUNICASTCLEAR) EMAC Port Registers The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 51 and described in Table 51 .
www.ti.com 5.24 Receive Maximum Length Register (RXMAXLEN) EMAC Port Registers The receive maximum length register (RXMAXLEN) is shown in Figure 52 and described in Table 52 . Figure 52. Receive Maximum Length Register (RXMAXLEN) 31 16 Reserved R-0 15 0 RXMAXLEN R/W-1518 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 52.
www.ti.com 5.25 Receive Buffer Offset Register (RXBUFFEROFFSET) EMAC Port Registers The receive buffer offset register (RXBUFFEROFFSET) is shown in Figure 53 and described in Table 53 .
www.ti.com 5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) EMAC Port Registers The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 54 and described in Table 54 .
www.ti.com 5.27 Receive Channel 0-7 Flow Control Threshold Register (RX nFLOWTHRESH) EMAC Port Registers The receive channel 0-7 flow control threshold register (RX n FLOWTHRESH) is shown in Figure 55 and described in Table 55 .
www.ti.com 5.28 Receive Channel 0-7 Free Buffer Count Register (RXnFREEBUFFER) EMAC Port Registers The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 56 and described in Table 56 .
www.ti.com 5.29 MAC Control Register (MACCONTROL) EMAC Port Registers The MAC control register (MACCONTROL) is shown in Figure 57 and described in Table 57 .
www.ti.com EMAC Port Registers Table 57. MAC Control Register (MACCONTROL) Field Descriptions (continued) Bit Field Value Description 1 Receive flow control enabled. For full-duplex mode, outgoing pause frames are sent when receive FIFO flow control is triggered.
www.ti.com 5.30 MAC Status Register (MACSTATUS) EMAC Port Registers The MAC status register (MACSTATUS) is shown in Figure 58 and described in Table 58 .
www.ti.com EMAC Port Registers Table 58. MAC Status Register (MACSTATUS) Field Descriptions (continued) Bit Field Value Description 15-12 RXERRCODE Receive host error code. These bits indicate that EMAC detected receive DMA related host errors. The host should read this field after a host error interrupt (HOSTPEND) to determine the error.
www.ti.com 5.31 Emulation Control Register (EMCONTROL) EMAC Port Registers The emulation control register (EMCONTROL) is shown in Figure 59 and described in Table 59 .
www.ti.com 5.32 FIFO Control Register (FIFOCONTROL) EMAC Port Registers The FIFO control register (FIFOCONTROL) is shown in Figure 60 and described in Table 60 .
www.ti.com 5.33 MAC Configuration Register (MACCONFIG) EMAC Port Registers The MAC configuration register (MACCONFIG) is shown in Figure 61 and described in Table 61 .
www.ti.com 5.34 Soft Reset Register (SOFTRESET) EMAC Port Registers The Soft Reset Register (SOFTRESET) is shown in Figure 62 and described in Table 62 . Figure 62. Soft Reset Register (SOFTRESET) 31 16 Reserved R-0 15 1 0 Reserved SOFTRESET R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 62.
www.ti.com 5.35 MAC Source Address Low Bytes Register (MACSRCADDRLO) EMAC Port Registers The MAC source address low bytes register (MACSRCADDRLO) is shown in Figure 63 and described in Table 63 .
www.ti.com 5.36 MAC Source Address High Bytes Register (MACSRCADDRHI) EMAC Port Registers The MAC Source Address High Bytes Register (MACSRCADDRHI) is shown in Figure 64 and described in Table 64 .
www.ti.com 5.37 MAC Hash Address Register 1 (MACHASH1) EMAC Port Registers The MAC hash registers allow group addressed frames to be accepted on the basis of a hash function of the address.
www.ti.com 5.38 MAC Hash Address Register 2 (MACHASH2) EMAC Port Registers The MAC hash address register 2 (MACHASH2) is shown in Figure 66 and described in Table 66 . Figure 66. MAC Hash Address Register 2 (MACHASH2) 31 16 MACHASH2 R/W-0 15 0 MACHASH2 R/W-0 LEGEND: R/W = Read/Write; - n = value after reset Table 66.
www.ti.com 5.39 Back Off Test Register (BOFFTEST) EMAC Port Registers The back off test register (BOFFTEST) is shown in Figure 67 and described in Table 67 .
www.ti.com 5.40 Transmit Pacing Algorithm Test Register (TPACETEST) EMAC Port Registers The Transmit Pacing Algorithm Test Register (TPACETEST) is shown in Figure 68 and described in Table 68 .
www.ti.com 5.41 Receive Pause Timer Register (RXPAUSE) EMAC Port Registers The receive pause timer register (RXPAUSE) is shown in Figure 69 and described in Table 69 . Figure 69. Receive Pause Timer Register (RXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 69.
www.ti.com 5.42 Transmit Pause Timer Register (TXPAUSE) EMAC Port Registers The Transmit Pause Timer Register (TXPAUSE) is shown in Figure 70 and described in Table 70 . Figure 70. Transmit Pause Timer Register (TXPAUSE) 31 16 Reserved R-0 15 0 PAUSETIMER R-0 LEGEND: R = Read only; - n = value after reset Table 70.
www.ti.com 5.43 MAC Address Low Bytes Register (MACADDRLO) EMAC Port Registers The MAC address low bytes register (MACADDRLO) is shown in Figure 71 and described in Table 71 .
www.ti.com 5.44 MAC Address High Bytes Register (MACADDRHI) EMAC Port Registers The MAC address high bytes register (MACADDRHI) is shown in Figure 72 and described in Table 72 .
www.ti.com 5.45 MAC Index Register (MACINDEX) EMAC Port Registers The MAC index register (MACINDEX) is shown in Figure 73 and described in Table 73 . Figure 73. MAC Index Register (MACINDEX) 31 16 Reserved R-0 15 5 4 0 Reserved MACINDEX R-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; - n = value after reset Table 73.
www.ti.com 5.46 Transmit Channel 0-7 DMA Head Descriptor Pointer Register (TXnHDP) EMAC Port Registers The transmit channel 0-7 DMA head descriptor pointer register (TXnHDP) is shown in Figure 74 and described in Table 74 .
www.ti.com 5.47 Receive Channel 0-7 DMA Head Descriptor Pointer Register (RXnHDP) EMAC Port Registers The receive channel 0-7 DMA head descriptor pointer register (RXnHDP) is shown in Figure 75 and described in Table 75 .
www.ti.com 5.48 Transmit Channel 0-7 Completion Pointer Register (TX nCP) EMAC Port Registers The Transmit Channel 0-7 Completion Pointer Register (TX n CP) is shown in Figure 76 and described in Table 76 .
www.ti.com 5.49 Receive Channel 0-7 Completion Pointer Register (RX nCP) EMAC Port Registers The receive channel 0-7 completion pointer register (RX n CP) is shown in Figure 77 and described in Table 77 .
www.ti.com 5.50 Network Statistics Registers 5.50.1 Good Receive Frames Register (RXGOODFRAMES) 5.50.2 Broadcast Receive Frames Register (RXBCASTFRAMES) EMAC Port Registers The EMAC has a set of statistics that record events associated with frame traffic.
www.ti.com 5.50.3 Multicast Receive Frames Register (RXMCASTFRAMES) 5.50.4 Pause Receive Frames Register (RXPAUSEFRAMES) 5.50.5 Receive CRC Errors Register (RXCRCERRORS) 5.50.6 Receive Alignment/Code Errors Register (RXALIGNCODEERRORS) EMAC Port Registers The total number of good multicast frames received on the EMAC.
www.ti.com 5.50.7 Receive Oversized Frames Register (RXOVERSIZED) 5.50.8 Receive Jabber Frames Register (RXJABBER) 5.50.9 Receive Undersized Frames Register (RXUNDERSIZED) 5.50.10 Receive Frame Fragments Register (RXFRAGMENTS) EMAC Port Registers The total number of oversized frames received on the EMAC.
www.ti.com 5.50.11 Filtered Receive Frames Register (RXFILTERED) 5.50.12 Receive QOS Filtered Frames Register (RXQOSFILTERED) 5.50.13 Receive Octet Frames Register (RXOCTETS) 5.
www.ti.com 5.50.15 Broadcast Transmit Frames Register (TXBCASTFRAMES) 5.50.16 Multicast Transmit Frames Register (TXMCASTFRAMES) 5.50.17 Pause Transmit Frames Register (TXPAUSEFRAMES) 5.
www.ti.com 5.50.20 Transmit Single Collision Frames Register (TXSINGLECOLL) 5.50.21 Transmit Multiple Collision Frames Register (TXMULTICOLL) 5.50.22 Transmit Excessive Collision Frames Register (TXEXCESSIVECOLL) 5.50.23 Transmit Late Collision Frames Register (TXLATECOLL) 5.
www.ti.com 5.50.25 Transmit Carrier Sense Errors Register (TXCARRIERSENSE) 5.50.26 Transmit Octet Frames Register (TXOCTETS) 5.50.27 Transmit and Receive 64 Octet Frames Register (FRAME64) 5.50.28 Transmit and Receive 65 to 127 Octet Frames Register (FRAME65T127) 5.
www.ti.com 5.50.30 Transmit and Receive 256 to 511 Octet Frames Register (FRAME256T511) 5.50.31 Transmit and Receive 512 to 1023 Octet Frames Register (FRAME512T1023) 5.50.32 Transmit and Receive 1024 to RXMAXLEN Octet Frames Register (FRAME1024TUP) 5.
www.ti.com 5.50.34 Receive FIFO or DMA Start of Frame Overruns Register (RXSOFOVERRUNS) 5.50.35 Receive FIFO or DMA Middle of Frame Overruns Register (RXMOFOVERRUNS) 5.
www.ti.com Appendix A Glossary Appendix A Broadcast MAC Address — A special Ethernet MAC address used to send data to all Ethernet devices on the local network. The broadcast address is FFh-FFh-FFh-FFh-FFh-FFh. The LSB of the first byte is odd, qualifying it as a group address; however, its value is reserved for broadcast.
www.ti.com Appendix A Jumbo Packets — Jumbo frames are defined as those packets whose length exceeds the standard Ethernet MTU, which is 1500 kbytes.
www.ti.com Appendix B Revision History Appendix B Table B-1 lists the changes made since the previous version of this document. Table B-1. Document Revision History Reference Additions/Modifications/Deletions Section 2.1 Changed Section 2.1 . Section 2.
IMPORT ANT NOTICE T exas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Texas Instruments TMS320C645x DSP c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Texas Instruments TMS320C645x DSP - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Texas Instruments TMS320C645x DSP, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Texas Instruments TMS320C645x DSP va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Texas Instruments TMS320C645x DSP, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Texas Instruments TMS320C645x DSP.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Texas Instruments TMS320C645x DSP. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Texas Instruments TMS320C645x DSP ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
