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SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual JANUARY 2008 SPRS462B.
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR Data Manual Literature Number: SPRS462B SEPTEMBER 2007 – Revised JANUARY 2008 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty.
Contents SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 1 Features .............................................................................................................................. 7 1.
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 6.2 Recommended Operating Conditions ..........
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.8.2 PLL2 Controller Memory Map ................................................................................ 153 7.8.3 PLL2 Controller Register Descriptions .
SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) ...................................................................... 221 7.17.1 TCP2 Device-Specific Information .
www.ti.com 1 Features SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Parameters • Controlled Baseline • Endianess: Little Endian, Big Endia.
www.ti.com 1.1 ZTZ/GTZ BGA Package (Bottom View) ZTZ/GTZ 697-PIN BALL GRID ARRA Y (BGA) P ACKAGE ( BOTT OM VIEW ) A 2 B 1 3 4 5 6 7 8 9 10 1 1 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 C D E F G H .
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .
www.ti.com 1.3 Functional Block Diagram L2 Memory Controller (Memory Protect/ Bandwidth Mgmt) Serial Rapid I/O DDR2 Mem Ctlr System (B) C64x+ DSP Core Data Path B B Register File B31−B16 B15−B0 Instruction Fetch Data Path A A Register File A31−A16 A15−A0 Device Configuration Logic .
www.ti.com 2 Device Overview 2.1 Device Characteristics SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-1 , provides an overview of the C6455 DSP.
www.ti.com 2.2 CPU (DSP Core) Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-1. Characteristics of the C6455 Processor (continued) HARDWARE FEATURES C6455 Process Technology µ m 0.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Other new features include: • SPLOOP - A small instruction buffer in the CPU that aids in creation of software pipelining loops where multiple iterations of a loop are executed in parallel.
www.ti.com src2 src2 .D1 .M1 .S1 .L1 long src odd dst src2 src1 src1 src1 src1 even dst even dst odd dst dst1 dst src2 src2 src2 long src DA1 ST1b LD1b LD1a ST1a Data path A Odd register file A (A1, A3, A5...A31) Odd register file B (B1, B3, B5...B31) .
www.ti.com 2.3 Memory Map Summary SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-2 shows the memory map address ranges of the C6455 device.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-2. C6455 Memory Map Summary (continued) MEMORY BLOCK DESCRIPTION BLOCK SIZE (.
www.ti.com 2.4 Boot Sequence 2.4.1 Boot Modes Supported SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The boot sequence is a process by which .
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 software such as Code Composer Studio. For the PCI host boot, the CPU is out of reset, but it executes an IDLE instruction until a DSP interrupt is generated by the host.
www.ti.com 2.4.2 2nd-Level Bootloaders SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SRIO boot is a software boot mode. Any of the boot modes can be used to download a 2nd-level bootloader.
www.ti.com 2.5 Pin Assignments 2.5.1 Pin Map AG AF AE AD AC AB AA Y W V U T R 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 CLKR1/ GP[0] HD15/ AD15 HD2/ AD2 URADDR0/ PGNT/ GP[12] HD22/.
www.ti.com AG AF AE AD AC AB AA Y W V U T R 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 SDA AED27 V SS ASADS/ ASRE AED17 AHOLD PLL V1 AEA13/ LENDIAN AEA4/ SYSCLKOUT _.
www.ti.com C D E F G H J K L M N P 17 18 19 20 21 22 23 24 25 26 27 28 29 17 18 19 20 21 22 23 24 25 26 27 28 29 RSV09 AED52 DV DD 33 V SS V SS V SS AECLKIN AEA9/ MACSEL0 CLKIN1 DV DD 33 AEA15/ AECLKI.
www.ti.com A D E F G H J K L M N P 13 12 1 1 10 9 8 7 6 5 4 3 2 1 13 12 1 1 10 9 8 7 6 5 4 3 2 1 RGRXD2 RGTXD3 DV DD 33 UXDA T A2/ MTXD2 V SS UXDA T A0/ MTXD0/ RMTXD0 CV DD MON UXDA T A6/ MTXD6 V SS U.
www.ti.com 2.6 Signal Groups Description • TRST IEEE Standard 1 149.1 (JT AG) Emulation Reserved Reset and Interrupts Control/Status TDI TDO TMS TCK NMI RESET RSV03 RSV04 Clock/PLL1 and PLL Controll.
www.ti.com A. This pin functions as GP[1] by default. For more details, see the Device Configuration section of this document. B. These McBSP1 peripheral pins are muxed with the GPIO peripheral pins and by default these signals function as GPIO peripheral pins.
www.ti.com ACE4 (A ) AECLKOUT AED[63:0] ACE3 (A ) ACE2 (A ) AEA[19:0] AARDY Data Memory Map Space Select Address Byte Enables 64 20 External Memory I/F Control EMIF A (64-bit Data Bus) AECLKIN AHOLD A.
www.ti.com McBSPs (Multichannel Buffered Serial Ports) (B) CLKX0 FSX0 DX0 CLKR0 FSR0 DR0 T ransmit McBSP0 Receive Clock CLKX1/GP[3] FSX1/GP[1 1] DX1/GP[9] CLKR1/GP[0] FSR1/GP[10] DR1/GP[8] T ransmit M.
www.ti.com RGTXCTL, RGRXCTL URSOC/MRXER/RMRXER, URENB/MRXDV , URCLA V/MCRS/RMCRSDV , UXSOC/MCOL, UXENB/MTXEN/RMTXEN Ethernet MAC (EMAC) and MDIO (B) UXADDR3/MDIO UXADDR4/MDCLK MDIO Clock Clocks Error Detect and Control Input/Output Receive RGMDIO RGMDCLK RGTXD[3:0] A.
www.ti.com URADDR2/PINT A/GP[14] Control/Status URADDR4/PCLK/GP[2] URDA T A0/MRXD0/RMRXD0 URDA T A1/MRXD1/RMRXD1 URADDR3/PREQ /GP[15] URADDR1/PRST /GP[13] URADDR0/PGNT /GP[12] Receive URDA T A7/MRXD7 .
www.ti.com 2.7 Terminal Functions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The terminal functions table ( Table 2-3 ) identifies the exte.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. Reserved. This pin must be connected to ground (V SS ) via a 200- Ω resistor for proper device operation.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. SUPPLY VOLTAGE MONITOR PINS Die-side 1.2-V core supply (CV DD ) voltage monitor pin.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. U16 SRIO interface supply: 1.25-V core supply voltage (-1000 and -1200 devices) V15 DV DDRM S 1.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. A29 E26 E28 G2 H23 H28 J6 J24 K1 K7 K23 L24 M7 M23 M28 N24 P6 P28 R1 R6 R23 DV DD33 T7 S 3.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. AD5 AD7 AD14 AD18 AD22 AD24 AE6 AE8 AE15 AF1 AF16 DV DD33 AF24 S 3.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO. R18 T11 T13 T15 T17 T19 U12 1.25-V core supply voltage (-1000 and -1200 devices) CV DD S 1.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 2-3. Terminal Functions (continued) SIGNAL TYPE (1) IPD/IPU (2) DESCRIPTION NAME NO.
www.ti.com 2.8 Development 2.8.1 Development Support 2.8.2 Device Support 2.8.2.1 Device and Development-Support Tool Nomenclature SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTE.
www.ti.com SM=Qualifieddevice SM=HiRel(non-38535) A = 40 C to 1 05 C ( exten ded tem perat ure) - º º S = 55 C to 105 C (exten ded tem perat ure) - º º 2.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 C6000 DSP platforms. SPRU970 TMS320C645x DSP DDR2 Memory Controller User's Guide. This document describes the DDR2 memory controller in the C645x digital-signal processors (DSPs).
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 signal processor (DSPs) of the C6000™ DSP family has been designed to perform this operation for IS2000 and 3GPP wireless standards. This document describes the operation and programming of the TCP.
www.ti.com 3 Device Configuration 3.1 Device Configuration at Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, certain device configurations like boot mode, pin multiplexing, and endianess, are selected at device reset.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO. FUNCTIONAL DESCRIPTION PIN IPU (1) HPI peripheral bus width select (HPI_WIDTH).
www.ti.com 3.2 Peripheral Configuration at Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-1. C6455 Device Configuration Pins (AEA[19:0], ABA[1:0], and PCI_EN) (continued) CONFIGURATION IPD/ NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-2. PCI_EN, PCI66, PCI_EEAI, and HPI_WIDTH Peripheral Selection (HPI and PCI) .
www.ti.com 3.3 Peripheral Selection After Device Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, peripherals can be in one of several states. These states are listed in Table 3-4 .
www.ti.com Reset Static Powerdown Disabled Enable In Progress Enabled Unlock the PERCFG0 register by using the PERLOCK register . W rite to the PERCFG0 register within 16 SYSCLK3 clock cycles to change the state of the peripherals. Poll the PERST A T registers to verify state change.
www.ti.com 3.4 Device State Control Registers SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device has a set of registers that are used to control the status of its peripherals. These registers are shown in Table 3-5 and described in the next sections.
www.ti.com 3.4.1 Peripheral Lock Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 When written with correct 32 bit key (0x0F0A0B00), the Peripheral Lock Register (PERLOCK) allows one write to the PERCFG0 register within 16 SYSCLK3 cycles.
www.ti.com 3.4.2 Peripheral Configuration Register 0 Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Configuration Register (PERCFG0) is used to change the state of the peripherals.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-7. Peripheral Configuration Register 0 (PERCFG0) Field Descriptions (continued) Bit Field Value Description 16 McBSP1CTL Mode control for McBSP1 0 Set McBSP1 to disabled mode 1 Set McBSP1 to enabled mode 15 Reserved Reserved.
www.ti.com 3.4.3 Peripheral Configuration Register 1 Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Configuration Register (PERCFG1) is used to enable the EMIFA and DDR2 Memory Controller.
www.ti.com 3.4.4 Peripheral Status Registers Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Peripheral Status Registers (PERSTAT0 and PERSTAT1) show the status of the C6455 peripherals.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-9. Peripheral Status Register 0 (PERSTAT0) Field Descriptions (continued) Bit.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 31 16 Reserved R-0 15 6 5 3 2 0 Reserved UTOPIASTAT PCISTAT R-0 R-0 R-0 LEGEND: R = Read only; - n = value after reset Figure 3-7. Peripheral Status Register 1 (PERSTAT1) - 0x02AC 0018 Table 3-10.
www.ti.com 3.4.5 EMAC Configuration Register (EMACCFG) Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The EMAC Configuration Register (EMACCFG) is used to assert and deassert the reset of the Reduced Media Independent Interface (RMII) logic of the EMAC.
www.ti.com 3.4.6 Emulator Buffer Powerdown Register (EMUBUFPD) Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Emulator Buffer Powerdown Register (EMUBUFPD) is used to control the state of the pin buffers of emulator pins EMU[18:2].
www.ti.com 3.5 Device Status Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The device status register depicts the device configuration selected upon device reset. Once set, these bits will remain set until a device reset.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-13. Device Status Register (DEVSTAT) Field Descriptions (continued) Bit Field.
www.ti.com 3.6 JTAG ID (JTAGID) Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 3-13.
www.ti.com 3.7 Pullup/Pulldown Resistors 3.8 Configuration Examples SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Proper board design should ensure that input pins to the C6455 device always be at a valid logic level and not floating.
www.ti.com Shadingdenotesaperipheralmodulenotavailableforthisconfiguration. UTOPIA McBSP0 TIMER0 EMIF A GPIO PLL2 andPLL2 Controller TIMER1 PLL1 andPLL1 Controller DDR.
www.ti.com Shadingdenotesaperipheralmodulenotavailableforthisconfiguration. UTOPIA McBSP0 TIMER0 EMIF A GPIO TIMER1 PLL1 andPLL1 Controller DDR2 EMIF VCP2 AED[63:0] 64 AE.
www.ti.com 4 System Interconnect 4.1 Internal Buses, Bridges, and Switch Fabrics SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, the C64x+ Megamodule, the EDMA3 transfer controllers, and the system peripherals are interconnected through two switch fabrics.
www.ti.com 4.2 Data Switch Fabric Connections SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 4-1 shows the connection between slaves and masters through the data switched central resource (SCR).
www.ti.com Serial RapidIO (Descriptor) EMAC HPI M M M 128-bit (SYSCLK2) M3 M0 S S M M M M S TCP2 VCP2 S McBSPs S UTOPIA S DDR2 Memory Controller S EMIF A S PCI S MASTER SLA VE S M Bridge CFG SCR S Bri.
www.ti.com 4.3 Configuration Switch Fabric SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 4-1.
www.ti.com Megamodule M CFG SCR S M M S TCP2 VCP2 S McBSPs S UTOPIA S T imers S HPI S PCI S S Bridge 7 GPIO S EMAC/MDIO M Data SCR S S I2C S S PLL Controllers (A) S S Device Configuration Registers (A.
www.ti.com 4.4 Bus Priorities SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 On the C6455 device, bus priority is programmable for each master. The register bit fields and default priority levels for C6455 bus masters are shown in Table 4-2 .
www.ti.com 5 C64x+ Megamodule A register file Data path 1 Data path 2 B register file D2 S2 xx xx M2 L2 Instruction decode M1 xx xx L1 S1 D1 16/32−bit instruction dispatch Instruction fetch SPLOOP b.
www.ti.com 4K bytes 8K bytes 16K bytes L1P memory 00E0 0000h 00E0 4000h 00E0 6000h 00E0 7000h 00E0 8000h direct mapped SRAM 1/2 dm 3/4 SRAM SRAM 7/8 All SRAM 000 001 010 01 1 100 Block base address L1.
www.ti.com 32K bytes 32K bytes 64K bytes 128K bytes 1840K bytes L2 memory 0080 0000h 009C 0000h 009E 0000h 009F 0000h 009F 8000h 00A0 0000h 7/8 SRAM 4-way cache 4-way cache SRAM 15/16 4-way 31/32 SRAM.
www.ti.com 5.2 Memory Protection 5.3 Bandwidth Management SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Memory protection allows an operating system to define who or what is authorized to access L1D, L1P, and L2 memory.
www.ti.com 5.4 Power-Down Control 5.5 Megamodule Resets SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C64x+ Megamodule supports the ability to power-down various parts of the C64x+ Megamodule.
www.ti.com 5.6 Megamodule Revision SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The version and revision of the C64x+ Megamodule can be read from the Megamodule Revision ID Register (MM_REVID) located at address 0181 2000h.
www.ti.com 5.7 C64x+ Megamodule Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-4. Megamodule Interrupt Registers (continued) HEX ADDRESS RANGE ACRONYM REGIS.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers HEX ADDRESS RANGE ACRONYM REGISTE.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE ACR.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-8. Megamodule Cache Configuration Registers (continued) HEX ADDRESS RANGE ACR.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-9. Megamodule L1/L2 Memory Protection Registers (continued) HEX ADDRESS RANGE.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 5-10. CPU Megamodule Bandwidth Management Registers HEX ADDRESS RANGE ACRONYM R.
www.ti.com 6 Device Operating Conditions 6.1 Absolute Maximum Ratings Over Operating Case Temperature Range (Unless 6.2 Recommended Operating Conditions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Otherwise Noted) (1) Supply voltage range: CV DD (2) -0.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Recommended Operating Conditions (continued) MIN NOM MAX UNIT V SS Supply ground 0 0 0 V 3.3 V pins (except PCI-capable and 2 V I2C pins) PCI-capable 0.
www.ti.com 6.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Operating Case Temperature (Unless Otherwise Noted) PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT 3.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Ca.
www.ti.com 7 C64x+ Peripheral Information and Electrical Specifications 7.1 Parameter Information T ransmission Line 4.0 pF 1.85 pF Z0 = 50 Ω (see Note) T ester Pin Electronics Data Sheet T iming Reference Point Output Under T est NOTE: This data sheet provides timing at the device pin.
www.ti.com 7.1.3 Timing Parameters and Board Routing Analysis 1 2 3 4 5 6 7 8 10 1 1 AECLKOUT (Output from DSP) AECLKOUT (Input to External Device) Control Signals (A) (Output from DSP) Control Signal.
www.ti.com 7.2 Recommended Clock and Control Signal Transition Behavior 7.3 Power Supplies 7.3.1 Power-Supply Sequencing DV DD33 CV DD12 All other power supplies 1 2 7.
www.ti.com 7.3.4 Preserving Boundary-Scan Functionality on RGMII and DDR2 Memory Pins SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Peripherals used for booting, like I2C and HPI, are automatically enabled after device reset.
www.ti.com 7.4 Enhanced Direct Memory Access (EDMA3) Controller SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-mapped slave endpoints on the device.
www.ti.com 7.4.1 EDMA3 Device-Specific Information 7.4.2 EDMA3 Channel Synchronization Events SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The EDMA supports two addressing modes: constant addressing and increment addressing mode.
www.ti.com 7.4.3 EDMA3 Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-3.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM R.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM R.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM R.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM R.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM R.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-4. EDMA3 Channel Controller Registers (continued) HEX ADDRESS RANGE ACRONYM R.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-5. EDMA3 Parameter RAM (1) HEX ADDRESS RANGE ACRONYM REGISTER NAME 02A0 4000 .
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-6. EDMA3 Transfer Controller 0 Registers (continued) HEX ADDRESS RANGE ACRONY.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-7. EDMA3 Transfer Controller 1 Registers (continued) HEX ADDRESS RANGE ACRONY.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE ACRONY.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-8. EDMA3 Transfer Controller 2 Registers (continued) HEX ADDRESS RANGE ACRONY.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-9. EDMA3 Transfer Controller 3 Registers (continued) HEX ADDRESS RANGE ACRONY.
www.ti.com 7.5 Interrupts 7.5.1 Interrupt Sources and Interrupt Controller SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The CPU interrupts on the C6455 device are configured through the C64x+ Megamodule Interrupt Controller.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-10. C6455 System Event Mapping (continued) EVENT NUMBER INTERRUPT EVENT DESCRIPTION 41 XINT0 McBSP0 transmit interrupt 42 RINT1 McBSP1 receive interrupt 43 XINT1 McBSP1 transmit interrupt 44 - 50 Reserved Reserved.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-10. C6455 System Event Mapping (continued) EVENT NUMBER INTERRUPT EVENT DESCRIPTION Reserved. These system events are not connected and, therefore, 102 - 112 Reserved not used.
www.ti.com 7.5.2 External Interrupts Electrical Data/Timing 2 1 NMI SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-11. Timing Requirements for External Interrupts (1) (see Figure 7-6 ) -720 -850 A-1000/-1000 NO.
www.ti.com 7.6 Reset Controller 7.6.1 Power-on Reset ( POR Pin) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The reset controller detects the different type of resets supported on the C6455 device and manages the distribution of those resets throughout the device.
www.ti.com 7.6.2 Warm Reset ( RESET Pin) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 all the system clocks are invalid at this point. – The RESETSTAT pin stays asserted (low), indicating the device is in reset.
www.ti.com 7.6.3 Max Reset 7.6.4 System Reset 7.6.5 CPU Reset SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Section 2.4 , Boot Sequence ). NOTE The POR pin should be held inactive (high) throughout the Warm Reset sequence.
www.ti.com 7.6.6 Reset Priority SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 If any of the above reset sources occur simultaneously, the PLLCTRL only processes the highest priority reset request.
www.ti.com 7.6.7 Reset Controller Register 7.6.7.1 Reset Type Status Register Description SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The reset type status (RSTYPE) register (029A 00E4) is the only register for the reset controller.
www.ti.com 7.6.8 Reset Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-14. Timing Requirements for Reset (1) (2) (3) (see Figure 7-8 and Figure 7-9 ) -720 -850 A-1000/-1000 NO.
www.ti.com CLKIN1 PCLK RESET RESETST A T SYSREFCLK (PLL1C) Z Group POR SYSCLK3 SYSCLK4 SYSCLK5 AECLKOUT (Internal) Boot and Device Configuration Pins Low Group High Group CLKIN2 Internal Reset PLL2C S.
www.ti.com CLKIN1 CLKIN2 POR RESET (A)(B) RESETST A T Boot and Device Configuration Pins (C) 9 7 6 8 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. RESET should only be used after device has been powered up.
www.ti.com 7.7 PLL1 and PLL1 Controller SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The primary PLL controller generates the input clock to .
www.ti.com 1 0 0 1 DIVIDER D4 CLKIN1 (B) PLLEN (PLLCTL.[0]) SYSCLK2 SYSCLK3 AECLKIN (External EMIF Clock Input) EMIF A DIVIDER PREDIV DIVIDER D2 (A) DIVIDER D3 (A) AECLKOUT PLL V1 C2 C1 EMI Filter +1.
www.ti.com 7.7.1.2 PLL1 Controller Operating Modes 7.7.1.3 PLL1 Stabilization, Lock, and Reset Times SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 • SYSCLK4 is used as the internal clock for the EMIFA.
www.ti.com 7.7.2 PLL1 Controller Memory Map SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL lock time is the amount of time needed from when the PLL is taken out of reset (PLLRST = 1 with PLLEN = 0) to when to when the PLL controller can be switched to PLL mode (PLLEN = 1).
www.ti.com 7.7.3 PLL1 Controller Register Descriptions 7.7.3.1 PLL1 Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 This section provides a description of the PLL1 controller registers.
www.ti.com 7.7.3.2 PLL Multiplier Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL multiplier control register (PLLM) is shown in Figure 7-12 and described in Table 7-20 .
www.ti.com 7.7.3.3 PLL Pre-Divider Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL pre-divider control register (PREDIV) is shown in Figure 7-13 and described in Table 7-21 .
www.ti.com 7.7.3.4 PLL Controller Divider 4 Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller divider 4 register (PLLDIV4) is shown in Figure 7-14 and described in Table 7-22 .
www.ti.com 7.7.3.5 PLL Controller Divider 5 Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller divider 5 register (PLLDIV5) is shown in Figure 7-15 and described in Table 7-23 .
www.ti.com 7.7.3.6 PLL Controller Command Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-16 and described in Table 7-24 .
www.ti.com 7.7.3.7 PLL Controller Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller status register (PLLSTAT) shows the PLL controller status. PLLSTAT is shown in Figure 7-17 and described in Table 7-25 .
www.ti.com 7.7.3.8 PLL Controller Clock Align Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller clock align control register (ALNCTL) is shown in Figure 7-18 and described in Table 7-26 .
www.ti.com 7.7.3.9 PLLDIV Ratio Change Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Whenever a different ratio is written to the PLLDIV n registers, the PLLCTRL flags the change in the PLLDIV ratio change status registers (DCHANGE).
www.ti.com 7.7.3.10 SYSCLK Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SYSCLK status register (SYSTAT) shows the status of the system clocks (SYSCLK n ). SYSTAT is shown in Figure 7-20 and described in Table 7-28 .
www.ti.com 7.7.4 PLL1 Controller Input and Output Clock Electrical Data/Timing CLKIN1 2 3 4 4 5 1 SYSCLK4 3 4 4 2 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-29. Timing Requirements for CLKIN1 Devices (1) (2) (3) (see Figure 7-21 ) -720 -850 A-1000/-1000 -1200 NO.
www.ti.com 7.8 PLL2 and PLL2 Controller PLL V2 PLL2 SYSCLK2(FromPLL1Controller) SYSCLK1 DDR2 Memory Controller EMAC CLKIN2 (B)(C) C162 560 pF EMIFilter +1.
www.ti.com 7.8.1 PLL2 Controller Device-Specific Information 7.8.1.1 Internal Clocks and Maximum Operating Frequencies 7.8.1.2 PLL2 Controller Operating Modes SM320C6455-EP FIXED-POINT DIGITAL SIGNAL .
www.ti.com 7.8.2 PLL2 Controller Memory Map 7.8.3 PLL2 Controller Register Descriptions SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The memory map of the PLL2 controller is shown in Table 7-32 .
www.ti.com 7.8.3.1 PLL Controller Divider 1 Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller divider 1 register (PLLDIV1) is shown in Figure 7-24 and described in Table 7-33 .
www.ti.com 7.8.3.2 PLL Controller Command Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller command register (PLLCMD) contains the command bit for GO operation. PLLCMD is shown in Figure 7-25 and described in Table 7-34 .
www.ti.com 7.8.3.3 PLL Controller Status Register 7.8.3.4 PLL Controller Clock Align Control Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The PLL controller status register (PLLSTAT) shows the PLL controller status.
www.ti.com 7.8.3.5 PLLDIV Ratio Change Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Whenever a different ratio is written to the PLLDIV1 register, the PLLCTRL flags the change in the DCHANGE status register.
www.ti.com 7.8.3.6 SYSCLK Status Register SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The SYSCLK status register (SYSTAT) shows the status of the system clock (SYSCLK1). SYSTAT is shown in Figure 7-29 and described in Table 7-38 .
www.ti.com 7.8.4 PLL2 Controller Input Clock Electrical Data/Timing CLKIN2 2 3 4 4 5 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-39. Timing Requirements for CLKIN2 (1) (2) (3) (see Figure 7-30 ) -720 -850 A-1000/-1000 NO.
www.ti.com 7.9 DDR2 Memory Controller 7.9.1 DDR2 Memory Controller Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The 32 bit, 533-MHz (data rate) DDR2 Memory Controller bus of the C6455 is used to interface to JESD79D-2A standard-compliant DDR2 SDRAM devices.
www.ti.com 7.9.2 DDR2 Memory Controller Peripheral Register Description(s) 7.9.3 DDR2 Memory Controller Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-40.
www.ti.com 7.10 External Memory Interface A (EMIFA) 7.10.1 EMIFA Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The.
www.ti.com 7.10.2 EMIFA Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-41.
www.ti.com 7.10.3 EMIFA Electrical Data/Timing AECLKIN 2 3 4 4 5 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-42. Timing Requirements for AECLKIN for EMIFA (1) (2) (see Figure 7-31 ) -720 -850 A-1000/-1000 NO.
www.ti.com 5 6 2 AECLKIN AECLKOUT1 4 4 1 3 7.10.3.1 Asynchronous Memory Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-43. Switching Characteristics Over Recommended Operating Conditions for AECLKOUT for the EMIFA Module (1) (2) (3) (see Figure 7-32 ) -720 -850 A-1000/-1000 NO.
www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE ( A) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address Read Data Hold = 1 2 Strobe = 4 Setup = 1 2 2 4 10 10 1 1 1 3 A AAOE/ASOE and AAWE /ASWE operate as AAOE (identified under select signals) and AA WE , respectively , during asynchronous memory accesses.
www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ ABA[1:0] AED[63:0] AAOE/ASOE (A ) AR/W AA WE/ASWE ( A) AARDY (B ) Byte Enables Address W rite Data Hold = 1 12 Strobe = 4 Setup = 1 12 12 12 12 13 13 1 1 1.
www.ti.com 7.10.3.2 Programmable Synchronous Interface Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-46. Timing Requirements for Programmable Synchronous Interface Cycles for EMIFA Module (see Figure 7-36 ) -720 -850 A-1000/-1000 NO.
www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B ) AA WE/ASWE ( B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 9 1 4 5 8 9 6 7 3 1 2 BE1 BE2 BE3 BE4 EA1 EA2 EA4 8 READ latency =.
www.ti.com AECLKOUT ACEx ABE[7:0] AEA[19:0]/ABA[1:0] AED[63:0] ASADS/ASRE (B) AAOE/ASOE (B) AA WE /ASWE (B) BE1 BE2 BE3 BE4 Q1 Q2 Q3 1 1 3 12 10 4 2 1 8 5 8 EA1 EA2 EA3 EA4 10 W rite Latency = 1 (B) 1.
www.ti.com 7.10.4 HOLD/ HOLDA Timing HOLD HOLDA EMIF Bus (A) DSP Owns Bus External Requestor Owns Bus DSP Owns Bus DSP DSP 1 3 2 5 4 AECLKOUT SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-48.
www.ti.com 7.10.5 BUSREQ Timing AECLKOUTx 1 ABUSREQ 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-50. Switching Characteristics Over Recommended Operating Conditions for the BUSREQ Cycles for EMIFA Module (see Figure 7-40 ) -720 -850 A-1000/-1000 NO.
www.ti.com 7.11 I2C Peripheral 7.11.1 I2C Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The inter-integrated circu.
www.ti.com Clock Prescale I2CPSC Peripheral Clock (CPU/6) I2CCLKH Generator Bit Clock I2CCLKL Noise Filter SCL I2CXSR I2CDXR T ransmit T ransmit Shift T ransmit Buffer I2CDRR Shift I2CRSR Receive Buff.
www.ti.com 7.11.2 I2C Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-51.
www.ti.com 7.11.3 I2C Electrical Data/Timing 7.11.3.1 Inter-Integrated Circuits (I2C) Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-52. Timing Requirements for I2C Timings (1) (see Figure 7-42 ) -720 -850 A-1000/-1000 NO.
www.ti.com 10 8 4 3 7 12 5 6 14 2 3 13 Stop Start Repeated Start Stop SDA SCL 1 1 1 9 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-42. I2C Receive Timings Table 7-53. Switching Characteristics for I2C Timings (1) (see Figure 7-43 ) -720 -850 A-1000/-1000 NO.
www.ti.com 25 23 19 18 22 27 20 21 17 18 28 Stop Start Repeated Start Stop SDA SCL 16 26 24 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Figure 7-43.
www.ti.com 7.12 Host-Port Interface (HPI) Peripheral 7.12.1 HPI Device-Specific Information 7.12.2 HPI Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device includes a user-configurable 16 bit or 32 bit Host-port interface (HPI16/HPI32).
www.ti.com 7.12.3 HPI Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-55. Timing Requirements for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 A-1000/-1000 NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-56. Switching Characteristics for Host-Port Interface Cycles (1) (2) (see Table 7-56 through Figure 7-51 ) -720 -850 A-1000/-1000 NO.
www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 16 15 37 13 14 16 15 37 13 3 1 2 3 1 2 38 7 4 6 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS.
www.ti.com HCS HAS HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 2 3 1 37 9 10 14 2 38 12 1 1 12 1 1 12 1 1 13 7 6 1 3 13 37 9 10 36 HCNTL[1:0] 12 1 1 12 1 1 12 1 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A.
www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 34 5 17 18 17 18 34 5 4 38 37 13 16 15 14 13 16 15 37 35 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A. HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT( HDS1 XOR HDS2)] OR HCS.
www.ti.com HCS HAS HCNTL[1:0] HR/W HHWIL HSTROBE (A ) HD[15:0] HRDY (B) 5 34 17 18 13 10 12 9 37 12 12 1 1 1 1 1 1 17 18 14 1 1 1 1 1 1 37 10 9 13 12 12 12 5 34 38 35 36 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A.
www.ti.com 15 16 3 2 4 1 38 13 7 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A.
www.ti.com 36 1 1 10 12 9 1 38 13 2 3 6 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (output) HCNTL[1:0] (input) 7 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A.
www.ti.com 17 15 38 5 16 13 18 34 35 4 HCS (input) HAS (input) HSTROBE (A ) (input) HR/W (input) HRDY (B) (output) HD[31:0] (input) HCNTL[1:0] (input) 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A.
www.ti.com HRDY (B) (output) 5 1 1 9 17 18 34 HAS (input) HR/W (input) HSTROBE (A ) (input) HCS (input) 35 36 38 HD[31:0] (input) HCNTL[1:0] (input) 10 12 13 37 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 A.
www.ti.com 7.13 Multichannel Buffered Serial Port (McBSP) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The McBSP provides these functions: .
www.ti.com 7.13.1 McBSP Device-Specific Information 7.13.1.1 McBSP Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The CLKS signal is shared by both McBSP0 and McBSP1 on this device.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-58. McBSP 1 Registers HEX ADDRESS RANGE ACRONYM REGISTER NAME COMMENTS The CPU and EDMA controller can only read 0290 0000 DRR1 McBSP1 Data Receive Register via Configuration Bus this register; they cannot write to it.
www.ti.com 7.13.2 McBSP Electrical Data/Timing 7.13.2.1 Multichannel Buffered Serial Port (McBSP) Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-59. Timing Requirements for McBSP (1) (see Figure 7-52 ) -720 -850 A-1000/-1000 NO.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-60. Switching Characteristics Over Recommended Operating Conditions for McBSP (see Figure 7-52 ) (continued) -720 -850 A-1000/-1000 NO.
www.ti.com Bit(n-1) (n-2) (n-3) Bit 0 Bit(n-1) (n-2) (n-3) 14 12 1 1 10 9 3 3 2 8 7 6 5 4 4 3 1 3 2 CLKS CLKR FSR (int) FSR (ext) DR CLKX FSX (int) FSX (ext) FSX (XDA TDL Y=00b) DX 13 (A) 13 (A) 2 1 C.
www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-62.
www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 4 3 7 6 2 1 CLKX FSX DX DR 5 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-64.
www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 8 7 6 2 1 CLKX FSX DX DR SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-66.
www.ti.com Bit 0 Bit(n-1) (n-2) (n-3) (n-4) Bit 0 Bit(n-1) (n-2) (n-3) (n-4) 5 4 3 7 6 2 1 CLKX FSX DX DR SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-68.
www.ti.com 7.14 Ethernet MAC (EMAC) Configuration Bus DMA Memory T ransfer Controller Peripheral Bus EMAC Control Module EMAC Module MDIO Module MDIO Bus EMAC/MDIO Interrupt Interrupt Controller Ether.
www.ti.com 7.14.1 EMAC Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Modes The EMAC module on the C6455 .
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-70. EMAC/MDIO Multiplexed Pins (MII, RMII, and GMII Modes) BALL NUMBER DEVICE.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Interface Mode Clocking The on-chip PLL2 and PLL2 Controller generate the clocks to the EMAC module in RGMII or GMII mode.
www.ti.com 7.14.2 EMAC Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE ACRON.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-71. Ethernet MAC (EMAC) Control Registers (continued) HEX ADDRESS RANGE ACRON.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-72. EMAC Statistics Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER .
www.ti.com 7.14.3 EMAC Electrical Data/Timing 7.14.3.1 EMAC MII and GMII Electrical Data/Timing MRCLK (Input) 2 3 1 4 4 MTCLK (Input) 2 3 1 4 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-75.
www.ti.com GMTCLK (Output) 2 3 1 4 4 MRCLK (Input) 1 2 MRXD7−MRXD4(GMII only), MRXD3−MRXD0, MRXDV , MRXER (Inputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-77.
www.ti.com 1 MTCLK (Input) MTXD7−MTXD4(GMII only), MTXD3−MTXD0, MTXEN (Outputs) 1 GMTCLK (Output) MTXD7−MTXD0, MTXEN (Outputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-79.
www.ti.com 7.14.3.2 EMAC RMII Electrical Data/Timing RMREFCLK (Input) 1 2 3 3 1 RMREFCLK (Input) MTXD1-MTXD0, MTXEN (Outputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The RMREFCLK pin is used to source a clock to the EMAC when it is configured for RMII operation.
www.ti.com RMREFCLK (Input) 1 2 3 3 4 5 MRXD1-MRXD0, MCRSDV , MRXER (Inputs) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-83. Timing Requirements for EMAC RMII Input Receive for 100 Mbps (1) (see Figure 7-67 ) -720 -850 A-1000/-1000 NO.
www.ti.com 7.14.3.3 EMAC RGMII Electrical Data/Timing RGREFCLK (Output) 2 3 4 4 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 An extra clock signal, RGREFCLK, running at 125 MHz is included as a convenience to the user.
www.ti.com RXD[3:0] (A) RXCTL (A) RXC (at DSP) (B) 5 RXERR RXDV 6 1st Half-byte 2nd Half-byte RXD[7:4] RXD[3:0] 2 3 1 4 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-86.
www.ti.com TXC (at DSP) (B) TXD[3:0] (A) TXCTL (A) 5 6 1st Half-byte TXERR TXEN 2nd Half-byte 1 2 Internal TXC TXC at DSP pins 4 4 2 3 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-88.
www.ti.com 7.14.4 Management Data Input/Output (MDIO) 7.14.4.1 MDIO Device-Specific Information 7.14.4.2 MDIO Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Management Data Input/Output (MDIO) module implements the 802.
www.ti.com 7.14.4.3 MDIO Electrical Data/Timing 1 3 4 MDCLK MDIO (input) 1 7 MDCLK MDIO (output) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-90. Timing Requirements for MDIO Input (R)(G)MII (see Figure 7-71 ) -720 -850 A-1000/-1000 NO.
www.ti.com 7.15 Timers 7.15.1 Timers Device-Specific Information 7.15.2 Timers Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REV.
www.ti.com 7.15.3 Timers Electrical Data/Timing TINPLx T OUTLx 4 3 2 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-94. Timing Requirements for Timer Inputs (1) (see Figure 7-73 ) -720 -850 A-1000/-1000 NO.
www.ti.com 7.16 Enhanced Viterbi-Decoder Coprocessor (VCP2) 7.16.1 VCP2 Device-Specific Information 7.16.2 VCP2 Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SP.
www.ti.com 7.17 Enhanced Turbo Decoder Coprocessor (TCP2) 7.17.1 TCP2 Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-96.
www.ti.com 7.17.2 TCP2 Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-97.
www.ti.com 7.18 Peripheral Component Interconnect (PCI) 7.18.1 PCI Device-Specific Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 DSP supports connections to a PCI backplane via the integrated PCI master/slave bus interface.
www.ti.com 7.18.2 PCI Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-99.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100. PCI Back End Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGIS.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-100. PCI Back End Configuration Registers (continued) DSP ACCESS ACRONYM DSP .
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-102. PCI Hook Configuration Registers DSP ACCESS ACRONYM DSP ACCESS REGISTER .
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-103. PCI External Memory Space (continued) HEX ADDRESS OFFSET ACRONYM REGISTE.
www.ti.com 7.18.3 PCI Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Texas Instruments (TI) has performed the simulation.
www.ti.com 7.19 UTOPIA 7.19.1 UTOPIA Device-Specific Information 7.19.2 UTOPIA Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The Universal Test and Operations PHY Interface for ATM (UTOPIA) peripheral is a 50 MHz, 8 Bit Slave-only interface.
www.ti.com 7.19.3 UTOPIA Electrical Data/Timing UXCLK 1 2 3 4 4 URCLK 1 2 3 4 4 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-106. Timing Requirements for UXCLK (1) (see Figure 7-74 ) -720 -850 A-1000/-1000 NO.
www.ti.com P47 P48 H1 N 0x1F N 0x1F N + 1 0x1F N N 10 8 4 3 2 1 UXCLK UXDA T A[7:0] UXADDR[4:0] UXCLA V UXENB UXSOC 9 P46 P45 0 x1F A. The UT OPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the UXCLA V and UXSOC signals).
www.ti.com P48 H1 H2 H3 N 0x1F N+1 0x1F N+2 0x1F N N+1 N+2 12 1 1 9 10 5 4 3 2 1 URCLK URDA T A[7:0] URADDR[4:0] URCLA V URENB URSOC A. The UT OPIA Slave module has signals that are middle-level signals indicating a high-impedance state (i.e., the URCLA V and URSOC signals).
www.ti.com 7.20 Serial RapidIO (SRIO) Port 7.20.1 Serial RapidIO Device-Specific Information 7.20.2 Serial RapidIO Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112. RapidIO Control Registers (continued) HEX ADDRESS RANGE ACRONYM REGISTER.
www.ti.com 7.20.3 Serial RapidIO Electrical Data/Timing SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-112.
www.ti.com SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 TI only supports designs that follow the board design guidelines outlined in the SPRAAA8 application report.
www.ti.com 7.21 General-Purpose Input/Output (GPIO) 7.21.1 GPIO Device-Specific Information 7.21.2 GPIO Peripheral Register Description(s) SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B .
www.ti.com 7.21.3 GPIO Electrical Data/Timing GPIx GPOx 4 3 2 1 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 7-114. Timing Requirements for GPIO Inputs (1) (2) (see Figure 7-78 ) -720 -850 A-1000/-1000 NO.
www.ti.com 7.22 Emulation Features and Capability 7.22.1 Advanced Event Triggering (AET) 7.22.2 Trace SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 The C6455 device supports Advanced Event Triggering (AET).
www.ti.com 7.22.3 IEEE 1149.1 JTAG 7.22.3.1 JTAG Device-Specific Information 7.22.4 JTAG Peripheral Register Description(s) 7.22.5 JTAG Electrical Data/Timing TCK TDO TDI/TMS/TRST 1 2 3 4 2 SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 7.
www.ti.com Revision History SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
www.ti.com 8 Mechanical Data 8.1 Thermal Data 8.2 Packaging Information SM320C6455-EP FIXED-POINT DIGITAL SIGNAL PROCESSOR SPRS462B – SEPTEMBER 2007 – REVISED JANUARY 2008 Table 8-1 shows the thermal resistance characteristics for the PBGA - ZTZ/GTZ mechanical package.
PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) SM320C6455BGTZEP ACTIVE FCBGA GTZ 697 44 TBD SNPB Level-.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Texas Instruments SM320C6455-EP c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Texas Instruments SM320C6455-EP - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Texas Instruments SM320C6455-EP, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Texas Instruments SM320C6455-EP va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Texas Instruments SM320C6455-EP, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Texas Instruments SM320C6455-EP.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Texas Instruments SM320C6455-EP. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Texas Instruments SM320C6455-EP ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
