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21-S3-C2410A-032004 USER'S MANUAL S3C2410A – 200MHz & 266MHz 32-Bit RISC Microprocessor Revision 1.0.
S3C2410A 200MHz & 266MHz 32-BIT RISC MICROPROCESSOR USER'S MANUAL Revision 1.0.
Important Notice The information in this publication has been carefully checked and is believed to be entirely accurate at the time of publication. Samsung assumes no responsibility, however, for possible errors or omissions, or for any consequences resulting from the use of the information contained herein.
S3C2410A MICROPROCESSOR iii Table of Contents Chapter 1 Product Overview Introduction ......................................................................................................................................... 1-1 Features ..............
iv S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 3 ARM Instruction set Instruction Set Summay ....................................................................................................................... 3-1 Format Summary ..
S3C2410A MICROPROCESSOR v Table of Contents (Continued) Chapter 3 ARM Instruction set (Continued) Single Data Transfer (LDR, STR) ........................................................................................................... 3-28 Offsets And Auto-Indexing .
vi S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 3 ARM Instruction set (Continued) Coprocessor Data Transfers (LDC, STC) ................................................................................................ 3-53 The Coprocessor Fields .
S3C2410A MICROPROCESSOR vii Table of Contents (Continued) Chapter 4 Thumb Instruction Set (Continued) Format 5: Hi-Register Operations/Branch Exchange ............................................................................... 4-13 Operation .....
viii S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 4 Thumb Instruction Set (Continued) Format 16: Conditional Branch .............................................................................................................. 4-34 Operation .
S3C2410A MICROPROCESSOR ix Table of Contents (Continued) Chapter 6 NAND Flash Controller Overview ............................................................................................................................................. 6-1 Features .
x S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 8 DMA Overview ............................................................................................................................................. 8-1 DMA Request Sources ......
S3C2410A MICROPROCESSOR xi Table of Contents (Continued) Chapter 10 PWM Timer Overview ............................................................................................................................................. 10-1 Feature .........
xii S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 12 USB Host Controller Overview ............................................................................................................................................. 12-1 USB Host Controller Special Registers .
S3C2410A MICROPROCESSOR xiii Table of Contents (Continued) Chapter 14 Interrupt Controller Overview ............................................................................................................................................. 14-1 Interrupt Controller Operation .
xiv S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 16 ADC & Touch Screen Interface Overview ............................................................................................................................................
S3C2410A MICROPROCESSOR xv Table of Contents (Continued) Chapter 18 WatchDog Timer Overview ............................................................................................................................................. 18-1 Features ...
xvi S3C2410A MICROPROCESSOR Table of Contents (Continued) Chapter 21 IIS-BUS Interface Overview ............................................................................................................................................. 21-1 Block Diagram .
S3C2410A MICROPROCESSOR xvii Table of Contents (Continued) Chapter 23 BUS Priorities Overview ............................................................................................................................................. 23-1 Bus Priority Map .
xviii S3C2410A MICROPROCESSOR Table of Contents (Continued) Appendix 1- ARM920T Introduction Abuot the Introduction .......................................................................................................................... 1-1 Processor Functional Block Diagram .
S3C2410A MICROPROCESSOR xix Table of Contents (Concluded) Appendix 3- MMU (Continued) Level Two Descriptor ............................................................................................................................ 3-11 Translating Large Page References .
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S3C2410A MICROPROCESSOR xxi List of Figures Figure Title Page Number Number 1-1 S3C 2410A Block Diagram .................................................................................... 1-5 1-2 S3C2410A Pin Assignments (272-FBGA) ..................
xxii S3C2410A MICROPROCESSOR List of Figures (Continued) Figure Title Page Number Number 4-1 THUMB Instruction Set Formats ........................................................................... 4-2 4-2 Format 1 ...................................
S3C2410A MICROPROCESSOR xxiii List of Figures (Continued) Figure Title Page Number Number 6-1 NAND Flash Controller Block Diagram ................................................................... 6-2 6-2 NAND Flash Operation Scheme .................
xxiv S3C2410A MICROPROCESSOR List of Figures (Continued) Figure Title Page Number Number 14-1 Interrupt Process Diagram .................................................................................... 14-1 14-2 Priority Generating Block ..........
S3C2410A MICROPROCESSOR xxv List of Figures (Continued) Figure Title Page Number Number 24-8 ROM/SRAM Burst READ Timing(I) (Tacs = 0, Tcos = 0, Tacc = 2, Tcoh = 0, Tcah = 0, PMC = 0, ST = 0, DW = 16-bit) ...............................................
xxvi S3C2410A MICROPROCESSOR List of Figures (Concluded) Figure Title Page Number Number 1-1 ARM920T Functional Block Diagram ..................................................................... 1-2 2-1 CP15 MRC and MCR Bit Pattern ..................
S3C2410A MICROPROCESSOR xxvii List of Tables Table Title Page Number Number 1-1 272-Pin FBGA Pin Assignments – Pin Number Order ............................................. 1-7 1-2 272-Pin FBGA Pin Assignments ......................................
xxviii S3C2410A MICROPROCESSOR List of Tables (Continued) Table Title Page Number Number 8-1 DMA Request Sources for Each Channel ............................................................... 8-2 8-2 DMA Controller Module Signal Timing Constants ...
S3C2410A MICROPROCESSOR xxix List of Table (Concluded) Figure Title Page Number Number 2-1 ARM9TDMI Im plementation Option ........................................................................ 2-2 2-2 CP15 Register Map .............................
S3C2410A PRODUCT OVERVIEW 1- 1 1 PRODUCT OVERVIEW INTRODUCTION This manual describes SAMSUNG's S3C2410A 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance micro-controller solution in small die size.
PRODUCT OVERVIEW S3 C2410A 1- 2 FEATURES Architecture • Integrated system for hand-held devices and general embedded applications • 16/32-Bit RISC architecture and powerful instruction set with AR.
S3C2410A PRODUCT OVERVIEW 1- 3 FEATURES ( Continued) Interrupt Controller • 55 Interrupt sources (One Watch dog timer, 5 timers, 9 UARTs, 24 external interrupts, 4 DMA, 2 RTC, 2 ADC, 1 IIC, 2 SPI, 1.
PRODUCT OVERVIEW S3 C2410A 1- 4 FEATURES ( Continued) Watchdog Timer • 16-bit Watchdog Timer • Interrupt request or system reset at time-out IIC-Bus Interface • 1-ch Multi-Master IIC-Bus • Serial, 8-bit oriented and bi-directional data transfers can be made at up to 100 Kbit/s in Standard mode or up to 400 Kbit/s in Fast mode.
S3C2410A PRODUCT OVERVIEW 1- 5 BLOCK DIAGRAM ARM920T ARM9TDMI Processor core (Internal Embedded ICE) DD[31:0] WriteBack PA Tag RAM Data MMU C13 DVA[31:0] DV A[31:0] Instruction CACHE (16KB) Instructio.
PRODUCT OVERVIEW S3 C2410A 1- 6 PIN ASSIGNMENTS BOTTOM VIEW U T R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Figure 1-2. S3C2410A Pin Assignments (272-FBGA).
S3C2410A PRODUCT OVERVIEW 1- 7 Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name A1 DATA19 B14 ADDR0/GPA0 D10 ADDR19/GPA4 A2 DATA.
PRODUCT OVERVIEW S3 C2410A 1- 8 Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order (Continued) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name F6 VSSi H4 nXDREQ1/GPB8 K13 TXD2/nR.
S3C2410A PRODUCT OVERVIEW 1- 9 Table 1-1. 272-Pin FBGA Pin Assignments – Pin Number Order (Continued) Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name M11 EINT23/nYPON/GPG15 P8 SPICLK0/GP.
PRODUCT OVERVIEW S3 C2410A 1- 10 Table 1-2. 272-Pin FBGA Pin Assignments Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type C3 DATA21 DATA21 Hi-z Hi-.
S3C2410A PRODUCT OVERVIEW 1- 11 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type J5 TDO TDO OOO.
PRODUCT OVERVIEW S3 C2410A 1- 12 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type T2 VD16/GPD8 .
S3C2410A PRODUCT OVERVIEW 1- 13 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type L9 EINT11/nSS1.
PRODUCT OVERVIEW S3 C2410A 1- 14 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type T15 AIN1 AIN1.
S3C2410A PRODUCT OVERVIEW 1- 15 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type K13 TXD2/nRTS1.
PRODUCT OVERVIEW S3 C2410A 1- 16 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type B17 VSSi VSSi.
S3C2410A PRODUCT OVERVIEW 1- 17 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type C10 VSSMOP VSS.
PRODUCT OVERVIEW S3 C2410A 1- 18 Table 1-2. 272-Pin FBGA Pin Assignments (Continued) Pin Number Pin Name Default Function I/O State @BUS REQ I/O State @PWR-off I/O State @nRESET I/O Type E6 VSSMOP VSS.
S3C2410A PRODUCT OVERVIEW 1- 19 7. The table below shows I/O types and the descriptions. I/O Type Descriptions d1i(vdd1ih), s3i(vss3i) 1.8V / 2.0V V DD /V SS for internal logic d1c(vdd1ih_core), s3i(vss3i) 1.8V / 2.0V V DD /V SS for internal logic without input driver d3o(vdd3op), s3o(vss3op) 3.
PRODUCT OVERVIEW S3 C2410A 1- 20 SIGNAL DESCRIPTIONS Table 1-3. S3C2410A Signal Descriptions Signal I/O Descriptions Bus Controller OM [1:0] I OM [1:0] sets S3C2410A in the TEST mode, which is used only at fabrication. Also, it determines the bus width of nGCS0.
S3C2410A PRODUCT OVERVIEW 1- 21 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Descriptions NAND Flash CLE O Command Latch Enable ALE O Address Latch Enable nFCE O NAND Flash Chip Enable nFRE O NAND Flash Read Enable nFWE O NAND Flash Write Enable NCON I NAND Flash Configuration.
PRODUCT OVERVIEW S3 C2410A 1- 22 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Descriptions UART RxD [2:0] I UART receives data input TxD [2:0] O UART transmits data output nCTS [1:0] I UART clear to send input signal nRTS [1:0] O UART request to send output signal UEXTCLK I UART clock signal ADC AIN [7:0] AI ADC input [7:0].
S3C2410A PRODUCT OVERVIEW 1- 23 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Description SD SDDAT [3:0] IO SD receive/transmit data SDCMD IO SD receive response/ transmit command SDC.
PRODUCT OVERVIEW S3 C2410A 1- 24 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Description Reset, Clock & Power (Continued) EXTCLK I External clock source. When OM [3:2] = 11b, EXTCLK is used for MPLL CLK source and UPLL CLK source.
S3C2410A PRODUCT OVERVIEW 1- 25 Table 1-3. S3C2410A Signal Descriptions (Continued) Signal I/O Description Power VDDalive P S3C2410A reset block and port status register V DD (1.8V / 2.0V). It should be always supplied whether in normal mode or in power-off mode.
PRODUCT OVERVIEW S3 C2410A 1- 26 S3C2410A SPECIAL REGISTERS Table 1-4. S3C2410A Special Registers Register Name Address (B. Endian) Address (L. Endian) Acc.
S3C2410A PRODUCT OVERVIEW 1- 27 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function USB Host Controller HcRevision 0x.
PRODUCT OVERVIEW S3 C2410A 1- 28 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function DMA DISRC0 0x4B000000 ← W R/W .
S3C2410A PRODUCT OVERVIEW 1- 29 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function Clock & Power Management LOCK.
PRODUCT OVERVIEW S3 C2410A 1- 30 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function UART ULCON0 0x50000000 ← W R/W.
S3C2410A PRODUCT OVERVIEW 1- 31 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function PWM Timer TCFG0 0x51000000 ← W .
PRODUCT OVERVIEW S3 C2410A 1- 32 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function USB Device FUNC_ADDR_REG 0x52000.
S3C2410A PRODUCT OVERVIEW 1- 33 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/W rite Function USB Device (Continued) EP2_DMA_CO.
PRODUCT OVERVIEW S3 C2410A 1- 34 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function I/O port GPACON 0x56000000 ← W.
S3C2410A PRODUCT OVERVIEW 1- 35 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function RTC RTCCON 0x57000043 0x57000040 .
PRODUCT OVERVIEW S3 C2410A 1- 36 Table 1-4. S3C2410A Special Registers (Continued) Register Name Address (B. Endian) Address (L. Endian) Acc. Unit Read/ Write Function SD interface SDICON 0x5A000000 .
S3C2410A PROGRAMMER'S MODEL 2- 1 2 PROGRAMMER'S MODEL OVERVIEW S3C2410A has been developed using the advanced ARM920T core, which has been designed by Advanced RISC Machines, Ltd.
PROGRAMMER'S MODEL S3C2410A 2- 2 BIG-ENDIAN FORMAT In Big-Endian format, the most significant byte of a word is stored at the lowest numbered byte and the least significant byte at the highest numbered byte. Byte 0 of the memory system is therefore connected to data lines 31 through 24.
S3C2410A PROGRAMMER'S MODEL 2- 3 OPERATING MODES ARM920T supports seven modes of operation: • User (usr): The normal ARM program execution state • FIQ (fiq): Designed to support a data transf.
PROGRAMMER'S MODEL S3C2410A 2- 4 R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13 R14 R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R9 R8 R10 R11 R12 R13_ svc R14_ svc R15 (PC) R0 R1 R2 R3 R4 R5 R6 R7 R9_ fiq R1.
S3C2410A PROGRAMMER'S MODEL 2- 5 The THUMB State Register Set The THUMB state register set is a subset of the ARM state set. The programmer has direct access to eight general registers, R0-R7, as well as the Program Counter (PC), a stack pointer register (SP), a link register (LR), and the CPSR.
PROGRAMMER'S MODEL S3C2410A 2- 6 The relationship between ARM and THUMB state registers The THUMB state registers relate to the ARM state registers in the following way: • THUMB state R0-R7 and.
S3C2410A PROGRAMMER'S MODEL 2- 7 Accessing Hi-Registers in THUMB State In THUMB state, registers R8-R15 (the Hi registers) are not part of the standard register set. However, the assembly language programmer has limited access to them, and can use them for fast temporary storage.
PROGRAMMER'S MODEL S3C2410A 2- 8 The Condition Code Flags The N, Z, C and V bits are the condition code flags. These may be changed as a result of arithmetic and logical operations, and may be tested to determine whether an instruction should be executed.
S3C2410A PROGRAMMER'S MODEL 2- 9 Table 2-1. PSR Mode Bit Values M[4:0] Mode Visible THUMB state registers Visible ARM state registers 10000 User R7..R0, LR, SP PC, CPSR R14..R0, PC, CPSR 10001 FIQ R7..R0, LR_fiq, SP_fiq PC, CPSR, SPSR_fiq R7..R0, R14_fiq.
PROGRAMMER'S MODEL S3C2410A 2- 10 EXCEPTIONS Exceptions arise whenever the normal flow of a program has to be halted temporarily, for example to service an interrupt from a peripheral. Before an exception can be handled, the current processor state must be preserved so that the original program can resume when the handler routine has finished.
S3C2410A PROGRAMMER'S MODEL 2- 11 Exception Entry/Exit Summary Table 2-2 summarizes the PC value preserved in the relevant R14 on exception entry, and the recommended instruction for exiting the exception handler.
PROGRAMMER'S MODEL S3C2410A 2- 12 IRQ The IRQ (Interrupt Request) exception is a normal interrupt caused by a LOW level on the nIRQ input. IRQ has a lower priority than FIQ and is masked out when a FIQ sequence is entered.
S3C2410A PROGRAMMER'S MODEL 2- 13 Software Interrupt The software interrupt instruction (SWI) is used for entering Supervisor mode, usually to request a particular supervisor function.
PROGRAMMER'S MODEL S3C2410A 2- 14 Exception Priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6.
S3C2410A PROGRAMMER'S MODEL 2- 15 INTERRUPT LATENCIES The worst case latency for FIQ, assuming that it is enabled, consists of the longest time the request can take to pass through the synchroniz.
PROGRAMMER'S MODEL S3C2410A 2- 16 NOTES.
S3C2410A ARM INSTRUCTION SET 3- 1 3 ARM INSTRUCTION SET INSTRUCTION SET SUMMAY This chapter describes the ARM instruction set in the ARM920T core. FORMAT SUMMARY The ARM instruction set formats are shown below.
ARM INSTRUCTION SET S3C2410A 3- 2 NOTE Some instruction codes are not defined but do not cause the Undefined instruction trap to be taken, for instance a Multiply instruction with bit 6 changed to a 1. These instructions should not be used, as their action may change in future ARM implementations.
S3C2410A ARM INSTRUCTION SET 3- 3 Table 3-1. The ARM Instruction Set (Continued) Mnemonic Instruction Action MRC Move from coprocessor register to CPU register Rn: = cRn {<op>cRm} MRS Move PSR s.
ARM INSTRUCTION SET S3C2410A 3- 4 THE CONDITION FIELD In ARM state, all instructions are conditionally executed according to the state of the CPSR condition codes and the instruction's condition field. This field (bits 31:28) determines the circumstances under which an instruction is to be executed.
S3C2410A ARM INSTRUCTION SET 3- 5 BRANCH AND EXCHANGE (BX) This instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. This instruction performs a branch by copying the contents of a general register, Rn, into the program counter, PC.
ARM INSTRUCTION SET S3C2410A 3- 6 Examples ADR R0, Into_THUMB + 1 ; Generate branch target address ; and set bit 0 high - hence ; arrive in THUMB state.
S3C2410A ARM INSTRUCTION SET 3- 7 BRANCH AND BRANCH WITH LINK (B, BL) The instruction is only executed if the condition is true. The various conditions are defined Table 3-2. The instruction encoding is shown in Figure 3-3, below. 31 24 27 Cond Offset 28 23 [24] Link bit 0 = Branch 1 = Branch with link [31:28] Condition Field 25 101 L 0 Figure 3-3.
ARM INSTRUCTION SET S3C2410A 3- 8 ASSEMBLER SYNTAX Items in {} are optional. Items in <> must be present. B{L}{cond} <expression> { L} Used to request the Branch with Link form of the instruction. If absent, R14 will not be affected by the instruction.
S3C2410A ARM INSTRUCTION SET 3- 9 DATA PROCESSING The data processing instruction is only executed if the condition is true. The conditions are defined in Table 3-2.
ARM INSTRUCTION SET S3C2410A 3- 10 The instruction produces a result by performing a specified arithmetic or logical operation on one or two operands. The first operand is always a register (Rn). The second operand may be a shifted register (Rm) or a rotated 8 bit immediate value (Imm) according to the value of the I bit in the instruction.
S3C2410A ARM INSTRUCTION SET 3- 11 CPSR FLAGS The data processing operations may be classified as logical or arithmetic. The logical operations (AND, EOR, TST, TEQ, ORR, MOV, BIC, MVN) perform the logical action on all corresponding bits of the operand or operands to produce the result.
ARM INSTRUCTION SET S3C2410A 3- 12 SHIFTS When the second operand is specified to be a shifted register, the operation of the barrel shifter is controlled by the Shift field in the instruction. This field indicates the type of shift to be performed (logical left or right, arithmetic right or rotate right).
S3C2410A ARM INSTRUCTION SET 3- 13 31 Contents of Rm Value of Operand 2 0 carry out 4 5 0 0 0 0 0 Figure 3-7. Logical Shift Right The form of the shift field which might be expected to correspond to LSR #0 is used to encode LSR #32, which has a zero result with bit 31 of Rm as the carry output.
ARM INSTRUCTION SET S3C2410A 3- 14 Rotate right (ROR) operations reuse the bits which "overshoot" in a logical shift right operation by reintroducing them at the high end of the result, in place of the zeros used to fill the high end in logical right operations.
S3C2410A ARM INSTRUCTION SET 3- 15 Register Specified Shift Amount Only the least significant byte of the contents of Rs is used to determine the shift amount.
ARM INSTRUCTION SET S3C2410A 3- 16 IMMEDIATE OPERAND ROTATES The immediate operand rotate field is a 4-bit unsigned integer which specifies a shift operation on the 8-bit immediate value. This value is zero extended to 32 bits, and then subject to a rotate right by twice the value in the rotate field.
S3C2410A ARM INSTRUCTION SET 3- 17 ASSEMBLER SYNTAX • MOV,MVN (single operand instructions). <opcode>{cond}{S} Rd,<Op2> • CMP,CMN,TEQ,TST (instructions which do not produce a result).
ARM INSTRUCTION SET S3C2410A 3- 18 PSR TRANSFER (MRS, MSR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The MRS and MSR instructions are formed from a subset of the Data Processing operations and are implemented using the TEQ, TST, CMN and CMP instructions without the S flag set.
S3C2410A ARM INSTRUCTION SET 3- 19 MSR (transfer register contents or immediate value to PSR flag bits only) Cond Source operand Pd 101001111 31 22 27 28 11 12 21 23 I 10 00 26 25 24 0 Cond 00000000 0.
ARM INSTRUCTION SET S3C2410A 3- 20 RESERVED BITS Only twelve bits of the PSR are defined in ARM920T (N,Z,C,V,I,F, T & M[4:0]); the remaining bits are reserved for use in future versions of the processor. Refer to Figure 2-6 for a full description of the PSR bits.
S3C2410A ARM INSTRUCTION SET 3- 21 ASSEMBLY SYNTAX • MRS - transfer PSR contents to a register MRS{cond} Rd,<psr> • MSR - transfer register contents to PSR MSR{cond} <psr>,Rm • MSR -.
ARM INSTRUCTION SET S3C2410A 3- 22 MULTIPLY AND MULTIPLY-ACCUMULATE (MUL, MLA) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
S3C2410A ARM INSTRUCTION SET 3- 23 If the Operands Are Interpreted as Signed Operand A has the value -10, operand B has the value 20, and the result is -200 which is correctly represented as 0xFFFFFF38.
ARM INSTRUCTION SET S3C2410A 3- 24 CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction. The N (Negative) and Z (Zero) flags are set correctly on the result (N is made equal to bit 31 of the result, and Z is set if and only if the result is zero).
S3C2410A ARM INSTRUCTION SET 3- 25 MULTIPLY LONG AND MULTIPLY-ACCUMULATE LONG (MULL, MLAL) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
ARM INSTRUCTION SET S3C2410A 3- 26 OPERAND RESTRICTIONS • R15 must not be used as an operand or as a destination register. • RdHi, RdLo, and Rm must all specify different registers. CPSR FLAGS Setting the CPSR flags is optional, and is controlled by the S bit in the instruction.
S3C2410A ARM INSTRUCTION SET 3- 27 ASSEMBLER SYNTAX Table 3-5. Assembler Syntax Descriptions Mnemonic Description Purpose UMULL{cond}{S} RdLo,RdHi,Rm,Rs Unsigned Multiply Long 32 x 32 = 64 UMLAL{cond}.
ARM INSTRUCTION SET S3C2410A 3- 28 SINGLE DATA TRANSFER (LDR, STR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-14. The single data transfer instructions are used to load or store single bytes or words of data.
S3C2410A ARM INSTRUCTION SET 3- 29 OFFSETS AND AUTO-INDEXING The offset from the base may be either a 12-bit unsigned binary immediate value in the instruction, or a second register (possibly shifted in some way). The offset may be added to (U = 1) or subtracted from (U = 0) the base register Rn.
ARM INSTRUCTION SET S3C2410A 3- 30 LDR from word aligned address A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D LDR from address offset by 2 A+3 A A+2 A+1 memory 24 16 8 0 A B C D register 24 16 8 0 A B C D Figure 3-15.
S3C2410A ARM INSTRUCTION SET 3- 31 USE OF R15 Write-back must not be specified if R15 is specified as the base register (Rn). When using R15 as the base register you must remember it contains an address 8 bytes on from the address of the current instruction.
ARM INSTRUCTION SET S3C2410A 3- 32 ASSEMBLER SYNTAX <LDR|STR>{cond}{B}{T} Rd,<Address> where: LDR Load from memory into a register STR Store from a register into memory {cond} Two-character condition mnemonic.
S3C2410A ARM INSTRUCTION SET 3- 33 EXAMPLES STR R1,[R2,R4]! ; Store R1 at R2+R4 (both of which are regis ters) ; and write back address to R2. STR R1,[R2],R4 ; Store R1 at R2 and write back R2+R4 to R2. LDR R1,[R2,#16] ; Load R1 from contents of R2+16, but don't write back.
ARM INSTRUCTION SET S3C2410A 3- 34 HALFWO RD AND SIGNED DATA TRANSFER (LDRH/STRH/LDRSB/LDRSH) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-16.
S3C2410A ARM INSTRUCTION SET 3- 35 31 27 19 15 Cond 28 16 11 12 21 23 1 20 L Rn Rd [3:0] Immediate Offset (Low Nibble) [6][5] S H 0 0 = SWP instruction 0 1 = Unsigned halfword 1 1 = Signed byte 1 1 = .
ARM INSTRUCTION SET S3C2410A 3- 36 HALFWORD LOAD AND STORES Setting S=0 and H=1 may be used to transfer unsigned Half-words between an ARM920T register and memory. The action of LDRH and STRH instructions is influenced by the BIGEND control signal. The two possible configurations are described in the section below.
S3C2410A ARM INSTRUCTION SET 3- 37 Big-Endian Configuration A signed byte load (LDRSB) expects data on data bus inputs 31 through to 24 if the supplied address is on a word boundary, on data bus inputs 23 through to 16 if it is a word address plus one byte, and so on.
ARM INSTRUCTION SET S3C2410A 3- 38 ASSEMBLER SYNTAX <LDR|STR>{cond}<H|SH|SB> Rd,<address> LDR Load from memory into a register STR Store from a register into memory {cond} Two-character condition mnemonic.
S3C2410A ARM INSTRUCTION SET 3- 39 EXAMPLES LDRH R1,[R2,-R3]! ; Load R1 from the contents of the halfword address ; contained in R2-R3 (both of which are registers) ; and write back address to R2 STRH R3,[R4,#14] ; Store the halfword in R3 at R14+14 but don't write back.
ARM INSTRUCTION SET S3C2410A 3- 40 BLOCK DATA TRANSFER (LDM, STM) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-18. Block data transfer instructions are used to load (LDM) or store (STM) any subset of the currently visible registers.
S3C2410A ARM INSTRUCTION SET 3- 41 ADDRESSING MODES The transfer addresses are determined by the contents of the base register (Rn), the pre/post bit (P) and the up/ down bit (U). The registers are transferred in the order lowest to highest, so R15 (if in the list) will always be transferred last.
ARM INSTRUCTION SET S3C2410A 3- 42 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-20. Pre-Increment Addressing Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-21.
S3C2410A ARM INSTRUCTION SET 3- 43 Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3-22. Pre-Decrement Addressing USE OF THE S BIT When the S bit is set in a LDM/STM instruction its meaning depends on whether or not R15 is in the transfer list and on the type of instruction.
ARM INSTRUCTION SET S3C2410A 3- 44 INCLUSION OF THE BASE IN THE REGISTER LIST When write-back is specified, the base is written back at the end of the second cycle of the instruction. During a STM, the first register is written out at the start of the second cycle.
S3C2410A ARM INSTRUCTION SET 3- 45 ASSEMBLER SYNTAX <LDM|STM>{cond}<FD|ED|FA|EA|IA|IB|DA|DB> Rn{!},<Rlist>{^} where: { cond} Two character condition mnemonic. See Table 3-2. Rn An expression evaluating to a valid register number <Rlist> A list of registers and register ranges enclosed in {} (e.
ARM INSTRUCTION SET S3C2410A 3- 46 EXAMPLES LDMFD SP!,{R0,R1,R2} ; Unstack 3 registers. STMIA R0,{R0-R15} ; Save all registers. LDMFD SP!,{R15} ; R15 ← (SP), CPSR unchanged. LDMFD SP!,{R15}^ ; R15 ← (SP), CPSR <- SPSR_mode ; (allowed only in privileged modes).
S3C2410A ARM INSTRUCTION SET 3- 47 SINGLE DATA SWAP (SWP) 31 19 15 Cond 28 16 11 12 21 23 B 20 00 Rn Rd [3:0] Source Register [15:12] Destination Register [19:16] Base Register [22] Byte/Word Bit 0 = Swap word quantity 1 = Swap word quantity [31:28] Condition Field 22 00010 0000 Rm 1001 27 8 7 4 3 0 Figure 3-23.
ARM INSTRUCTION SET S3C2410A 3- 48 USE OF R15 Do not use R15 as an operand (Rd, Rn or Rs) in a SWP instruction. DATA ABORTS If the address used for the swap is unacceptable to a memory management system, the memory manager can flag the problem by driving ABORT HIGH.
S3C2410A ARM INSTRUCTION SET 3- 49 SOFTWARE INTERRUPT (SWI) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-24, below. 31 24 27 1111 Cond Comment Field (Ignored by Processor) 28 23 [31:28] Condition Field 0 Figure 3-24.
ARM INSTRUCTION SET S3C2410A 3- 50 ASSEMBLER SYNTAX SWI{cond} <expression> { cond} Two character condition mnemonic, Table 3-2. <expression> Evaluated and placed in the comment field (which is ignored by ARM920T). Examples SWI ReadC ; Get next character from read stream.
S3C2410A ARM INSTRUCTION SET 3- 51 COPROCESSOR DATA OPERATIONS (CDP) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction encoding is shown in Figure 3-25. This class of instruction is used to tell a coprocessor to perform some internal operation.
ARM INSTRUCTION SET S3C2410A 3- 52 INSTRUCTION CYCLE TIMES Coprocessor data operations take 1S + bI incremental cycles to execute, where b is the number of cycles spent in the coprocessor busy-wait loop. S and I are defined as sequential (S-cycle) and internal (I-cycle).
S3C2410A ARM INSTRUCTION SET 3- 53 COPROCESSOR DATA TRANSFERS (LDC, STC) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.
ARM INSTRUCTION SET S3C2410A 3- 54 THE COPROCESSOR FIELDS The CP# field is used to identify the coprocessor which is required to supply or accept the data, and a coprocessor will only respond if its number matches the contents of this field.
S3C2410A ARM INSTRUCTION SET 3- 55 ASSEMBLER SYNTAX <LDC|STC>{cond}{L} p#,cd,<Address> LDC Load from memory to coprocessor STC Store from coprocessor to memory { L} When present perform long transfer (N = 1), otherwise perform short transfer (N = 0) { cond} Two character condition mnemonic.
ARM INSTRUCTION SET S3C2410A 3- 56 COPROCESSOR REGISTER TRANSFERS (MRC, MCR) The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2.. The instruction encoding is shown in Figure 3-27. This class of instruction is used to communicate information directly between ARM920T and a coprocessor.
S3C2410A ARM INSTRUCTION SET 3- 57 TRANSFERS TO R15 When a coprocessor register transfer to ARM920T has R15 as the destination, bits 31, 30, 29 and 28 of the transferred word are copied into the N, Z, C and V flags respectively. The other bits of the transferred word are ignored, and the PC and other CPSR bits are unaffected by the transfer.
ARM INSTRUCTION SET S3C2410A 3- 58 UNDEFINED INSTRUCTION The instruction is only executed if the condition is true. The various conditions are defined in Table 3-2. The instruction format is shown in Figure 3-28. 31 27 Cond 28 25 24 011 xxxxxxxxxxxxxxxxxxxx 1 xxxx 5 4 3 0 Figure 3-28.
S3C2410A ARM INSTRUCTION SET 3- 59 INSTRUCTION SET EXAMPLES The following examples show ways in which the basic ARM920T instructions can combine to give efficient code. None of these methods saves a great deal of execution time (although they may save some), mostly they just save code.
ARM INSTRUCTION SET S3C2410A 3- 60 Division and Remainder A number of divide routines for specific applications are provided in source form as part of the ANSI C library provided with the ARM Cross Development Toolkit, available from your supplier. A short general purpose divide routine follows.
S3C2410A ARM INSTRUCTION SET 3- 61 5. Overflow in unsigned multiply accumulate with a 64-bit result UMULL Rl,Rh,Rm,Rn ; 3 to 6 cycles ADDS Rl,Rl,Ra1 ; Lower accumulate ADC Rh,Rh,Ra2 ; Upper accumulate BCS overflow ; 1 cycle and 2 registers 6.
ARM INSTRUCTION SET S3C2410A 3- 62 Multiplication by 6 ADD Ra,Ra,Ra,LSL #1 ; Multiply by 3 MOV Ra,Ra,LSL#1 ; and then by 2 Multiply by 10 and add in extra number ADD Ra,Ra,Ra,LSL#2 ; Multiply by 5 ADD Ra,Rc,Ra,LSL#1 ; Multiply by 2 and ad d in next digit General recursive method for Rb := Ra*C, C a constant: 1.
S3C2410A ARM INSTRUCTION SET 3- 63 LOADING A WORD FROM AN UNKNOWN ALIGNMENT ; Enter with address in Ra (32 bits) uses ; Rb, Rc result in Rd. Note d must be less than c e.g. 0,1 BIC Rb,Ra,#3 ; Get word aligned address LDMIA Rb,{Rd,Rc} ; Get 64 bits containing answer AND Rb,Ra,#3 ; Correction factor in by tes MOVS Rb,Rb,LSL#3 ; .
ARM INSTRUCTION SET S3C2410A 3- 64 NOTES.
S3C2410A THUMB INSTRUCTION SET 4- 1 4 THUMB INSTRUCTION SET THUMB INSTRUCTION SET FORMAT The thumb instruction sets are 16-bit versions of ARM instruction sets (32-bit format). The ARM instructions are reduced to 16-bit versions, Thumb instructions, at the cost of versatile functions of the ARM instruction sets.
THUMB INSTRUCTION SET S3C2410A 4- 2 FORMAT SUMMARY The THUMB instruction set formats are shown in the following figure. Move Shifted register 0 0 0 0 0 0 000 000 1 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 1 1 0 .
S3C2410A THUMB INSTRUCTION SET 4- 3 OPCODE SUMMARY The following table summarizes the THUMB instruction set. For further information about a particular instruction please refer to the sections listed in the right-most column.
THUMB INSTRUCTION SET S3C2410A 4- 4 Table 4-1. THUMB Instruction Set Opcodes (Continued) Mnemonic Instruction Lo-Register Operand Hi-Register Operand Condition Codes Set NEG Negate Y – Y ORR OR Y .
S3C2410A THUMB INSTRUCTION SET 4- 5 FORMAT 1: MOVE SHIFTED REGISTER 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [10:6] Immediate Vale [12:11] Opcode 0 = LSL 1 = LSR 2 = ASR Offset5 6 5 3 2 Rd 0 0 13 12 11 Op Rs Figure 4-2. Format 1 OPERATION These instructions move a shifted value between Lo registers.
THUMB INSTRUCTION SET S3C2410A 4- 6 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-2. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
S3C2410A THUMB INSTRUCTION SET 4- 7 FORMAT 2: ADD/SUBTRACT 15 0 14 10 [2:0] Destination Register [5:3] Source Register [8:6] Register/Immediate Vale [9] Opcode 0 = ADD 1 = SUB [10] Immediate Flag 0 = Register operand 1 = Immediate oerand Rn/Offset3 Rd 0 0 13 12 11 Op Rs 9 8 111 6 5 3 2 0 Figure 4-3.
THUMB INSTRUCTION SET S3C2410A 4- 8 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-3. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
S3C2410A THUMB INSTRUCTION SET 4- 9 FORMAT 3: MOVE/COMPARE/ADD/SUBTRACT IMMEDIATE 15 0 0 14 10 [7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV 1 = CMP 2 = ADD 3 = SUB Offset8 Rd 0 0 13 12 11 Op 7 8 Figure 4-4.
THUMB INSTRUCTION SET S3C2410A 4- 10 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-4. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
S3C2410A THUMB INSTRUCTION SET 4- 11 FORMAT 4: ALU OPERATIONS 15 0 0 14 10 [2:0] Source/Destination Register [5:3] Source Register 2 [9:6] Opcode 5 6 3 Rd 0 0 13 12 11 Op Rs 0 0 0 9 2 Figure 4-5. Format 4 OPERATION The following instructions perform ALU operations on a Lo register pair.
THUMB INSTRUCTION SET S3C2410A 4- 12 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-5. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
S3C2410A THUMB INSTRUCTION SET 4- 13 FORMAT 5: HI-REGISTER OPERATIONS/BRANCH EXCHANGE 15 0 0 14 10 [2:0] Destination Register [5:3] Source Register [6] Hi Operand Flag 2 [7] Hi Operand Flag 1 [9:8] Opcode 6 5 3 2 Rd/Hd 0 0 13 12 11 Op Rs/Hs 0 0 0 987 H1 H2 Figure 4-6.
THUMB INSTRUCTION SET S3C2410A 4- 14 Table 4-6. Summary of Format 5 Instructions (Continued) Op H1 H2 THUMB assembler ARM equivalent Action 01 1 1 CMP Hd, Hs CMP Hd, Hs Compare two registers in the range 8-15. Set the condition code flags on the result.
S3C2410A THUMB INSTRUCTION SET 4- 15 EXAMPLES Hi-Register Operations ADD PC, R5 ; PC : = PC + R5 but don't set the condition codes. CMP R4, R12 ; Set the condition codes on the result of R4 - R12. MOV R15, R14 ; Move R14 (LR) into R15 (PC) ; but don't set the condition codes, ; eg.
THUMB INSTRUCTION SET S3C2410A 4- 16 FORMAT 6: PC-RELATIVE LOAD 15 0 0 14 10 [7:0] Immediate Value [10:8] Destination Register Word 8 0 0 13 12 11 Rd 0 0 8 7 Figure 4-7. Format 6 OPERATION This instruction loads a word from an address specified as a 10-bit immediate offset from the PC.
S3C2410A THUMB INSTRUCTION SET 4- 17 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction. EXAMPLES LDR R3,[PC,#844] ; Load into R3 the w ord found at the ; address formed by adding 844 to PC.
THUMB INSTRUCTION SET S3C2410A 4- 18 FORMAT 7: LOAD/STORE WITH REGISTER OFFSET [2:0] Source/Destination Register [5:3] Base Register [8:6] Offset Register [10] Byte/Word Flag 0 = Transfer word quantit.
S3C2410A THUMB INSTRUCTION SET 4- 19 OPERATION These instructions transfer byte or word values between registers and memory. Memory addresses are pre-indexed using an offset register in the range 0-7. The THUMB assembler syntax is shown in Table 4-8. Table 4-8.
THUMB INSTRUCTION SET S3C2410A 4- 20 FORMAT 8: LOAD/STORE SIGN-EXTENDED BYTE/HALFWORD [2:0] Destination Register [5:3] Base Register [8:6] Offset Register [10] Sign-Extended Flag 0 = Operand not sing-extended 1 = Operand sing-extended [11] H Flag 15 0 0 14 10 6 5 3 2 Rd 1 0 13 12 11 Rb 1 H S 9 8 Ro 1 Figure 4-9.
S3C2410A THUMB INSTRUCTION SET 4- 21 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-9. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
THUMB INSTRUCTION SET S3C2410A 4- 22 FORMAT 9: LOAD/STORE WITH IMMEDIATE OFFSET [2:0] Source/Destination Register [5:3] Base Register [10:6] Offset Register [11] Load/Store Flag 0 = Store to memory 1 .
S3C2410A THUMB INSTRUCTION SET 4- 23 OPERATION These instructions transfer byte or word values between registers and memory using an immediate 5 or 7-bit offset.
THUMB INSTRUCTION SET S3C2410A 4- 24 FORMAT 10: LOAD/STORE HALFWORD [2:0] Source/Destination Register [5:3] Base Register [10:6] Immediate Value [11] Load/Store Flag 0 = Store to memory 1 = Load from memory 15 0 0 14 10 6 5 3 2 Rd 1 0 13 12 11 Rb 0 L Offset5 Figure 4-11.
S3C2410A THUMB INSTRUCTION SET 4- 25 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-11. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
THUMB INSTRUCTION SET S3C2410A 4- 26 FORMAT 11: SP-RELATIVE LOAD/STORE [7:0] Immediate Value [10:8] Destination Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 0 0 13 12 11 Word 8 1 L Rd 7 8 Figure 4-12. Format 11 OPERATION The instructions in this group perform an SP-relative load or store.
S3C2410A THUMB INSTRUCTION SET 4- 27 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-12. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
THUMB INSTRUCTION SET S3C2410A 4- 28 FORMAT 12: LOAD ADDRESS [7:0] 8-bit Unsigned Constant [10:8] Destination Register [11] Source 0 = PC 1 = SP 15 0 1 14 10 0 1 13 12 11 Word 8 0 SP Rd 7 8 Figure 4-13.
S3C2410A THUMB INSTRUCTION SET 4- 29 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-13. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
THUMB INSTRUCTION SET S3C2410A 4- 30 FORMAT 13: ADD OFFSET TO STACK POINTER [6:0] 7-bit Immediate Value [7] Sign Flag 0 = Offset is positive 1 = Offset is negative 15 0 1 14 10 0 1 13 12 11 SWord 7 1 0 0 7 8 9 6 0 0 S Figure 4-14. Format 13 OPERATION This instruction adds a 9-bit signed constant to the stack pointer.
S3C2410A THUMB INSTRUCTION SET 4- 31 FORMAT 14: PUSH/POP REGISTERS [7:0] Register List [8] PC/LR Bit 0 = Do not store LR/Load PC 1 = Store LR/Load PC [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 0 1 13 12 11 Rlist 1 L 0 7 8 9 1 R Figure 4-15.
THUMB INSTRUCTION SET S3C2410A 4- 32 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 4-15. The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction.
S3C2410A THUMB INSTRUCTION SET 4- 33 FORMAT 15: MULTIPLE LOAD/STORE [7:0] Register List [10:8] Base Register [11] Load/Store Bit 0 = Store to memory 1 = Load from memory 15 0 1 14 10 1 0 13 12 11 Rlist 0 L 7 8 Rb Figure 4-16. Format 15 OPERATION These instructions allow multiple loading and storing of Lo registers.
THUMB INSTRUCTION SET S3C2410A 4- 34 FORMAT 16: CONDITIONAL BRANCH [7:0] 8-bit Signed Immediate [11:8] Condition 15 0 1 14 1 0 13 12 11 SOffset 8 1 7 8 Cond Figure 4-17. Format 16 OPERATION The instructions in this group all perform a conditional Branch depending on the state of the CPSR condition codes.
S3C2410A THUMB INSTRUCTION SET 4- 35 Table 4-17. The Conditional Branch Instructions (Continued) L THUMB assembler ARM equivalent Action 1001 BLS label BLS label Branch if C clear or Z set (unsigned l.
THUMB INSTRUCTION SET S3C2410A 4- 36 FORMAT 17: SOFTWARE INTERRUPT [7:0] Comment Field 15 0 1 14 1 0 13 12 11 Value 8 1 7 8 10 9 1111 Figure 4-18. Format 17 OPERATION The SWI instruction performs a software interrupt. On taking the SWI, the processor switches into ARM state and enters Supervisor (SVC) mode.
S3C2410A THUMB INSTRUCTION SET 4- 37 FORMAT 18: UNCONDITIONAL BRANCH [10:0] Immediate Value 15 0 1 14 1 1 13 12 11 Offset11 0 10 0 Figure 4-19. Format 18 OPERATION This instruction performs a PC-relative Branch. The THUMB assembler syntax is shown below.
THUMB INSTRUCTION SET S3C2410A 4- 38 FORMAT 19: LONG BRANCH WITH LINK [10:0] Long Branch and Link Offset High/Low [11] Low/High Offset Bit 0 = Offset high 1 = Offset low 15 0 1 14 1 1 13 12 11 Offset 1 10 H Figure 4-20. Format 19 OPERATION This format specifies a long branch with link.
S3C2410A THUMB INSTRUCTION SET 4- 39 INSTRUCTION CYCLE TIMES This instruction format does not have an equivalent ARM instruction. Table 4-20. The BL Instruction L THUMB assembler ARM equivalent Action.
THUMB INSTRUCTION SET S3C2410A 4- 40 INSTRUCTION SET EXAMPLES The following examples show ways in which the THUMB instructions may be used to generate small and efficient code.
S3C2410A THUMB INSTRUCTION SET 4- 41 GENERAL PURPOSE SIGNED DIVIDE This example shows a general purpose signed divide and remainder routine in both Thumb and ARM code.
THUMB INSTRUCTION SET S3C2410A 4- 42 Now fix up the signs of the quotient (R0) and remainder (R1) POP {R2, R3} ; Get dividend/divisor signs back EOR R3, R2 ; Result sign EOR R0, R3 ; Negate if result .
S3C2410A THUMB INSTRUCTION SET 4- 43 DIVISION BY A CONSTANT Division by a constant can often be performed by a short fixed sequence of shifts, adds and subtracts. Here is an example of a divide by 10 routine based on the algorithm in the ARM Cookbook in both Thumb and ARM code.
THUMB INSTRUCTION SET S3C2410A 4- 44 NOTES.
S3C2410A MEMORY CONTROLLER 5- 1 5 MEMORY CONTROLLER OVERVIEW The S3C2410A's memory controller provides memory control signals required for external memory access.
MEMORY CONTROLLER S 3C2410A 5- 2 [Not using NAND flash for boot ROM] SROM/SDRAM (nGCS7) 128MB 2MB/4MB/8MB/16MB /32MB/64MB/128MB 1GB HADDR[29:0] Accessible Region NOTES: 1.
S3C2410A MEMORY CONTROLLER 5- 3 FUNCTION DESCRIPTION BANK0 BUS WIDTH The data bus of BANK0 (nGCS0) should be configured to either 16-bit or 32-bit accordingly.
MEMORY CONTROLLER S 3C2410A 5- 4 SDRAM BANK ADDRESS PIN CONNECTION Table 5-2. SDRAM Bank Address Configuration Bank Size Bus Width Base Component Memory Configuration Bank Address 2MB x8 16Mb ( 1M x 8.
S3C2410A MEMORY CONTROLLER 5- 5 n WAIT PIN OPERATION If the WAIT corresponding to each memory bank is enabled, the nOE duration should be prolonged by the external nWAIT pin while the memory bank is active. nWAIT is checked from tacc-1. nOE will be deasserted at the next clock after sampling nWAIT is high.
MEMORY CONTROLLER S 3C2410A 5- 6 nXBREQ/nXBACK Pin Operation If nXBREQ is asserted, the S3C2410A will respond by lowering nXBACK. If nXBACK = L, the address/data bus and memory control signals are in Hi-z state as shown in Table 1-1. When nXBREQ is de-asserted, the nXBACK will also be de-asserted.
S3C2410A MEMORY CONTROLLER 5- 7 ROM Memory Interface Examples A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 D0 D1 D2 D3 D4 D5 D6 D7 nWE nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 nWE nOE nCE Figure 5-4.
MEMORY CONTROLLER S 3C2410A 5- 8 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 D0 D1 D2 D3 D4 D5 D6 D7 nWBE0 nOE nGCSn A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 DQ0 DQ1 DQ2 DQ3 D.
S3C2410A MEMORY CONTROLLER 5- 9 SRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A.
MEMORY CONTROLLER S 3C2410A 5- 10 SDRAM Memory Interface Examples A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 DQ0.
S3C2410A MEMORY CONTROLLER 5- 11 PROGRAMMABLE ACCESS CYCLE Tcoh Tcos Tacs HCLK A[24:0] nGCS nOE nWE nWBE D[31:0](R) D[31:0] (W) Tacc Tacp Tcah Tacs = 1 cycle Tcos = 1 cycle Tacc = 3 cycles Tacp = 2 cycles Tcoh = 1 cycle Tcah = 2 cycles Figure 5-12.
MEMORY CONTROLLER S 3C2410A 5- 12 HCLK SCKE nSCS nSCAS ADDR A10/AP RA nSRAS BA DATA (CL2) DATA (CL3) nWE DQM Trp Trcd RA Ca Da Da BA BA Cb Cc Cd Ce Db Dc Dd De Db Dc Dd De BA BA BA BA BA Bank Precharge Row Active Write Read (CL = 2, CL = 3, BL = 1) Trp = 2 cycle Tcas = 2 cycle Trcd = 2 cycle Tcp = 2 cycle Figure 5-13.
S3C2410A MEMORY CONTROLLER 5- 13 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) Register Address R/W Description Reset Value BWSCON 0x48000000 R/W Bus width & wait status control register 0x000000 BWSCON Bit Description Initial state ST7 [31] Determine SRAM for using UB/LB for bank 7.
MEMORY CONTROLLER S 3C2410A 5- 14 BUS WIDTH & WAIT CONTROL REGISTER (BWSCON) ( Continued) BWSCON Bit Description Initial state WS2 [10] Determine WAIT status for bank 2. 0 = WAIT disable 1 = WAIT enable 0 DW2 [9:8] Determine data bus width for bank 2.
S3C2410A MEMORY CONTROLLER 5- 15 BANK CONTROL REGISTER (BANKCONN: n GCS0- n GCS5) Register Address R/W Description Reset Value BANKCON0 0x48000004 R/W Bank 0 control register 0x0700 BANKCON1 0x4800000.
MEMORY CONTROLLER S 3C2410A 5- 16 BANK CONTROL REGISTER (BANKCON n : n GCS6- n GCS7) Register Address R/W Description Reset Value BANKCON6 0x4800001C R/W Bank 6 control register 0x18008 BANKCON7 0x48000020 R/W Bank 7 control register 0x18008 BANKCONn Bit Description Initial State MT [16:15] Determine the memory type for bank6 and bank7.
S3C2410A MEMORY CONTROLLER 5- 17 REFRESH CONTROL REGISTER Register Address R/W Description Reset Value REFRESH 0x48000024 R/W SDRAM refresh control register 0xac0000 REFRESH Bit Description Initial St.
MEMORY CONTROLLER S 3C2410A 5- 18 BANKSIZE REGISTER Register Address R/W Description Reset Value BANKSIZE 0x48000028 R/W Flexible bank size register 0x0 BANKSIZE Bit Description Initial State BURST_EN [7] ARM core burst operation enable. 0 = Disable burst operation.
S3C2410A MEMORY CONTROLLER 5- 19 SDRAM MODE REGISTER SET REGISTER (MRSR) Register Address R/W Description Reset Value MRSRB6 0x4800002C R/W Mode register set register bank6 xxx MRSRB7 0x48000030 R/W M.
MEMORY CONTROLLER S 3C2410A 5- 20 NOTES.
S3C2410A NAND FLASH CONTROLLER 6- 1 6 NAND FLASH CONTROLLER OVERVIEW Recently, a NOR flash memory gets high in price while an SDRAM and a NAND flash memory get moderate, motivating some users to execute the boot code on a NAND flash and execute the main code on an SDRAM.
NAND FLASH CONTROLLER S3C2410A 6- 2 BLOCK DIAGRAM Buffer Control System Bus CLE Internal Buffer (4KB) Register Bank Control State Machine ECC Encoder/ Decoder NAND Flash Interface nCE nRE nWE R/nB I/O0~I/O7 ALE Figure 6-1.
S3C2410A NAND FLASH CONTROLLER 6- 3 AUTO BOOT MODE SEQUENCE 1. Reset is completed. 2. When the auto boot mode is enabled, the first 4 KBytes of NAND flash memory is copied onto Steppingstone 4- KB internal buffer. 3. The Steppingstone is mapped to nGCS0.
NAND FLASH CONTROLLER S3C2410A 6- 4 PIN CONFIGURATION D[7:0] : Data/Command/Address In/Out Port (shared with the data bus) CLE : Command Latch Enable (Output) ALE : Address Latch Enable (Output) nFCE .
S3C2410A NAND FLASH CONTROLLER 6- 5 NAND FLASH MEMORY MAPPING NOTE: SFR means Special Function Register. Not Used SFR Area Not Used BootSRAM (4KBytes) SFR Area Not Used SDRAM (BANK7, nGCS7) SDRAM (BAN.
NAND FLASH CONTROLLER S3C2410A 6- 6 SPECIAL FUNCTION REGISTERS NAND FLASH CONFIGURATION ( NFCONF ) REGISTER Register Address R/W Description Reset Value NFCONF 0x4E000000 R/W NAND flash configuration .
S3C2410A NAND FLASH CONTROLLER 6- 7 NAND FLASH COMMAND SET (NFCMD) REGISTER Register Address R/W Description Reset Value NFCMD 0x4E000004 R/W NAND flash command set register – NFCMD Bit Description .
NAND FLASH CONTROLLER S3C2410A 6- 8 NAND FLASH OPERATION STATUS (NFSTAT) REGISTER Register Address R/W Description Reset Value NFSTAT 0x4E000010 R NAND flash operation status – NFSTAT Bit Description Initial State Reserved [16:1] Reserved – RnB [0] NAND flash memory ready/busy status.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 1 7 CLOCK & POWER MANAGEMENT OVERVIEW The clock & power management block consists of three parts: clock control, USB control, and power control.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 2 FUNCTIONAL DESCRIPTION CLOCK ARCHITECTURE Figure 7-1 shows a block diagram of the clock architecture. The main clock source comes from an external crystal (XTIpll) or an external clock (EXTCLK).
S3C2410A CLOCK & POWER MANAGEMENT 7 - 3 Nand Flash Controller OSC MPLL UPLL CLKCNTL FCLK HDIVN PDIVN Mpll Control Signal Upll POWCNTL F H P USBCNTL Test mode OM[1:0] Bus Controller Memory Controll.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 4 PHASE LOCKED LOOP (PLL) The MPLL within the clock generator, as a circuit, synchronizes an output signal with a reference input signal in frequency and phase.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 5 Divider P Loop Filter Fin M[7:0] S[1:0] PFD Divider M P[5:0] F vco PUMP VCO Divider S F ref MPLL,UPLL R C Internal 5 pF External MPLLCAP, UPLLCAP Figure 7-2.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 6 CLOCK CONTROL LOGIC The clock control logic determines the clock source to be used, i.e., the PLL clock (Mpll) or the direct external clock (XTIpll or EXTCLK).
S3C2410A CLOCK & POWER MANAGEMENT 7 - 7 Change PLL Settings In Normal Operation Mode During the operation of the S3C2410A in NORMAL mode, the user can change the frequency by writing the PMS value and the PLL lock time will be automatically inserted.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 8 FCLK, HCLK, and PCLK FCLK is used by ARM920T. HCLK is used for AHB bus, which is used by the ARM920T, the memory controller, the interrupt controller, the LCD controller, the DMA and the USB host block.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 9 POWER MANAGEMENT The power management block controls the system clocks by software for the reduction of power consumption in the S3C2410A. These schemes are related to PLL, clock control logics (FCLK, HCLK, and PCLK) and wakeup signals.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 10 IDLE POWER_OFF NORMAL (SLOW_BIT=0) SLOW (SLOW_BIT=1) IDLE_BIT=1 Interrupts, EINT[0:23], RTC alarm POWER_OFF BIT=1 EINT[15:0], RTC alarm RESET Figure 7-8. Power Management State Diagram Table 7-2. Clock and Power State in Each Power Mode Mode ARM920T AHB Modules (1) /WDT Power Management GPIO 32.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 11 NORMAL Mode In normal mode, all peripherals and the basic blocks including power management block, the CPU core, the bus controller, the memory controller, the interrupt controller, DMA, and the external master may operate fully.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 12 Users can change the frequency by enabling SLOW mode bit in CLKSLOW register in PLL on state. The SLOW clock is generated during the SLOW mode.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 13 If the user switches from SLOW mode to Normal mode by disabling SLOW_BIT and MPLL_OF F bit simultaneously in the CLKSLOW register, the frequency is changed just after the PLL lock time. Figure 7-11 shows the timing diagram.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 14 Power_OFF Mode The block disconnects the internal power. So, there occurs no power consumption due to CPU and the internal logic except the wake-up logic in this mode. Activating the Power_OFF mode requires two independent power sources.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 15 Procedure to Wake-up from Power_OFF mode 1. The internal reset signal will be asserted if one of the wake-up sources is issued. This reset duration is determined by the internal 16-bit counter logic and the reset assertion time is calculated as tRST = (65535 / XTAL_frequency).
CLOCK & POWER MANAGEMENT S3C2410A 7 - 16 Power Control of VDDi and VDDiarm In Power_OFF mode, only VDDi and VDDiarm will be turned off, which is controlled by PWREN pin. If PWREN signal is active(H), VDDi and VDDiarm are supplied by an external voltage regulator.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 17 Signaling EINT[15:0] for Wakeup The S3C2410A can be woken up from Power_OFF mode only if the following conditions are met. a) Level signals (H or L) or edge signals (rising or falling or both) are asserted on EINTn input pin.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 18 Output Port State and Power_OFF Mode The output port should have a proper logic level in power off mode, which makes the current consumption minimized. If there is no load on an output port pin, H level is preferred.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 19 CLOCK GENERATOR & POWER MANAGEMENT SPECIAL REGISTER LOCK TIME COUNT REGISTER (LOCKTIME) Register Address R/W Description Reset Value LOCKTIME 0x4C000000 R/W PLL lock time count register 0x00FFFFFF LOCKTIME Bit Description Initial State U_LTIME [23:12] UPLL lock time count value for UCLK.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 20 PLL VALUE SELECTION TABLE It is not easy to find a proper PLL value. So, We recommend referring to the following PLL value recommendation table. Input Frequency Output Frequency MDIV PDIV SDIV 12.00MHz 11.289MHz N/A N/A N/A 12.
S3C2410A CLOCK & POWER MANAGEMENT 7 - 21 CLOCK CONTROL REGISTER (CLKCON) Register Address R/W Description Reset Value CLKCON 0x4C00000C R/W Clock generator control register 0x7FFF0 CLKCON Bit Description Initial State SPI [18] Control PCLK into SPI block.
CLOCK & POWER MANAGEMENT S3C2410A 7 - 22 CLOCK SLOW CONTROL (CLKSLOW) REGISTER Register Address R/W Description Reset Value CLKSLOW 0x4C000010 R/W Slow clock control register 0x00000004 CLKSLOW Bit Description Initial State UCLK_ON [7] 0: UCLK ON (UPLL is also turned on and the UPLL lock time is inserted automatically.
S3C2410A DMA ] 8- 1 8 DMA OVERVIEW The S3C2410A supports four-channel DMA controller that is located between the system bus and the peripheral bus. Each channel of DMA controller can perform data movements between devices in the system bus and/or peripheral bus with no restrictions.
DMA S3C2410A 8- 2 DMA REQUEST SOURCES Each channel of the DMA controller can select one of DMA request source among four DMA sources if H/W DMA request mode is selected by DCON register. (Note that if S/W request mode is selected, this DMA request sources have no meaning at all.
S3C2410A DMA 8- 3 EXTERNAL DMA DREQ/DACK PROTOCOL There are three types of external DMA request/acknowledge protocols (Single service Demand, Single service Handshake and Whole service Handshake mode). Each type defines how the signals like DMA request and acknowledge are related to these protocols.
DMA S3C2410A 8- 4 Demand/Handshake Mode Comparison Demand and Handshake modes are related to the protocol between XnXDREQ and XnXDACK. Figure 8-2 shows the differences between the two modes. At the end of one transfer (Single/Burst transfer), DMA checks the state of double-synched XnXDREQ.
S3C2410A DMA 8- 5 Transfer Size — There are two different transfer sizes; unit and Burst 4. — DMA holds the bus firmly during the transfer of the chunk of data. Thus, other bus masters cannot get the bus. Burst 4 Transfer Size Four sequential Reads and Writes are performed respectively in the Burst 4 Transfer.
DMA S3C2410A 8- 6 EXAMPLES Single service in Demand Mode with Unit Transfer Size The assertion of XnXDREQ is need for every unit transfer (Single service mode). The operation continues while the XnXDREQ is asserted (Demand mode), and one pair of Read and Write (Single transfer size) is performed.
S3C2410A DMA 8- 7 DMA SPECIAL REGISTERS Each DMA channel has nine control registers (36 in total since there are four channels for DMA controller). Six of the control registers control the DMA transfer, and other three ones monitor the status of DMA controller.
DMA S3C2410A 8- 8 DMA INITIAL DESTINATION (DIDST) REGISTER Register Address R/W Description Reset Value DIDST0 0x4B000008 R/W DMA 0 initial destination register 0x00000000 DIDST1 0x4B000048 R/W DMA 1 .
S3C2410A DMA 8- 9 DMA CONTROL (DCON) REGISTER Register Address R/W Description Reset Value DCON0 0x4B000010 R/W DMA 0 control register 0x00000000 DCON1 0x4B000050 R/W DMA 1 control register 0x00000000.
DMA S3C2410A 8- 10 DMA CONTROL (DCON) REGISTER ( Continued) DCONn Bit Description Initial State SERVMODE [27] Select the service mode between Single service mode and Whole service mode. 0: Single service mode is selected in which after each atomic transfer (single or burst of length four) DMA stops and waits for another DMA request.
S3C2410A DMA 8- 11 DMA STATUS (DSTAT) REGISTER Register Address R/W Description Reset Value DSTAT0 0x4B000014 R DMA 0 count register 000000h DSTAT1 0x4B000054 R DMA 1 count register 000000h DSTAT2 0x4.
DMA S3C2410A 8- 12 CURRENT DESTINATION (DCDST) REGISTER Register Address R/W Description Reset Value DCDST0 0x4B00001C R DMA 0 current destination register 0x00000000 DCDST1 0x4B00005C R DMA 1 current.
S3C2410A DMA 8- 13 DMA MASK TRIGGER (DMASKTRIG) REGISTER Register Address R/W Description Reset Value DMASKTRIG0 0x4B000020 R/W DMA 0 mask trigger register 000 DMASKTRIG1 0x4B000060 R/W DMA 1 mask tri.
DMA S3C2410A 8- 14 S/W Work-Around The DMA auto-reload is occurred only when the DMA request is issued after the DMA counter reaches 0. So, the following code should be used in the DMA done interrupt handler before setting the DMA source address, destination address and counter register for the next auto-reload.
S3C2410A I/O PORTS 9- 1 9 I/O PORTS OVERVIEW The S3C2410A has 117 multi-functional input/output port pins. The ports are: — Port A (GPA): 23-output port — Port B (GPB): 11-input/output port — Po.
I/O PORTS S3C 2410A 9- 2 Table 9-1. S3C2410A Port Configuration Port A Selectable Pin Functions GPA22 Output only nFCE – – GPA21 Output only nRSTOUT – – GPA20 Output only nFRE – – GPA19 Ou.
S3C2410A I/O PORTS 9- 3 Table 9-1. S3C2410A Port Configuration (Continued) Port B Selectable Pin Functions GPB10 Input/output nXDREQ0 – – GPB9 Input/output nXDACK0 – – GPB8 Input/output nXDREQ.
I/O PORTS S3C 2410A 9- 4 Table 9-1. S3C2410A Port Configuration (Continued) Port D Selectable Pin Functions GPD15 Input/output VD23 nSS0 – GPD14 Input/output VD22 nSS1 – GPD13 Input/output VD21 .
S3C2410A I/O PORTS 9- 5 Table 9-1. S3C2410A Port Configuration (Continued) Port F Selectable Pin Functions GPF7 Input/output EINT7 – – GPF6 Input/output EINT6 – – GPF5 Input/output EINT5 – .
I/O PORTS S3C 2410A 9- 6 Table 9-1. S3C2410A Port Configuration (Continued) Port H Selectable Pin Functions GPH10 Input/output CLKOUT1 – – GPH9 Input/output CLKOUT0 – – GPH8 Input/output UEXTC.
S3C2410A I/O PORTS 9- 7 PORT CONTROL DESCRIPTIONS PORT CONFIGURATION REGISTER (GPACON-GPHCON) In the S3C2410A, most pins are multiplexed. So, It is require to determine which function is selected for each pin. port control register (PnCON) determines the function of each pin.
I/O PORTS S3C 2410A 9- 8 I/O PORT CONTROL REGISTER PORT A CONTROL REGISTERS (GPACON/GPADAT) Register Address R/W Description Reset Value GPACON 0x56000000 R/W Configure the pins of port A 0x7FFFFF GPA.
S3C2410A I/O PORTS 9- 9 PORT B CONTROL REGISTERS (GPBCON, GPBDAT, and GPBUP) Register Address R/W Description Reset Value GPBCON 0x56000010 R/W Configure the pins of port B 0x0 GPBDAT 0x56000014 R/W T.
I/O PORTS S3C 2410A 9- 10 PORT C CONTROL REGISTERS (GPCCON, GPCDAT, and GPCUP) Register Address R/W Description Reset Value GPCCON 0x56000020 R/W Configure the pins of port C 0x0 GPCDAT 0x56000024 R/W.
S3C2410A I/O PORTS 9- 11 G PCDAT Bit Description GPC[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin.
I/O PORTS S3C 2410A 9- 12 PORT D CONTROL REGISTERS (GPDCON, GPDDAT, and GPDUP) Register Address R/W Description Reset Value GPDCON 0x56000030 R/W Configure the pins of port D 0x0 GPDDAT 0x56000034 R/W.
S3C2410A I/O PORTS 9- 13 G PDDAT Bit Description GPD[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin.
I/O PORTS S3C 2410A 9- 14 PORT E CONTROL REGISTERS (GPECON, GPEDAT, and GPEUP) Register Address R/W Description Reset Value GPECON 0x56000040 R/W Configure the pins of port E 0x0 GPEDAT 0x56000044 R/W.
S3C2410A I/O PORTS 9- 15 GPEDAT Bit Description GPE[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin.
I/O PORTS S3C 2410A 9- 16 PORT F CONTROL REGISTERS (GPFCON, GPFDAT, and GPFPU) If GPF0 - GPF7 are used for wakeup signals in Power_OFF mode, the ports must be configured as external interrupt (set in Interrupt mode).
S3C2410A I/O PORTS 9- 17 PORT G CONTROL REGISTERS (GPGCON, GPGDAT, AND GPGUP) If GPG [7:0] are used for wakeup signals in Power_OFF mode, the ports must be configured as external interrupt (set in Interrupt mode).
I/O PORTS S3C 2410A 9- 18 GPGDAT Bit Description GPG[15:0] [15:0] When the port is configured as input port, data from external sources can be read to the corresponding pin. When the port is configured as output port, data written in this register can be sent to the corresponding pin.
S3C2410A I/O PORTS 9- 19 PORT H CONTROL REGISTERS (GPHCON, GPHDAT, AND GPHUP) Register Address R/W Description Reset Value GPHCON 0x56000070 R/W Configure the pins of port H 0x0 GPHDAT 0x56000074 R/W .
I/O PORTS S3C 2410A 9- 20 MISCELLANEOUS CONTROL REGISTER (MISCCR) Pads related USB are controlled by this register for USB host, or for USB device. Register Address R/W Description Reset Value MISCCR .
S3C2410A I/O PORTS 9- 21 DCLK CONTROL REGISTERS (DCLKCON) This register defines DCLKn signals, which work as clocks for external sources. See the following figure for how to make the DCLKn signals. The DCLKCON can actually operate only when CLKOUT[1:0] is set to send the DCLKn signals.
I/O PORTS S3C 2410A 9- 22 EXTERNAL INTERRUPT CONTROL REGISTER (EXTINT n ) The 24 external interrupts can be requested by various signaling methods. The EXTINTn configures the signaling method between the level trigger and edge trigger for the external interrupt request, and also configures the signal polarity.
S3C2410A I/O PORTS 9- 23 EXTINT1 Bit Description Reserved [31] Reserved EINT15 [30:28] Set the signaling method of the EINT15. 000 = Low level 001 = High level 01x = Falling edge triggered 10x = Rising edge triggered 11x = Both edge triggered Reserved [27] Reserved EINT14 [26:24] Set the signaling method of the EINT14.
I/O PORTS S3C 2410A 9- 24 EXTINT2 Bit Description FLTEN23 [31] Filter Enable for EINT23 0 = Disable 1= Enable EINT23 [30:28] Set the signaling method of the EINT23.
S3C2410A I/O PORTS 9- 25 EXTERNAL INTERRUPT FILTER REGISTER (EINTFLT n ) The EINTFLTn controls the length of filter for 8 external interrupts (EINT[23:16]).
I/O PORTS S3C 2410A 9- 26 EXTERNAL INTERRUPT MASK REGISTER (EINTMASK) Interrupt mask register for 20 external interrupts (EINT[23:4]). Register Address R/W Description Reset Value EINTMASK 0x560000A4 .
S3C2410A I/O PORTS 9- 27 EXTERNAL INTERRUPT PENDING REGISTER (EINTPEND n ) Interrupt pending register for 20 external interrupts (EINT[23:4]). You can clear a specific bit of the ENITPEND register by writing "1" on the corresponding bit of this register.
I/O PORTS S3C 2410A 9- 28 GENERAL STATUS REGISTER (GSTATUS n ) Register Address R/W Description Reset Value GSTATUS0 0x560000AC R External pin status Undefined GSTATUS1 0x560000B0 R Chip ID 0x32410000.
S3C2410A PWM TIMER 10- 1 10 PWM TIMER OVERVIEW The S3C2410A has five 16-bit timers. Timer 0, 1, 2, and 3 have Pulse Width Modulation (PWM) function. Timer 4 has an internal timer only with no output pins. The timer 0 has a dead-zone generator, which is used with a large current device.
PWM TIMER S3C2410A 10- 2 Clock Divider 5:1 MUX Dead Zone Generator TOUT0 TOUT1 TOUT2 Control Logic0 TCMPB0 TCNTB0 Control Logic1 TCMPB1 TCNTB1 5:1 MUX Clock Divider 5:1 MUX 5:1 MUX Control Logic2 TCMP.
S3C2410A PWM TIMER 10- 3 PWM TIMER OPERATION PRESCALER & DIVIDER An 8-bit prescaler and a 4-bit divider make the following output frequencies: 4-bit divider settings Minimum resolution (prescaler = 0) Maximum resolution (prescaler = 255) Maximum interval (TCNTBn = 65535) 1/2 (PCLK = 66.
PWM TIMER S3C2410A 10- 4 AUTO RELOAD & DOUBLE BUFFERING S3C2410A PWM Timers have a double buffering function, enabling the reload value changed for the next timer operation without stopping the current timer operation. So, although the new timer value is set, a current timer operation is completed successfully.
S3C2410A PWM TIMER 10- 5 TIMER INITIALIZATION USING MANUAL UPDATE BIT AND INVERTER BIT An auto reload operation of the timer occurs when the down counter reaches 0. So, a starting value of the TCNTn has to be defined by the user in advance. In this case, the starting value has to be loaded by the manual update bit.
PWM TIMER S3C2410A 10- 6 TIMER OPERATION TOUTn 1 2 4 6 50 110 40 40 60 20 3 7 9 10 5 8 11 Figure 10-4. Example of a Timer Operation Figure 10-4 shows the result of the following procedure: 1. Enable the auto reload function. Set the TCNTBn to 160 (50+110) and the TCMPBn to 110.
S3C2410A PWM TIMER 10- 7 PULSE WIDTH MODULATION (PWM) Write TCMPBn = 60 Write TCMPBn = 50 Write TCMPBn = 40 Write TCMPBn = 30 Write TCMPBn = 30 Write TCMPBn = Next PWM Value 60 50 40 30 30 Figure 10-5. Example of PWM PWM function can be implemented by using the TCMPBn.
PWM TIMER S3C2410A 10- 8 OUTPUT LEVEL CONTROL Inverter off Initial State Period 1 Period 2 Timer Stop Inverter on Figure 10-6. Inverter On/Off The following procedure describes how to maintain TOUT as high or low (assume the inverter is off): 1. Turn off the auto reload bit.
S3C2410A PWM TIMER 10- 9 DEAD ZONE GENERATOR The dead zone is for the PWM control in a power device. This function enables the insertion of the time gap between a turn-off of a switching device and a turn on of another switching device.
PWM TIMER S3C2410A 10- 10 DMA REQUEST MODE The PWM timer can generate a DMA request at every specific time. The timer keeps DMA request signals (nDMA_REQ) low until the timer receives an ACK signal. When the timer receives the ACK signal, it makes the request signal inactive.
S3C2410A PWM TIMER 10- 11 PWM TIMER CONTROL REGISTERS TIMER CONFIGURATION REGISTER0 (TCFG0) Timer input clock Frequency = PCLK / {prescaler value+1} / {divider value} {prescaler value} = 0~255 {divide.
PWM TIMER S3C2410A 10- 12 TIMER CONFIGURATION REGISTER1 (TCFG1) Register Address R/W Description Reset Value TCFG1 0x51000004 R/W 5-MUX & DMA mode selecton register 0x00000000 TCFG1 Bit Descriptio.
S3C2410A PWM TIMER 10- 13 TIMER CONTROL (TCON) REGISTER Register Address R/W Description Reset Value TCON 0x51000008 R/W Timer control register 0x00000000 TCON Bit Description Initial state Timer 4 auto reload on/off [22] Determine auto reload on/off for Timer 4.
PWM TIMER S3C2410A 10- 14 TIMER CONTROL (TCON) REGISTER ( Continued) TCON Bit Description Initial state Reserved [7:5] Reserved Dead zone enable [4] Determine the dead zone operation. 0 = Disable 1 = Enable 0 Timer 0 auto reload on/off [3] Determine auto reload on/off for Timer 0.
S3C2410A PWM TIMER 10- 15 TIMER 0 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB0/TCMPB0) Register Address R/W Description Reset Value TCNTB0 0x5100000C R/W Timer 0 count buffer register 0.
PWM TIMER S3C2410A 10- 16 TIMER 1 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB1/TCMPB1) Register Address R/W Description Reset Value TCNTB1 0x51000018 R/W Timer 1 count buffer register 0.
S3C2410A PWM TIMER 10- 17 TIMER 2 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB2/TCMPB2) Register Address R/W Description Reset Value TCNTB2 0x51000024 R/W Timer 2 count buffer register 0.
PWM TIMER S3C2410A 10- 18 TIMER 3 COUNT BUFFER REGISTER & COMPARE BUFFER REGISTER (TCNTB3/TCMPB3) Register Address R/W Description Reset Value TCNTB3 0x51000030 R/W Timer 3 count buffer register 0.
S3C2410A PWM TIMER 10- 19 TIMER 4 COUNT BUFFER REGISTER (TCNTB4) Register Address R/W Description Reset Value TCNTB4 0x5100003C R/W Timer 4 count buffer register 0x00000000 TCNTB4 Bit Description Init.
PWM TIMER S3C2410A 10- 20 NOTES.
S3C2410A UART 11- 1 11 UART OVERVIEW The S3C2410A UART (Universal Asynchronous Receiver and Transmitter) provides three independent asynchronous serial I/O (SIO) ports, each of which can operate in Interrupt-based or DMA-based mode. In other words, the UART can generate an interrupt or a DMA request to transfer data between CPU and the UART.
UART S3C2410A 11- 2 BLOCK DIAGRAM Buad-rate Generator Control Unit Transmitter Receiver Peripheral BUS TXDn Clock Source RXDn Transmit FIFO Register (FIFO mode) Transmit Holding Register (Non-FIFO mod.
S3C2410A UART 11- 3 UART OPERATION The following sections describe the UART operations that include data transmission, data reception, interrupt generation, baud-rate generation, Loopback mode, Infra-red mode, and auto flow control. Data Transmission The data frame for transmission is programmable.
UART S3C2410A 11- 4 Auto Flow Control (AFC) The S3C2410A's UART 0 and UART 1 support auto flow control with nRTS and nCTS signals. In case, it can be connected to external UARTs. If users want to connect a UART to a Modem, disable auto flow control bit in UMCONn register and control the signal of nRTS by software.
S3C2410A UART 11- 5 RS-232C interface If users want to connect the UART to modem interface (instead of null modem), nRTS, nCTS, nDSR, nDTR, DCD and nRI signals are needed. In this case, the users can control these signals with general I/O ports by software because the AFC does not support the RS-232C interface.
UART S3C2410A 11- 6 UART Error Status FIFO UART has the error statu s FIFO besides the Rx FIFO register. The error status FIFO indicates which data, among FIFO registers, is received with an error. The error interrupt will be issued only when the data, which has an error, is ready to read out.
S3C2410A UART 11- 7 Baud-Rate Generation Each UART's baud-rate generator provides the serial clock for the transmitter and the receiver. The source clock for the baud-rate generator can be selected with the S3C2410A's internal system clock or UEXTCLK.
UART S3C2410A 11- 8 Infra-Red (IR) Mode The S3C2410A UART block supports infra-red (IR) transmission and reception, which can be selected by setting the Infra-red-mode bit in the UART line control register (ULCONn). Figure 11-4 illustrates how to implement the IR mode.
S3C2410A UART 11- 9 Start Bit Stop Bit Data Bits SIO Frame 0101 00110 1 Figure 11-5. Serial I/O Frame Timing Diagram (Normal UART) 0 Start Bit Stop Bit Data Bits IR Transmit Frame Bit Time Pulse Width = 3/16 Bit Frame 0 0 0 0 1 1 1 1 1 Figure 11-6.
UART S3C2410A 11- 10 UART SPECIAL REGISTERS UART LINE CONTROL REGISTER There are three UART line control registers including ULCON0, ULCON1, and ULCON2 in the UART block.
S3C2410A UART 11- 11 UART CONTROL REGISTER There are three UART control registers including UCON0, UCON1 and UCON2 in the UART block. Register Address R/W Description Reset Value UCON0 0x50000004 R/W .
UART S3C2410A 11- 12 UART CONTROL REGISTER (Continued) UCONn Bit Description Initial State Transmit Mode [3:2] Determine which function is currently able to write Tx data to the UART transmit buffer register.
S3C2410A UART 11- 13 UART FIFO CONTROL REGISTER There are three UART FIFO control registers including UFCON0, UFCON1 and UFCON2 in the UART block. Register Address R/W Description Reset Value UFCON0 0.
UART S3C2410A 11- 14 UART MODEM CONTROL REGISTER There are two UART MODEM control registers including UMCON0 and UMCON1 in the UART block. Register Address R/W Description Reset Value UMCON0 0x5000000.
S3C2410A UART 11- 15 UART TX/RX STATUS REGISTER There are three UART Tx/Rx status registers including UTRSTAT0, UTRSTAT1 and UTRSTAT2 in the UART block.
UART S3C2410A 11- 16 UART ERROR STATUS REGISTER There are three UART Rx error status registers including UERSTAT0, UERSTAT1 and UERSTAT2 in the UART block.
S3C2410A UART 11- 17 UART FIFO STATUS REGISTER There are three UART FIFO status registers including UFSTAT0, UFSTAT1 and UFSTAT2 in the UART block. Register Address R/W Description Reset Value UFSTAT0.
UART S3C2410A 11- 18 UART MODEM STATUS REGISTER There are two UART modem status registers including UMSTAT0 and UMSTAT1 in the UART block. Register Address R/W Description Reset Value UMSTAT0 0x500000.
S3C2410A UART 11- 19 UART TRANSMIT BUFFER REGISTER (HOLDING REGISTER & FIFO REGISTER) There are three UART transmit buffer registers including UTXH0, UTXH1 and UTXH2 in the UART block.
UART S3C2410A 11- 20 UART BAUD RATE DIVISOR REGISTER There are three UART baud rate divisor registers including UBRDIV0, UBRDIV1 and UBRDIV2 in the UART block.
S3C2410A BUS HOST CON TROLLER 12 - 1 12 USB HOST CONTROLLER OVERVIEW S3C2410A supports 2-port USB host interface as follows: • OHCI Rev 1.0 compatible • USB Rev1.
BUS HOST CONTROLLER S3C2410A 12 - 2 USB HOST CONTROLLER SPECIAL REGISTERS The S3C2410A USB host controller complies with OHCI Rev 1.0. Refer to Open Host Controller Interface Rev 1.
S3C2410A USB DEVICE 13- 1 13 USB DEVICE CONTROLLER OVERVIEW Universal Serial Bus (USB) device controller is designed to provide a high performance full speed function controller solution with DMA interface. USB device controller allows bulk transfer with DMA, interrupt transfer and control transfer.
USB DEVICE S3C2410 A 13- 2 SIE RT_VP_OUT RT_VM_IN RT_VP_IN RXD RT_UXSUSPEND RT_UX_OEN RT_VM_OUT MC_ADDR[13:0] SIU GFI FIFOs MCU & DMA I/F MC_DATA_IN[31:0] MC_DATA_OUT[31:0] USB_CLK SYS_CLK SYS_RESETN MC_WR WR_RDN MC_CSN MC_INTR DREQN[3:0] DACKN[3:0] Figure 13-1.
S3C2410A USB DEVICE 13- 3 USB DEVICE CONTROLLER SPECIAL REGISTERS This section describes detailed functionalities about register sets of USB device controller. All special function register is byte-accessible or word-accessible. If you access byte mode offset-address is different in little endian and big endian.
USB DEVICE S3C2410 A 13- 4 USB Device Controller Special Registers (Continued) Register Name Description Offset Address EP2_DMA_TTC_M Endpoint2 DMA transfer counter middle-byte register 0x228(L) / 0x2.
S3C2410A USB DEVICE 13- 5 FUNCTION ADDRESS REGISTER (FUNC_ADDR_REG) This register maintains the USB device controller address assigned by the host. The Micro Controller Unit (MCU) writes the value received through a SET_ADDRESS descriptor to this register.
USB DEVICE S3C2410 A 13- 6 POWER MANAGEMENT REGISTER (PWR_REG) This register acts as a power control register in the USB block. Register Address R/W Description Reset Value PWR_REG 0x52000144(L) 0x520.
S3C2410A USB DEVICE 13- 7 INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) The USB core has two interrupt registers. These registers act as status registers for the MCU when it is interrupted. The bits are cleared by writing a "1" (not "0") to each bit that was set.
USB DEVICE S3C2410 A 13- 8 INTERRUPT REGISTER (EP_INT_REG/USB_INT_REG) ( Continued) Register Address R/W Description Reset Value USB_INT_REG 0x52000158(L) 0x5200015B(B) R/W (byte) USB interrupt pendin.
S3C2410A USB DEVICE 13- 9 INTERRUPT ENABLE REGISTER (EP_INT_EN_REG /USB_INT_EN_REG) Corresponding to each interrupt register, The USB device controller also has two interrupt enable registers (except resume interrupt enable). By default, usb reset interrupt is enabled.
USB DEVICE S3C2410 A 13- 10 FRAME NUMBER REGISTER (FPAME_NUM1_REG/FRAME_NUM2_REG) When the host transfers USB packets, each Start Of Frame (SOF) packet includes a frame number. The USB device controller catches this frame number and loads it into this register automatically.
S3C2410A USB DEVICE 13- 11 INDEX REGISTER (INDEX_REG) The INDEX register is used to indicate certain endpoint registers effectively. The MCU can access the endpoint registers (MAXP_REG, IN_CSR1_REG, IN_CSR2_REG, OUT_CSR1_REG, OUT_CSR2_REG, OUT_FIFO_CNT1_REG, and OUT_FIFO_CNT2_REG) for an endpoint inside the core using the INDEX register.
USB DEVICE S3C2410 A 13- 12 END POINT0 CONTROL STATUS REGISTER (EP0_CSR) This register has the control and status bits for Endpoint 0. Since a control transaction is involved with both IN and OUT tokens, there is only one CSR register, mapped to the IN CSR1 register.
S3C2410A USB DEVICE 13- 13 END POINT0 CONTROL STATUS REGISTER (EP0_CSR) ( Continued) EP0_CSR Bit MCU USB Description Initial State IN_PKT_RDY [1] SET CLEAR Set by the MCU after writing a packet of data into EP0 FIFO. The USB clears this bit once the packet has been successfully sent to the host.
USB DEVICE S3C2410 A 13- 14 END POINT IN CONTROL STATUS REGISTER (IN_CSR1_REG/IN_CSR2_REG) Register Address R/W Description Reset Value IN_CSR1_REG 0x52000184(L) 0x52000187(B) R/W (byte) IN END POINT .
S3C2410A USB DEVICE 13- 15 END POINT IN CONTROL STATUS REGISTER ( IN_CSR1_REG/IN_CSR2_REG) ( Continued) IN_CSR1_REG Bit MCU USB Description Initial State IN_PKT_RDY [0] R/SET CLEAR Set by the MCU after writing a packet of data into the FIFO. The USB clears this bit once the packet has been successfully sent to the host.
USB DEVICE S3C2410 A 13- 16 END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) Register Address R/W Description Reset Value OUT_CSR1_REG 0x52000190(L) 0x52000193(B) R/W (byte) End Point.
S3C2410A USB DEVICE 13- 17 END POINT OUT CONTROL STATUS REGISTER (OUT_CSR1_REG/OUT_CSR2_REG) ( Continued) Register Address R/W Description Reset Value OUT_CSR2_REG 0x52000194(L) 0x52000197(B) R/W (byt.
USB DEVICE S3C2410 A 13- 18 END POINT FIFO REGISTER (EPN_FIFO_REG) The EPn_FIFO_REG enables the MCU to access to the EPn FIFO. Register Address R/W Description Reset Value EP0_FIFO 0x520001C0(L) 0x520.
S3C2410A USB DEVICE 13- 19 MAX PACKET REGISTER (MAXP_REG) Register Address R/W Description Reset Value MAXP_REG 0x52000180(L) 0x52000183(B) R/W (byte) End Point MAX packet register 0x01 MAXP_REG Bit M.
USB DEVICE S3C2410 A 13- 20 END POINT OUT WRITE COUNT REGISTER (OUT_FIFO_CNT1_REG/OUT_FIFO_CNT2_REG) These registers maintain the number of bytes in the packet as the number is unloaded by the MCU.
S3C2410A USB DEVICE 13- 21 DMA INTERFACE CONTROL REGISTER (EPN_DMA_CON) Register Address R/W Description Reset Value EP1_DMA_CON 0x52000200(L) 0x52000203(B) R/W (byte) EP1 DMA interface control regist.
USB DEVICE S3C2410 A 13- 22 DMA UNIT COUNTER REGISTER (EPN_DMA_UNIT) This register is valid in Demand mode. In other modes, this register value must be set to "0x01" Register Address R/W Des.
S3C2410A USB DEVICE 13- 23 DMA FIFO COUNTER REGISTER (EPN_DMA_FIFO) This register has values in byte size in FIFO to be transferred by DMA. In case of OUT_DMA_RUN enabled, the value in OUT FIFO Write Count Register1 will be loaded in this register automatically.
USB DEVICE S3C2410 A 13- 24 DMA TOTAL TRANSFER COUNTER REGISTER (EPN_DMA_TTC_L, M, H) This register should have total number of bytes to be transferred using DMA (total 20-bit counter).
S3C2410A INTERRUPT CONTROLLER 14- 1 14 INTERRUPT CONTROLLER OVERVIEW The interrupt controller in the S3C2410A receives the request from 56 interrupt sources. These interrupt sources are provided by internal peripherals such as the DMA controller, the UART, IIC, and others.
INTERRUPT CONTROLLER S3C2410A 14- 2 INTERRUPT CONTROLLER OPERATION F-bit and I-bit of Program Status Register (PSR) If the F-bit of PSR in ARM920T CPU is set to 1, the CPU does not accept the Fast Interrupt Request (FIQ) from the interrupt controller.
S3C2410A INTERRUPT CONTROLLER 14- 3 INTERRUPT SOURCES The interrupt controller supports 56 interrupt sources as shown in the table below. Sources Descriptions Arbiter Group INT_ADC ADC EOC and Touch i.
INTERRUPT CONTROLLER S3C2410A 14- 4 INTERRUPT PRIORITY GENERATING BLOCK The priority logic for 32 interrupt requests is composed of seven rotation based arbiters: six first-level arbiters and one second-level arbiter as shown in Figure 14-2 below.
S3C2410A INTERRUPT CONTROLLER 14- 5 INTERRUPT PRIORITY Each arbiter can handle six interrupt requests based on the one bit arbiter mode control (ARB_MODE) and two bits of selection control signals (ARB_SEL) as follows: — If ARB_SEL bits are 00b, the priority order is REQ0, REQ1, REQ2, REQ3, REQ4, and REQ5.
INTERRUPT CONTROLLER S3C2410A 14- 6 INTERRUPT CONTROLLER SPECIAL REGISTERS There are five control registers in the interrupt controller: source pending register, interrupt mode register, mask register, priority register, and interrupt pending register.
S3C2410A INTERRUPT CONTROLLER 14- 7 SOURCE PENDING (SRCPND) REGISTER (Continued) SRCPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested 0 INT_RTC [30] 0 = Not requested, 1 .
INTERRUPT CONTROLLER S3C2410A 14- 8 INTERRUPT MODE (INTMOD) REGISTER This register is composed of 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the corresponding interrupt is processed in the FIQ (fast interrupt) mode.
S3C2410A INTERRUPT CONTROLLER 14- 9 INTMOD Bit Description Initial State INT_ADC [31] 0 = IRQ, 1 = FIQ 0 INT_RTC [30] 0 = IRQ, 1 = FIQ 0 INT_SPI1 [29] 0 = IRQ, 1 = FIQ 0 INT_UART0 [28] 0 = IRQ, 1 = FI.
INTERRUPT CONTROLLER S3C2410A 14- 10 INTERRUPT MASK (INTMSK) REGISTER This register also has 32 bits each of which is related to an interrupt source. If a specific bit is set to 1, the CPU does not se.
S3C2410A INTERRUPT CONTROLLER 14- 11 INTMSK Bit Description Initial State INT_ADC [31] 0 = Service available, 1 = Masked 1 INT_RTC [30] 0 = Service available, 1 = Masked 1 INT_SPI1 [29] 0 = Service av.
INTERRUPT CONTROLLER S3C2410A 14- 12 PRIORITY REGISTER (PRIORITY) Register Address R/W Description Reset Value PRIORITY 0x4A00000C R/W IRQ priority control register 0x7F PRIORITY Bit Description Initi.
S3C2410A INTERRUPT CONTROLLER 14- 13 PRIORITY REGISTER (PRIORITY) ( Continued) PRIORITY Bit Description Initial State ARB_MODE1 [1] Arbiter 1 group priority rotate enable 0 = Priority does not rotate .
INTERRUPT CONTROLLER S3C2410A 14- 14 INTERRUPT PENDING (INTPND) REGISTER Each of the 32 bits in the interrupt pending register shows whether the corresponding interrupt request, which is unmasked and waits for the interrupt to be serviced, has the highest priority .
S3C2410A INTERRUPT CONTROLLER 14- 15 INTPND Bit Description Initial State INT_ADC [31] 0 = Not requested, 1 = Requested 0 INT_RTC [30] 0 = Not requested, 1 = Requested 0 INT_SPI1 [29] 0 = Not requeste.
INTERRUPT CONTROLLER S3C2410A 14- 16 INTERRUPT OFFSET (INTOFFSET) REGISTER The value in the interrupt offset register shows which interrupt request of IRQ mode is in the INTPND register. This bit can be cleared automatically by clearing SRCPND and INTPND.
S3C2410A INTERRUPT CONTROLLER 14- 17 SUB SOURCE PENDING (SUBSRCPND) REGISTER You can clear a specific bit of the SUBSRCPND register by writing a data to this register. It clears only the bit positions of the SUBSRCPND register corresponding to those set to one in the data.
INTERRUPT CONTROLLER S3C2410A 14- 18 INTERRUPT SUB MASK (INTSUBMSK) REGISTER This register has 11 bits each of which is related to an interrupt source.
S3C2410A LCD CONTROLLER 15- 1 15 LCD CONTROLLER OVERVIEW The LCD controller in the S3C2410A consists of the logic for transferring LCD image data from a video buffer located in system memory to an external LCD driver.
LCD CONTROLLER S3 C2410A 15- 2 COMMON FEATURES The LCD controller has a dedicated DMA that supports to fetch the image data from video buffer located in system memory. Its features also include: — Dedicated interrupt functions (INT_FrSyn and INT_FiCnt) — The system memory is used as the display memory.
S3C2410A LCD CONTROLLER 15- 3 BLOCK DIAGRAM System Bus LPC3600 is a timing control logic unit for LTS350Q1-PD1 or LTS350Q1-PD2. REGBANK LCDCDMA VIDPRCS LPC3600 TIMEGEN VD[23:0] VCLK /LCD_HCLK VLINE / HSYNC / CPV VFRAME / VSYNC / STV VM / VDEN / TP LCDVF0 LCDVF1 LCDVF2 .
LCD CONTROLLER S3 C2410A 15- 4 STN LCD CONTROLLER OPERATION TIMING GENERATOR (TIMEGEN) The TIMEGEN generates the control signals for the LCD driver, such as VFRAME, VLINE, VCLK, and VM. These control signals are closely related to the configuration on the LCDCON1/2/3/4/5 registers in the REGBANK.
S3C2410A LCD CONTROLLER 15- 5 Table 15-1. Relation Between VCLK and CLKVAL (STN, HCLK = 60 MHz) CLKVAL 60 MHz/X VCLK 2 60 MHz/4 15.0 MHz 3 60 MHz/6 10.
LCD CONTROLLER S3 C2410A 15- 6 256 Level Color Mode Operation The S3C2410A LCD controller can support an 8-bit per pixel 256 color display mode. The color display mode can generate 256 levels of color using the dithering algorithm and FRC. The 8-bit per pixel are encoded into 3-bits for red, 3-bits for green, and 2-bits for blue.
S3C2410A LCD CONTROLLER 15- 7 DITHERING AND FRAME RATE CONTROL For STN LCD displays (except monochrome), video data must be processed by a dithering algorithm. The DITHFRC block has two functions, such as Time-based Dithering Algorithm for reducing flicker and Frame Rate Control (FRC) for displaying gray and color level on the STN panel.
LCD CONTROLLER S3 C2410A 15- 8 Display Types The LCD controller supports 3 types of LCD drivers: 4-bit dual scan, 4-bit single scan, and 8-bit single scan display mode. Figure 15-2 shows these 3 different display types for monochrome displays, and Figure 15-3 show these 3 different display types for color displays.
S3C2410A LCD CONTROLLER 15- 9 MEMORY DATA FORMAT (STN, BSWP=0) Mono 4-bit Dual Scan Display: Video Buffer Memory: Address Data 0000H A[31:0] 0004H B[31:0] • • • 1000H L[31:0] 1004H M[31:0] • • • LCD Panel A[31] A[30] ...... A[0] B[31] B[30] .
LCD CONTROLLER S3 C2410A 15- 10 MEMORY DATA FORMAT ( STN, BSWP = 0 ) ( Continued) In 4-level gray mode, 2 bits of video data correspond to 1 pixel. In 16-level gray mode, 4 bits of video data correspond to 1 pixel. In 256 level color mode, 8 bits (3 bits of red, 3 bits of green, and 2 bits of blue) of video data correspond to 1 pixel.
S3C2410A LCD CONTROLLER 15- 11 4-bit Dual Scan Display 4-bit Single Scan Display 8-bit Single Scan Display . . . . . . . . . . . . VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 VD3 VD2 VD1 VD0 . . . . . . VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 .
LCD CONTROLLER S3 C2410A 15- 12 VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel . . . . . . 4-bit Dual Scan Display VD3 R1 VD2 G1 VD1 B1 VD0 R2 VD3 G2 VD2 B2 VD1 R3 VD0 G3 . . . . . . 1 Pixel 4-bit Single Scan Display VD7 R1 VD6 G1 VD5 B1 VD4 R2 VD7 G2 VD6 B2 VD5 R3 VD4 G3 .
S3C2410A LCD CONTROLLER 15- 13 Timing Requirements Image data should be transferred from the memory to the LCD driver using the VD[7:0] signal. VCLK signal is used to clock the data into the LCD driver's shift register.
LCD CONTROLLER S3 C2410A 15- 14 WDLY WLH LINE1LINE2LINE3LINE4LINE5LINE6 LINE1 LINEn First Line Timing LINECNT decreases & Display the 1st line LINEBLANK First Line Check & Data Timing VFRAME V.
S3C2410A LCD CONTROLLER 15- 15 TFT LCD CONTROLLER OPERATION The TIMEGEN generates the control signals for LCD driver, such as VSYNC, HSYNC, VCLK, VDEN, and LEND signal. These control signals are highly related with the configurations on the LCDCON1/2/3/4/5 registers in the REGBANK.
LCD CONTROLLER S3 C2410A 15- 16 MEMORY DATA FORMAT (TFT) This section includes some examples of each display mode. 24BPP Display (BSWP = 0, HWSWP = 0, BPP24BL = 0) D[31:24] D[23:0] 000H Dummy Bit P1 004H Dummy Bit P2 008H Dummy Bit P3 ... (BSWP = 0, HWSWP = 0, BPP24BL = 1) D[31:8] D[7:0] 000H P1 Dummy Bit 004H P2 Dummy Bit 008H P3 Dummy Bit .
S3C2410A LCD CONTROLLER 15- 17 16BPP Display (BSWP = 0, HWSWP = 0) D[31:16] D[15:0] 000H P1 P2 004H P3 P4 008H P5 P6 ... (BSWP = 0, HWSWP = 1) D[31:16] D[15:0] 000H P2 P1 004H P4 P3 008H P6 P5 .
LCD CONTROLLER S3 C2410A 15- 18 8BPP Display (BSWP = 0, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H P1 P2 P3 P4 004H P5 P6 P7 P8 008H P9 P10 P11 P12 ... (BSWP = 1, HWSWP = 0) D[31:24] D[23:16] D[15:8] D[7:0] 000H P4 P3 P2 P1 004H P8 P7 P6 P5 008H P12 P11 P10 P9 .
S3C2410A LCD CONTROLLER 15- 19 4BPP Display (BSWP = 0, HWSWP = 0) D[31:28] D[27:24] D[23:20] D[19:16] D[15:12] D[11:8] D[7:4] D[3:0] 000H P1 P2 P3 P4 P5 P6 P7 P8 004H P9 P10 P11 P12 P13 P14 P15 P16 008H P17 P18 P19 P20 P21 P22 P23 P24 .
LCD CONTROLLER S3 C2410A 15- 20 256 PALETTE USAGE (TFT) Palette Configuration and Format Control The S3C2410A provides 256 color palette for TFT LCD Control. The user can select 256 colors from the 64K colors in these two formats. The 256 color palette consists of the 256 (depth) × 16-bit SPSRAM.
S3C2410A LCD CONTROLLER 15- 21 12 345 LCD Panel 16BPP 5:5:5+1 Format (Non-Palette) R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I R4 R3 R2 R1 R0 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0 I 12 345 LCD Panel 16BPP .
LCD CONTROLLER S3 C2410A 15- 22 INT_FrSyn VSYNC HSYNC VDEN HSYNC VCLK VD LEND VBPD+1 VSPW+1 VFPD+1 HBPD+1 HFPD+1 HSPW+1 VDEN 1 Frame 1 Line LINEVAL +1 HOZVAL+1 Figure 15-6.
S3C2410A LCD CONTROLLER 15- 23 SAMSUNG TFT LCD PANEL (3.5 ″ PORTRAIT / 256K COLOR /REFLECTIVE A-SI TFT LCD) The S3C2410A supports SEC TFT LCD panel (SAMSUNG 3.
LCD CONTROLLER S3 C2410A 15- 24 VIRTUAL DISPLAY (TFT/STN) The S3C2410A supports hardware horizontal or vertical scrolling. If the screen is scrolled, the fields of LCDBASEU and LCDBASEL in LCDSADDR1/2 registers need to be changed (see Figure 15-7), except the values of PAGEWIDTH and OFFSIZE.
S3C2410A LCD CONTROLLER 15- 25 LCD POWER ENABLE (STN/TFT) The S3C2410A provides Power enable (PWREN) function. When PWREN is set to make PWREN signal enabled, the output value of LCD_PWREN pin is controlled by ENVID.
LCD CONTROLLER S3 C2410A 15- 26 LCD CONTROLLER SPECIAL REGISTERS LCD Control 1 Register Register Address R/W Description Reset Value LCDCON1 0X4D000000 R/W LCD control 1 register 0x00000000 LCDCON1 Bit Description Initial State LINECNT (read only) [27:18] Provide the status of the line counter.
S3C2410A LCD CONTROLLER 15- 27 LCD Control 2 Register Register Address R/W Description Reset Value LCDCON2 0X4D000004 R/W LCD control 2 register 0x00000000 LCDCON2 Bit Description Initial State VBPD [31:24] TFT : Vertical back porch is the number of inactive lines at the start of a frame, after vertical synchronization period.
LCD CONTROLLER S3 C2410A 15- 28 LCD Control 3 Register Register Address R/W Description Reset Value LCDCON3 0X4D000008 R/W LCD control 3 register 0x00000000 LCDCON3 Bit Description Initial state HBPD (TFT) [25:19] TFT : Horizontal back porch is the number of VCLK periods between the falling edge of HSYNC and the start of active data.
S3C2410A LCD CONTROLLER 15- 29 LCD Control 4 Register Register Address R/W Description Reset Value LCDCON4 0X4D00000C R/W LCD control 4 register 0x00000000 LCDCON4 Bit Description Initial state MVAL [15:8] STN : These bit define the rate at which the VM signal will toggle if the MMODE bit is set to logic '1'.
LCD CONTROLLER S3 C2410A 15- 30 LCD Control 5 Register Register Address R/W Description Reset Value LCDCON5 0X4D000010 R/W LCD control 5 register 0x00000000 LCDCON5 Bit Description Initial state Reserved [31:17] This bit is reserved and the value should be '0'.
S3C2410A LCD CONTROLLER 15- 31 LCD Control 5 Register (Continued) LCDCON5 Bit Description Initial state INVVDEN [6] TFT : This bit indicates the VDEN signal polarity. 0 = Normal 1 = Inverted 0 INVPWREN [5] STN/TFT : This bit indicates the PWREN signal polarity.
LCD CONTROLLER S3 C2410A 15- 32 FRAME BUFFER START ADDRESS 1 REGISTER Register Address R/W Description Reset Value LCDSADDR1 0X4D000014 R/W STN/TFT : Frame buffer start address 1 register 0x00000000 LCDSADDR1 Bit Description Initial State LCDBANK [29:21] These bits indicate A[30:22] of the bank location for the video buffer in the system memory.
S3C2410A LCD CONTROLLER 15- 33 FRAME Buffer Start Address 3 Register Register Address R/W Description Reset Value LCDSADDR3 0X4D00001C R/W STN/TFT : Virtual screen address set 0x00000000 LCDSADDR3 Bit Description Initial State OFFSIZE [21:11] Virtual screen offset size (the number of half words).
LCD CONTROLLER S3 C2410A 15- 34 RED Lookup Table Register Register Address R/W Description Reset Value REDLUT 0X4D000020 R/W STN : Red lookup table register 0x00000000 REDLUT Bit Description Initial State REDVAL [31:0] These bits define which of the 16 shades will be chosen by each of the 8 possible red combinations.
S3C2410A LCD CONTROLLER 15- 35 Dithering Mode Register Register Address R/W Description Reset Value DITHMODE 0X4D00004C R/W STN : Dithering mode register. This register reset value is 0x00000 But, user can change this value to 0x12210. (Refer to a sample program source for the latest value of this register.
LCD CONTROLLER S3 C2410A 15- 36 Temp Palette Register Register Address R/W Description Reset Value TPAL 0X4D000050 R/W TFT : Temporary palette register. This register value will be video data at next frame. 0x00000000 TPAL Bit Description Initial state TPALEN [24] Temporary palette register enable bit.
S3C2410A LCD CONTROLLER 15- 37 LCD I nterrupt Pending Register Register Address R/W Description Reset Value LCDINTPND 0X4D000054 R/W Indicate the LCD interrupt pending register 0x0 LCDINTPND Bit Description Initial state INT_FrSyn [1] LCD frame synchronized interrupt pending bit.
LCD CONTROLLER S3 C2410A 15- 38 LCD I nterrupt Mask Register Register Address R/W Description Reset Value LCDINTMSK 0X4D00005C R/W Determine which interrupt source is masked. The masked interrupt source will not be serviced. 0x3 LCDINTMSK Bit Description Initial state FIWSEL [2] Determine the trigger level of LCD FIFO.
S3C2410A LCD CONTROLLER 15- 39 Register Setting Guide (STN) The LCD controller supports multiple screen sizes by special register setting. The CLKVAL value determines the frequency of VCLK. This value has to be determined such that the VCLK value is greater than data transmission rate.
LCD CONTROLLER S3 C2410A 15- 40 Example 1: 160 x 160, 4-level gray, 80 frame/sec, 4-bit single scan display, HCLK frequency is 60 MHz WLH = 1, WDLY = 1.
S3C2410A LCD CONTROLLER 15- 41 Gray Level Selection Guide The S3C2410A LCD controller can generate 16 gray level using Frame Rate Control (FRC). The FRC characteristics may cause unexpected patterns in gray level. These unwanted erroneous patterns may be shown in fast response LCD or at lower frame rates.
LCD CONTROLLER S3 C2410A 15- 42 Register Setting Guide (TFT LCD) The CLKVAL register value determines the frequency of VCLK and frame rate. Frame Rate = 1/ [ { (VSPW+1) + (VBPD+1) + (LIINEVAL + 1) + (.
S3C2410A ADC AND TOUCH SCREEN INTERFACE 16 - 1 16 ADC & TOUCH SCREEN INTERFACE OVERVIEW The 10-bit CMOS analog to digital converter (ADC) of the S3C2410A is a recycling typed device with 8-channel analog inputs. It converts the analog input signal into 10-bit binary digital codes at a maximum conversion rate of 500KSPS with 2.
ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 2 ADC & TOUCH SCREEN INTERFACE OPERATION BLOCK DIAGRAM Figure 16-1 shows the functional block diagram of the S3C2410A A/D converter and Touch Screen Interface. Note that the A/D converter is a recycling type.
S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 3 EXAMPLE FOR TOUCH SCREEN In this example, AIN[7] is connected with XP and AIN[5]is connected with YP pad of the touch screen panel.
ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 4 FUNCTION DESCRIPTIONS A/D Conversion Time When the PCLK frequency is 50 MHz and the prescaler value is 49, total 10-bit conversion time is given: A/D converter freq.
S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 5 3. Auto (Sequential) X/Y Position Conversion Mode. Auto (Sequential) X/Y Position Conversion Mode (AUTO_PST = 1 and XY_PST = 0) is operated in the following way: The Touch Screen Controller automatically converts X-position and Y-position.
ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 6 Programming Notes 1. The A/D converted data can be accessed by means of interrupt or polling method. With interrupt method, the overall conversion time - from A/D converter start to converted data read - may be delayed because of the return time of interrupt service routine and data access time.
S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 7 ADC AND TOUCH SCREEN INTERFACE SPECIAL REGISTERS ADC CONTROL (ADCCON) REGISTER Register Address R/W Description Reset Value ADCCON 0x58000000 R/W ADC control register 0x3FC4 ADCCON Bit Description Initial State ECFLG [15] End of conversion flag (read only).
ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 8 ADC TOUCH SCREEN CONTROL (ADCTSC) REGISTER Register Address R/W Description Reset Value ADCTSC 0x58000004 R/W ADC touch screen control register 0x058 ADCTSC Bit Description Initial State Reserved [8] This bit should be zero.
S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 9 ADC START DELAY (ADCDLY) REGISTER Register Address R/W Description Reset Value ADCDLY 0x58000008 R/W ADC start or interval delay register 0x00ff ADCDLY Bi.
ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 10 ADC CONVERSION DATA (ADCDAT0) REGISTER Register Address R/W Description Reset Value ADCDAT0 0x5800000C R ADC conversion data register - ADCDAT0 Bit Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode.
S3C2410A ADC AND TOUCH SCREEN INTERFACE 16- 11 ADC CONVERSION DATA (ADCDAT1) REGISTER Register Address R/W Description Reset Value ADCDAT1 0x58000010 R ADC conversion data register - ADCDAT1 Bit Description Initial State UPDOWN [15] Up or down state of Stylus at Waiting for Interrupt Mode.
ADC AND TOUCH SCREEN INTERFACE S3C2410A 16- 12 NOTES.
S3C2410A REAL TIME CLOCK (RTC) 17- 1 17 REAL TIME CLOCK (RTC) OVERVIEW The Real Time Clock (RTC) unit can be operated by the backup battery while the system power is off. The RTC can transmit 8-bit data to CPU as Binary Coded Decimal (BCD) values using the STRB/LDRB ARM operation.
REAL TIME CLOCK (RTC) S3C2410A 17- 2 REAL TIME CLOCK OPERATION 2 15 Clock Divider XTOrtc XTIrtc Control Register SEC Leap Year Generator Alarm Generator Reset Register 1 Hz ALMINT RTCCON RTCALM RTCRST Time Tick Generator TIME TICK TICNT 128 Hz PMWKUP PWDN MIN HOUR DATE DAY MON YEAR Figure 17-1.
S3C2410A REAL TIME CLOCK (RTC) 17- 3 READ/WRITE REGISTERS Bit 0 of the RTCCON register must be set high in order to write the BCD register in RTC block. To display the second, minute, hour, date, month, and year, the CPU should read the data in BCDSEC, BCDMIN, BCDHOUR, BCDDAY, BCDDATE, BCDMON, and BCDYEAR registers, respectively, in the RTC block.
REAL TIME CLOCK (RTC) S3C2410A 17- 4 32.768KHZ X-TAL CONNECTION EXAMPLE The Figure 17-2 shows a circuit of the RTC unit oscillation at 32.768 kHz. XTIrtc XTOrtc 32768Hz 15~ 22pF Figure 17-2.
S3C2410A REAL TIME CLOCK (RTC) 17- 5 REAL TIME CLOCK SPECIAL REGISTERS REAL TIME CLOCK CONTROL (RTCCON) REGISTER The RTCCON register consists of 4 bits such as the RTCEN, which controls the read/write enable of the BCD registers, CLKSEL, CNTSEL, and CLKRST for testing.
REAL TIME CLOCK (RTC) S3C2410A 17- 6 RTC ALARM CONTROL (RTCALM) REGISTER The RTCALM register determines the alarm enable and the alarm time. Note that the RTCALM register generates the alarm signal through both ALMINT and PMWKUP in power down mode, but only through ALMINT in the normal operation mode.
S3C2410A REAL TIME CLOCK (RTC) 17- 7 ALARM SECOND DATA (ALMSEC) REGISTER Register Address R/W Description Reset Value ALMSEC 0x57000054(L) 0x57000057(B) R/W (by byte) Alarm second data register 0x0 ALMSEC Bit Description Initial State Reserved [7] 0 SECDATA [6:4] BCD value for alarm second.
REAL TIME CLOCK (RTC) S3C2410A 17- 8 ALARM DATE DATA (ALMDATE) REGISTER Register Address R/W Description Reset Value ALMDATE 0x57000060(L) 0x57000063(B) R/W (by byte) Alarm date data register 0x01 ALMDAY Bit Description Initial State Reserved [7:6] 00 DATEDATA [5:4] BCD value for alarm date, from 0 to 28, 29, 30, 31.
S3C2410A REAL TIME CLOCK (RTC) 17- 9 RTC ROUND RESET (RTCRST) REGISTER Register Address R/W Description Reset Value RTCRST 0x5700006C(L) 0x5700006F(B) R/W (by byte) RTC round reset register 0x0 RTCRST Bit Description Initial State SRSTEN [3] Round second reset enable.
REAL TIME CLOCK (RTC) S3C2410A 17- 10 BCD HOUR (BCDHOUR) REGISTER Register Address R/W Description Reset Value BCDHOUR 0x57000078(L) 0x5700007B(B) R/W (by byte) BCD hour register Undefined BCDHOUR Bit Description Initial State Reserved [7:6] - HOURDATA [5:4] BCD value for hour.
S3C2410A REAL TIME CLOCK (RTC) 17- 11 BCD MONTH (BCDMON) REGISTER Register Address R/W Description Reset Value BCDMON 0x57000084(L) 0x57000087(B) R/W (by byte) BCD month register Undefined BCDMON Bit Description Initial State Reserved [7:5] - MONDATA [4] BCD value for month.
REAL TIME CLOCK (RTC) S3C2410A 17- 12 NOTES.
S3C2410A WATCHDOG TIMER 18- 1 18 WATCHDOG TIMER OVERVIEW The S3C2410A watchdog timer is used to resume the controller operation whenever it is disturbed by malfunctions such as noise and system errors. It can be used as a normal 16-bit interval timer to request interrupt service.
WATCHDOG TIMER S3C 2410A 18- 2 WATCHDOG TIMER OPERATION Figure 18-1 shows the functional block diagram of the watchdog timer. The watchdog timer uses only PCLK as its source clock. The PCLK frequency is prescaled to generate the corresponding watchdog timer clock, and the resulting frequency is divided again.
S3C2410A WATCHDOG TIMER 18- 3 WATCHDOG TIMER SPECIAL REGISTERS WATCHDOG TIMER CONTROL (WTCON) REGISTER The WTCON register allows the user to enable/disable the watchdog timer, select the clock signal from 4 different sources, enable/disable interrupts, and enable/disable the watchdog timer output.
WATCHDOG TIMER S3C 2410A 18- 4 WATCHDOG TIMER DATA (WTDAT) REGISTER The WTDAT register is used to specify the time-out duration. The content of WTDAT cannot be automatically loaded into the timer counter at initial watchdog timer operation. However, using 0x8000 (initial value) will drive the first time- out.
S3C2410A MMC/SD/SD IO HOST CONTROLLER 19- 1 19 MMC/SD/SDIO HOST CONTROLLER OVERVIEW The S3C2410A SD Host controller can support MMC/SD card and SDIO devices. FEATURES — SD Memory Card Spec. (ver. 1.0) / MMC Spec. (2.11) compatible — SDIO Card Spec (ver.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 2 BLOCK DIAGRAM CMD Reg (5byte) Resp Reg (17byte) CMD Control 8bit Shift Reg CRC7 Prescaler FIFO (64byte) DAT Control 32bit Shift Reg CRC16*4 DMA INT APB I/F 32 32 8 8 32 32 32 32 32 32 PADDR PSEL PCLK PWDATA [31:0] PRDATA [31:0] DREQ DACK INT TxCMD RxCMD SDCLK TxDAT[3:0] RxDAT[3:0] Figure 19-1.
S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 3 SDI OPERATION A serial clock line is synchronized with the five data lines for shifting and sampling of the information. Making the appropriate bit settings to the SDIPRE register depends on the transmission frequency.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 4 SDIO OPERATION There are two functions of the SDIO operation: SDIO Interrupt receiving and Read Wait Request generation. These two functions can operate when RcvIOInt bit and RwaitEn bit of SDICON register is activated respectively.
S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 5 SDI SPECIAL REGISTERS SDI Control (SDICON) Register Register Address R/W Description Reset Value SDICON 0x5A000000 R/W SDI control register 0x0 SDICON Bit De.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 6 SDI Command Argument Register (SDICARG) Register Address R/W Description Reset Value SDICARG 0x5A000008 R/W SDI command argument register 0x0 SDICARG Bit Des.
S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 7 SDI Command Status (SDICSTA) Register Register Address R/W Description Reset Value SDICSTA 0x5A000010 R/(W) SDI command status register 0x0 SDICSTA Bit Description Initial Value Response CRC Fail(RspCrc) [12] R/W CRC check failed when command response received.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 8 SDI Response Register 0 (SDIRSP0) Register Address R/W Description Reset Value SDIRSP0 0x5A000014 R SDI response register 0 0x0 SDIRSP0 Bit Description Initi.
S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 9 SDI Data / Busy Timer (SDIDTIMER) Register Register Address R/W Description Reset Value SDIDTIMER 0x5A000024 R/W SDI data / busy timer register 0x2000 SDIDTI.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 10 SDI Data Control (SDIDCON) Register Register Address R/W Description Reset Value SDIDCON 0x5A00002C R/W SDI data control register 0x0 SDIDCON Bit Descriptio.
S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 11 SDI Data Remain Counter (SDIDCNT) Register Register Address R/W Description Reset Value SDIDCNT 0x5A000030 R SDI data remain counter register 0x0 SDIDCNT Bi.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 12 SDI Data Status (SDIDSTA) Register Register Address R/W Description Reset Value SDIDSTA 0x5A000034 R/(W) SDI data status register 0x0 SDIDSTA Bit Description Initial Value Read Wait Request Occur (RWaitReq) [10] R/W Read wait request signal transmits to SD card.
S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 13 SDI FIFO Status (SDIFSTA) Register Register Address R/W Description Reset Value SDIFSTA 0x5A000038 R SDI FIFO status register 0x0 SDIFSTA Bit Description In.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 14 SDI Data (SDIDAT) Register Register Address R/W Description Reset Value SDIDAT 0x5A00003C(Li/W, Li/B, Bi/W) 0x5A00003F(Bi/B) R/W SDI data register 0x0 SDIDAT Bit Description Initial State Data Register [31:0] This field contains the data to be transmitted or received over the SDI channel.
S3C2410A MMC/SD/SDIO HOST CONTROLLER 19- 15 SDI Interrupt Mask (SDIIMSK) Register Register Address R/W Description Reset Value SDIIMSK 0x5A000040 R/W SDI interrupt mask register 0x0 SDIIMSK Bit Description Initial Value RspCrc Interrupt Enable [17] Response CRC error interrupt.
MMC/SD/SDIO HOST CONTROLLER S3C2410A 19- 16 SDI D ata/ B usy T imer R egister SDI data/ busy timer register has 16-bit counter. In case of 25MHz operation, the countable maximum time is 2.6ms (40ns * 0x10000). But, some cards have very long access time (TAAC), their TAAC are up to 100ms.
S3C2410A IIC-BUS INTERFACE 20- 1 20 IIC-BUS INTERFACE OVERVIEW The S3C2410A RISC microprocessor can support a multi-master IIC-bus serial interface. A dedicated serial data line (SDA) and a serial clock line (SCL) carry information between bus masters and peripheral devices which are connected to the IIC-bus.
IIC-BUS INTERFACE S3C2410A 20- 2 PCLK Address Register SDA 4-bit Prescaler IIC-Bus Control Logic IICSTAT IICCON Comparator Shift Register Shift Register (IICDS) Data Bus SCL Figure 20-1. IIC-Bus Block Diagram NOTE: IIC DATA HOLD TIME The IIC data hold time(tSDAH) is minimum 0ns.
S3C2410A IIC-BUS INTERFACE 20- 3 IIC-BUS INTERFACE The S3C2410A IIC-bus interface has four operation modes: — Master transmitter mode — Master receive mode — Slave trans mitter mode — Slave receive mode Functional relationships among these operating modes are described below.
IIC-BUS INTERFACE S3C2410A 20- 4 DATA TRANSFER FORMAT Every byte placed on the SDA line should be eight bits in length. The bytes can be unlimitedly transmitted per transfer. The first byte following a Start condition should have the address field. The address field can be transmitted by the master when the IIC-bus is operating in Master mode.
S3C2410A IIC-BUS INTERFACE 20- 5 SDA Acknowledgement Signal from Receiver SCL S 1 2 7 8 9 1 2 9 Acknowledgement Signal from Receiver MSB ACK Byte Complete, Interrupt within Receiver Clock Line Held Low by receiver and/or transmitter Figure 20-4.
IIC-BUS INTERFACE S3C2410A 20- 6 READ-WRITE OPERATION In Transmitter mode, when the data is transferred, the IIC-bus interface will wait until IIC-bus Data Shift (IICDS) register receives a new data. Before the new data is written into the register, the SCL line will be held low, and then released after it is written.
S3C2410A IIC-BUS INTERFACE 20- 7 FLOWCHARTS OF OPERATIONS IN EACH MODE The following steps must be executed before any IIC Tx/Rx operations. 1) Write own slave address on IICADD register, if needed. 2) Set IICCON register. a) Enable interrupt b) Define SCL period 3) Set IICSTAT to enable Serial Output Write slave address to IICDS.
IIC-BUS INTERFACE S3C2410A 20- 8 Write slave address to IICDS. Write 0xB0 (M/R Start) to IICSTAT. The data of the IICDS (slave address) is transmitted. ACK period and then interrupt is pending. Write 0x90 (M/R Stop) to IICSTAT. Read a new data from IICDS.
S3C2410A IIC-BUS INTERFACE 20- 9 IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Write data to IICDS. The IIC address match interrupt is generated. Clear pending bit to resume. The data of the IICDS is shifted to SDA.
IIC-BUS INTERFACE S3C2410A 20- 10 IIC detects start signal. and, IICDS receives data. IIC compares IICADD and IICDS (the received slave address). Read data from IICDS. The IIC address match interrupt is generated. Clear pending bit to resume. SDA is shifted to IICDS.
S3C2410A IIC-BUS INTERFACE 20- 11 IIC-BUS INTERFACE SPECIAL REGISTERS MULTI-MASTER IIC-BUS CONTROL (IICCON) REGISTER Register Address R/W Description Reset Value IICCON 0x54000000 R/W IIC-Bus control register 0x0X IICCON Bit Description Initial State Acknowledge generation (note 1) [7] IIC-bus acknowledge enable bit.
IIC-BUS INTERFACE S3C2410A 20- 12 MULTI-MASTER IIC-BUS CONTROL/STATUS (IICSTAT) REGISTER Register Address R/W Description Reset Value IICSTAT 0x54000004 R/W IIC-Bus control/status register 0x0 IICSTAT Bit Description Initial State Mode selection [7:6] IIC-bus master/slave Tx/Rx mode select bits.
S3C2410A IIC-BUS INTERFACE 20- 13 MULTI-MASTER IIC-BUS ADDRESS (IICADD) REGISTER Register Address R/W Description Reset Value IICADD 0x54000008 R/W IIC-Bus address register 0xXX IICADD Bit Description Initial State Slave address [7:0] 7-bit slave address, latched from the IIC-bus.
IIC-BUS INTERFACE S3C2410A 20- 14 NOTES.
S3C2410A IIS-BUS INTERFACE 21- 1 21 IIS-BUS INTERFACE OVERVIEW Currently, many digital audio systems are attracting the consumers on the market, in the form of compact discs, digital audio tapes, digital sound processors, and digital TV sound.
IIS-BUS INTERFACE S3C2410A 21- 2 BLOCK DIAGRAM ADDR DATA CNTL PCLK BRFC IPSR_A IPSR_B TxFIFO RxFIFO SCLKG CHNC SFTR LRCK SCLK SD CDCLK Figure 21-1. IIS-Bus Block Diagram FUNCTIONAL DESCRIPTIONS Bus interface, register bank, and state machine (BRFC): Bus interface logic and FIFO access are controlled by the state machine.
S3C2410A IIS-BUS INTERFACE 21- 3 DMA Transfer In this mode, transmit or receive FIFO is accessible by the DMA controller. DMA service request in transmit or receive mode is made by the FIFO ready flag automatically. Transmit and Receive Mode In this mode, IIS bus interface can transmit and receive data simultaneously.
IIS-BUS INTERFACE S3C2410A 21- 4 IIS-bus Format (N=8 or 16) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) MSB (1st) LRCK SCLK SD LEFT RIGHT LEFT MSB-justified Format (N=8 or 16) 2nd Bit N-1th Bit LSB (last) MSB (1st) 2nd Bit N-1th Bit LSB (last) LRCK SCLK SD LEFT RIGHT MSB (1st) Figure 21-2.
S3C2410A IIS-BUS INTERFACE 21- 5 Table 21-2 Usable Serial Bit Clock Frequency (IISCLK = 16 or 32 or 48fs) Serial bit per channel 8-bit 16-bit Serial clock frequency (IISCLK) @CODECLK = 256fs 16fs, 32f.
IIS-BUS INTERFACE S3C2410A 21- 6 IIS MODE REGISTER (IISMOD) REGISTER Register Address R/W Description Reset Value IISMOD 0x55000004 (Li/W, Li/HW, Bi/W) 0x55000006 (Bi/HW) R/W IIS mode register 0x0 IISMOD Bit Description Initial State Master/slave mode select [8] 0 = Master mode (IISLRCK and IISCLK are output mode).
S3C2410A IIS-BUS INTERFACE 21- 7 IIS PRESCALER (IISPSR) REGISTER Register Address R/W Description Reset Value IISPSR 0x55000008 (Li/HW, Li/W, Bi/W) 0x5500000A (Bi/HW) R/W IIS prescaler register 0x0 II.
IIS-BUS INTERFACE S3C2410A 21- 8 IIS FIFO CONTROL (IISFCON) REGISTER Register Address R/W Description Reset Value IISFCON 0x5500000C (Li/HW, Li/W, Bi/W) 0x5500000E (Bi/HW) R/W IIS FIFO interface regis.
S3C2410A SPI INTERFACE 22- 1 22 SPI INTERFACE OVERVIEW The S3C2410A Serial Peripheral Interface (SPI) can interface the serial data transfer. The S3C2410A includes two SPI, each of which has two 8-bit shift registers for transmission and receiving, respectively.
SPI INTERFACE S3C2 410A 22- 2 BLOCK DIAGRAM 8bit Prescaler 1 PCLK Status Register 1 Prescaler Register 1 /SS nSS 0 SCK SPICLK 0 MOSI SPIMOSI 0 MISO SPIMISO 0 Pin Control Logic 0 MSTR Tx 8bit Shift Reg.
S3C2410A SPI INTERFACE 22- 3 SPI OPERATION Using the SPI interface, the S3C2410A can send/receive 8 –bit data simultaneously with an external device. A serial clock line is synchronized with the two data lines for shifting and sampling of the information.
SPI INTERFACE S3C2 410A 22- 4 SPI Transfer Format The S3C2410A supports 4 different format to transfer the data. Figure 22-2 shows four waveforms for SPICLK.
S3C2410A SPI INTERFACE 22- 5 Transmitting Procedure by DMA 1. The SPI is configured as DMA mode. 2. DMA is configured properly. 3. The SPI requests DMA service. 4. DMA transmits 1byte data to the SPI. 5. The SPI transmits the data to card. 6. Return to Step 3 until DMA count becomes 0.
SPI INTERFACE S3C2 410A 22- 6 Guide 1) DMA mode: This mode cannot be used at SPI slave Rx mode with f ormat B. 2) Polling mode: DATA_READ signal should be delayed by 1phase of SPICLK at SPI slave Rx mode with format B. 3) Interrupt mode: DATA_READ signal should be delayed 1phase of SPICLK at SPI slave Rx mode with format B.
S3C2410A SPI INTERFACE 22- 7 SPI SPECIAL REGISTERS SPI CONTROL REGISTER Register Address R/W Description Reset Value SPCON0 0x59000000 R/W SPI channel 0 control register 0x00 SPCON1 0x59000020 R/W SPI channel 1 control register 0x00 SPCONn Bit Description Initial State SPI Mode Select (SMOD) [6:5] Determine how and by what SPTDAT is read/written.
SPI INTERFACE S3C2 410A 22- 8 SPI STATUS REGISTER Register Address R/W Description Reset Value SPSTA0 0x59000004 R SPI channel 0 status register 0x01 SPSTA1 0x59000024 R SPI channel 1 status register .
S3C2410A SPI INTERFACE 22- 9 SPI PIN CONTROL REGISTER When the SPI system is enabled, the direction of pins, except nSS pin, is controlled by MSTR bit of SPCONn register.
SPI INTERFACE S3C2 410A 22- 10 SPI Baud Rate Prescaler Register Register Address R/W Description Reset Value SPPRE0 0x5900000C R/W SPI cannel 0 baud rate prescaler register 0x00 SPPRE1 0x5900002C R/W SPI cannel 1 baud rate prescaler register 0x00 SPPREn Bit Description Initial State Prescaler Value [7:0] Determine SPI clock rate as above equation.
S3C2410A BUS PRIORITIES 23- 1 23 BUS PRIORITIES OVERVIEW The bus arbitration logic determines the priorities of bus masters. It supports a combination of rotation priority mode and fixed priority mode.
BUS PRIORITIES S3C 2410A 23- 2 NOTES.
S3C2410A ELECTRICAL DATA 24- 1 24 ELECTRICAL DATA ABSOLUTE MAXIMUM RATINGS Table 24-1. Absolute Maximum Rating Parameter Symbol Rating (200MHz / 266MHz) Unit DC Supply Voltage V DDi 1.8V / 2.0V V DD 2.7 V DDRTC 1.8V V DD 2.7 V DDIO 3.3V V DD 3.8 DC Input Voltage V IN 3.
ELECTRICAL DATA S3C 2410A 24- 2 D.C. ELECTRICAL CHARACTERISTICS Table 24-3 and 24-4 define the DC electrical characteristics for the standard LVCMOS I/O buffers.
S3C2410A ELECTRICAL DATA 24- 3 Table 24-4. USB DC Electrical Characteristics Symbol Parameter Condition Min Max Unit V IH High level input voltage 2.5 V V IL Low level input voltage 0.8 V I IH High level input current Vin = 3.3V -10 10 µ A I IL Low level input current Vin = 0.
ELECTRICAL DATA S3C 2410A 24- 4 A.C. ELECTRICAL CHARACTERISTICS 1/2 V DD 1/2 V DD t XTALCYC NOTE: The clock input from the X TIpll pin. Figure 24-1. XTIpll Clock Timing t EXTHIGH V IH 1/2 V DD V IL V IL V IH V IH 1/2 V DD t EXTLOW t EXTCYC NOTE: The clock input from the EXTCLK pin.
S3C2410A ELECTRICAL DATA 24- 5 HCLK (internal) SCLK CLKOUT (HCLK) t HC2CK t HC2SCLK Figure 24-4. HCLK/CLKOUT/SCLK in case that EXTCLK is used EXTCLK t RESW nRESET Figure 24-5.
ELECTRICAL DATA S3C 2410A 24- 6 nRESET XTIpll or EXTCLK VCO output MCU operates by XTIpll or EXTCLK clcok. Clock Disable t PLL FCLK is new frequency. Power PLL can operate after OM[3:2] is latched. PLL is configured by S/W first time. VCO is adapted to new clock frequency.
S3C2410A ELECTRICAL DATA 24- 7 XTIpll VCO Output Clock Disable FCLK Several slow clocks (XTIpll or EXTCLK) Power_OFF mode is initiated. t OSC2 EXTCLK Figure 24-7.
ELECTRICAL DATA S3C 2410A 24- 8 HCLK nGCSx tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH '1' Figure 24-8.
S3C2410A ELECTRICAL DATA 24- 9 HCLK nGCSx tRAD nOE DATA ADDR nBEx tRCD tROD tROD tRCD tRBED tRBED Tacc tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 24-9.
ELECTRICAL DATA S3C 2410A 24- 10 HCLK nGS nOE ADDR tXnBRQS XnBREQ tXnBRQH XnBACK 'HZ' 'HZ' 'HZ' tXnBACKD tXnBACKD tHZD tHZD tHZD Figure 24-10.
S3C2410A ELECTRICAL DATA 24- 11 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nWBEx '1' Tcoh Tcah tRCD tROD tRDS tRDH tROD tRCD tRAD Tacc Figure 24-11.
ELECTRICAL DATA S3C 2410A 24- 12 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR nBEx Tcoh Tcah tRCD tROD tRDS tRDH tROD tRCD tRAD tRBED tRBED Tacc Figure 24-12.
S3C2410A ELECTRICAL DATA 24- 13 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nWBEx Tcoh Tcah tRCD tRWD tRDD tRWD tRCD tRAD Tcos Tcoh tRWBED tRWBED Tacc tRDD Figure 24-13.
ELECTRICAL DATA S3C 2410A 24- 14 HCLK nGCSx tRAD Tacs nWE Tcos DATA ADDR nBEx Tcoh Tcah tRCD tRWD tRDD tRWD tRCD tRAD tRBED tRBED Tacc tRDD Figure 24-14.
S3C2410A ELECTRICAL DATA 24- 15 HCLK nGCSx nOE Tacc = 6cycle nWait DATA ADDR Tacs Tcos delayed NOTE : T he status of nWait is checked at (Tacc-1) cycle.
ELECTRICAL DATA S3C 2410A 24- 16 HCLK nGCSx tRAD Tacs nOE Tcos DATA ADDR tRCD tROD tRDS tRDH tRAD Tacc Figure 24-17. Masked-ROM Single READ Timing (Tacs = 2, Tcos = 2, Tacc = 8, PMC = 01/10/11) HCLK nGCSx tRAD nOE DATA ADDR tRCD tROD tRDS tRDH tRAD Tacc Tpac Tpac Tpac Tpac tRAD tRAD tRAD tRAD tRDS tRDH tRDS tRDH tRDS tRDH tRDS tRDH Figure 24-18.
S3C2410A ELECTRICAL DATA 24- 17 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Figure 24-19.
ELECTRICAL DATA S3C 2410A 24- 18 SCLK nSRAS nSCAS ADDR/BA nBEx tXnBRQH tXnBRQS SCKE A10/AP nGCSx nWE '1' XnBREQ XnBACK EXTCLK tXnBACKD tXnBACKD 'HZ' 'HZ' 'HZ' &.
S3C2410A ELECTRICAL DATA 24- 19 SCLK nSRAS tSAD nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSCSD tSRD 'HZ' '1' tSWD Figure 24-21.
ELECTRICAL DATA S3C 2410A 24- 20 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED Tcl Figure 24-22.
S3C2410A ELECTRICAL DATA 24- 21 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED Tcl .
ELECTRICAL DATA S3C 2410A 24- 22 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSCSD tSRD '1' '1' 'HZ' Trc NOTE: Before executing auto/self refresh command, all banks must be in idle state.
S3C2410A ELECTRICAL DATA 24- 23 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDS tSDH SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Tcl Tcl Tcl Figure 24-25.
ELECTRICAL DATA S3C 2410A 24- 24 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD tSAD tSCSD tSRD '1' '1' 'HZ' Trc tCKED '.
S3C2410A ELECTRICAL DATA 24- 25 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' tSAD tSAD Trcd tSCSD tSRD tSCSD tSAD tSAD tSBED tSWD Figure 24-27.
ELECTRICAL DATA S3C 2410A 24- 26 SCLK nSRAS tSAD Trp nSCAS DATA ADDR/BA nBEx tSRD tSDD tSDD SCKE A10/AP nGCSx tSCSD nWE tSAD tSCD tSWD '1' Trcd tSBED Figure 24-28.
S3C2410A ELECTRICAL DATA 24- 27 XSCLK tXRS tXRS tCADL tCADH tXAD XnXDREQ XnXDACK Read Write Min. 3SCLK Figure 24-29. External DMA Timing (Handshake, Single transfer) VSYNC HSYNC VDEN Tf2hsetup Tf2hhold Tvspw Tvbpd Tvfpd HSYNC VCLK VD VDEN LEND Tl2csetup Tvclkh Tvclk Tvclkl Tvdhold Tvdsetup Tve2hold Tle2chold Tlewidth Figure 24-30.
ELECTRICAL DATA S3C 2410A 24- 28 tSDIS IISCLK IISLRCK IISDO CODECLK IISDI tSDIH tSDO tLRCK Figure 24-31. IIS Interface Timing tSTOPH tSTARTS tSDAS tSDAH tBUF tSCLHIGH tSCLLOW fSCL IICSCL IICSDA Figure 24-32.
S3C2410A ELECTRICAL DATA 24- 29 SDCLK tSDCD SDCMD (out) tSDCH tSDCS tSDDD SDCMD (in) tSDDH tSDDS SDDATA[3:0] (in) SDDATA[3:0] (out) Figure 24-33. SD/MMC Interface Timing SPICLK tSPIMOD tSPISIH tSPISIS tSPISOD tSPIMIH tSPIMIS SPIMOSI (MO) SPIMOSI (SI) SPIMISO (SO) SPIMISO (MI) Figure 24-34.
ELECTRICAL DATA S3C 2410A 24- 30 TACLS TWRPH0 TWRPH1 COMMAND TWRPH0 TWRPH1 ADDRESS HCLK ALE nFWE DATA[7:0] DATA[7:0] HCLK CLE nFWE tCLED tCLED tWED tWED tWDS tWDH tALED tWED tWDS tALED tWED tWDH TACLS Figure 24-35.
S3C2410A ELECTRICAL DATA 24- 31 Table 24-6. Clock Timing Constants (V DDi =V DDalive =V DDiarm = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V DDMOP = 3.
ELECTRICAL DATA S3C 2410A 24- 32 Table 24-7. ROM/SRAM Bus Timing Constants (V DDi =V DDalive =V DDiarm = 1.8V ± 0.15 / 2.0 V ± 0.1 V, T A = -40 to 85 ° C, V DDMOP = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit ROM/SRAM Address Delay t RAD 3 – 11 / 10.
S3C2410A ELECTRICAL DATA 24- 33 Table 24-9. External Bus Request Timing Constants (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit eXternal Bus Request Setup time t XnBRQS 2 – 5 / 4 ns eXternal Bus Request Hold time t XnBRQH – – 1 / 0.
ELECTRICAL DATA S3C 2410A 24- 34 Table 24-11. TFT LCD Controller Module Signal Timing Constants (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.
S3C2410A ELECTRICAL DATA 24- 35 Table 24-13. IIC BUS Controller Module Signal Timing (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit SCL clock frequency f SCL – – std. 100 fast 400 kHz SCL high level pulse width t SCLHIGH std.
ELECTRICAL DATA S3C 2410A 24- 36 Table 24-15. SPI Interface Transmit/Receive Timing Constants (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Min Typ. Max Unit SPI MOSI Master Output Delay time t SPIMOD 1.
S3C2410A ELECTRICAL DATA 24- 37 Table 24-17. USB Full Speed Output Buffer Electrical Characteristics (V DD = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V EXT = 3.3V ± 0.3V) Parameter Symbol Condition Min Max Unit Driver Characteristics Transition Time Rise Time Fall Time TR TF CL = 50pF CL = 50pF 4.
ELECTRICAL DATA S3C 2410A 24- 38 Table 24-19. NAND Flash Interface Timing Constants (V DDi =V DDalive =V DDiarm = 1.8V ± 0.15 / 2.0 V ± 0.1 V , T A = -40 to 85 ° C, V DDIO = 3.3V ± 0.3V) Parameter Symbol Min Typ Max Unit NFCON Chip Enable delay t CED – – 6.
S3C2410A MECHANICAL DATA 25- 1 25 MECHANICAL DATA PACKAGE DIMENSIONS 14.00 14.00 0.35 ± 0.05 1.16 0.45 ± 0.05 C 0.12 MAX 0.10 C A B 0.15 TOLERANCE ± 0.
MECHANICAL DATA S3C2410A 25- 2 A1 INDEX MARK 0.80 x 16 = 12.80 ± 0.05 14.00 0.80 0.80 A B C D E F G H J K L M N P R T U 8 9 10 11 12 13 14 15 16 17 5 6 7 1 2 3 4 14.00 0.15 0.08 M M C C A B 272 - 0.45 ± 0.05 TOLERANCE ± 0.10 Figure 25-2. 272-FBGA-1414 Package Dimension 2 (Bottom View) The recommended land open size is 390 – 410 µ m (0.
ARM920T PROCESSOR I NTRODUCTION 1- 1 Appendix 1 ARM920T INTRODUCTION ABUOT THE INTRODUCTION The ARM920T is a member of the ARM9TDMI family of general-purpose microprocessors, which includes: — ARM9TDMI (ARM9TDMI core) — ARM940T (ARM9TDMI core plus cache and protection unit) — ARM920T (ARM9TD MI core plus cache and MMU).
INTRODUCTION ARM920 T PROCESSOR 1- 2 PROCESSOR FUNCTIONAL BLOCK DIAGRAM Shows the functional block diagram of the ARM920T External Coprocessor Interface Instruction Cache Instruction MMU R13 ARM9TDMI .
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 1 Appendix 2 PROGRAMMER'S MODEL ABOUT THE PROGRAMMER'S MODEL ARM920T incorporates the ARM9TDMI integer core, which implements the ARMv4T architecture. It executes the ARM and Thumb instruction sets, and includes Embedded ICE JTAG software debug features.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 2 ABOUT THE ARM9TDMI PROGRAMMER'S MODEL The ARM9TDMI processor core implements ARM v4T architecture, and so executes the ARM 32-bit instruction set and the compressed Thumb 16-bit instruction set. The programmer's model is fully described in the ARM Architecture Reference Manual.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 3 INSTRUCTION SET EXTENSION SPACES All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 4 CP15 REGISTER MAP SUMMARY CP15 defines 16 registers. The register map for CP15 is shown in Table 2 -2 Table 2-2.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 5 ACCESSING CP15 REGISTERS Throughout this section the following terms and abbreviations are used. Table 2-3. CP15 Abbreviations Term Abbreviation Description Unpredictable UNP For reads, the data returned when reading from this location is unpredictable; it could have any value.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 6 Addresses in ARM920T Three distinct types of address exist in an ARM920T system: • virtual address (VA) • modified virtual address (MVA) • physical address (PA). Below is an example of the address manipulation when the ARM9TDMI requests an instruction.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 7 REGISTER 0: ID CODE REGISTER This is a read-only register which returns a 32-bit device ID code. The ID code register is accessed by reading CP15 register 0 with the opcode_2 field set to any value other than 1 (the CRm field should be zero when reading).
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 8 REGISTER 0: CACHE TYPE REGISTER This is a read-only register which contains information about the size and architecture of the caches, allowing operating systems to establish how to perform such operations as cache cleaning and lockdown.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 9 Bits [20:18] give the data cache size. Bits [8:6] give the instruction cache size. Table 2 -7 on page 2 -9 shows the meaning of values used for cache size encoding.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 10 Table 2 -9 shows the meaning of values us ed for line length encoding Table 2-9. Line Length Encoding Bits [13:12]/Bits [1:0] Words Per Line 00 2 01 4 10 8 11 16 REGISTER 1: CONTROL REGISTER This register contains the control bits of the ARM920T.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 11 Table 2-10. Control Register 1-bit Functions Register Bits Name Function Value 31 iA bit Asynchronous clock select See Table 2 -11 on page 2 -11. 30 nF bit notFastBus select See Table 2 -11 on page 2 -11.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 12 Enabling the MMU Care must be taken with the address mapping of the code sequence used to enable the MMU, see Enabling the MMU on page 3 -25.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 13 REGISTER 3: DOMAIN ACCESS CONTROL REGISTER Register 3 is the read/write domain access control register consisting of sixteen 2-bit fields. Each of these 2-bit fields defines the access permissions for the domains shown in Table 2 -13.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 14 REGISTER 4: RESERVED Accessing (reading or writing) this register will cause unpredictable behavior. REGISTER 5: FAULT STATUS REGISTERS Register 5 is the fault status register (FSR).
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 15 REGISTER 6: FAULT ADDRESS REGISTER Register 6 is the fault address register (FAR) which contains the modified virtual address of the access being attempted when the last fault occurred. The FAR is only updated for data faults, not for prefetch faults.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 16 The function of each cache operation is selected by the opcode_2 and CRm fields in the MCR instruction used to write CP15 register 7. Writing other opcode_2 or CRm values is unpredictable. Reading from CP15 register 7 is unpredictable.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 17 The operations which can be carried out upon a single cache line identify the line using the data passed in the MCR instruction. The data is interpreted using one of the following formats: 31 0 4 3 0 Modified virtual address 5 0 0 0 0 2 1 SBZ Figure 2-2.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 18 REGISTER 8: TLB OPERATIONS Register 8 is a write-only register used to manage the translation lookaside buffers (TLBs), the instruction TLB and the data TLB.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 19 REGISTER 9: CACHE LOCK DOWN REGISTER Register 9 is the cache lock down register. The cache lock down register is 0x0 on reset.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 20 Figure 2-5 shows the format of bits in register 9 31 19 15 16 11 12 21 20 0 0 8 7 4 3 0 0000 0 Index 0 26 25 24 23 10 9 5 0000 2 1 0 0 0 0 0 0 0 0 13 14 17 18 000 22 UNP/SBZ 6 000 Figure 2-5. Register 9 Table 2-18 shows the instructions needed to access the cache lock down register: Table 2-18.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 21 REGISTER 10: TLB LOCK DOWN REGISTER Register 10 is the TLB lock down register. The TLB lock down register is 0x0 on reset.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 22 Load a single entry into I TLB location 0, make it immune to Invalidate All and lock it down: MCR to CP15 register 10, opcode_2 = 0x1, Base Value = 0, Current Victim = 0, P = 1 MCR I prefetch. Assuming an I TLB miss occurs, then entry 0 will be loaded.
ARM920T PROCESSOR P ROGRAMMER'S MODEL 2- 23 Using the process Identifier (ProcID) Addresses issued by the ARM9TDMI core in the range 0 to 32MB are translated by CP15 register 13, the ProcID register. Address A becomes A + (ProcID x 32MB). It is this translated address that is seen by both the Caches and MMU.
PROGRAMMER'S MODEL ARM920T PROCESSOR 2- 24 Changing the ProcID - performing a fast context switch A fast context switch is done by writing to CP15 register 13. The contents of the caches and TLBs do not have to be flushed after a fast context switch because they still hold valid address tags.
ARM920T PROCESSOR M MU 3- 1 Appendix 3 MMU ABOUT THE MMU ARM920T implements an enhanced ARM Architecture V4 MMU to provide translation and access permission checks for the instruction and data address ports of the ARM9TDMI.
MMU ARM920T PROCESS OR 3- 2 TRANSLATED ENTRIES Each TLB caches 64 translated entries. During CPU memory accesses, the TLB provides the protection information to the access control logic.
ARM920T PROCESSOR M MU 3- 3 MMU PROGRAM ACCESSIBLE REGISTERS Table 3-1 shows system control coprocessor (CP15) registers which are used, in conjunction with page table descriptors stored in memory, to determine the operation of the MMU Table 3-1.
MMU ARM920T PROCESS OR 3- 4 All the CP15 MMU registers, except register 8, contain state and can be read using MRC instructions and written using MCR instructions. Registers 5 and 6 are also written by the MMU during a data abort. Writing to Register 8 causes the MMU to perform a TLB operation, to manipulate TLB entries.
ARM920T PROCESSOR M MU 3- 5 Translation table 4096 entries TTB base Indexed by modified virtual address bits [31:20] 1MB Section base Indexed by modified virtual address bits [19:0] Coarse page table .
MMU ARM920T PROCESS OR 3- 6 HARDWARE TRANSLATION PROCESS TRANSLATION TABLE BASE The hardware translation process is initiated when the TLB does not contain a translation for the requested modified virtual address.
ARM920T PROCESSOR M MU 3- 7 LEVEL ONE FETCH Bits 31:14 of the translation table base register are concatenated with bits 31:20 of the modified virtual address to produce a 30-bit address as illustrated in Figure 3-3 on page 3 -7.
MMU ARM920T PROCESS OR 3- 8 LEVEL ONE DESCRIPTOR The level one descriptor returned is either a section descriptor a coarse page table descriptor, or a fine page table descriptor. A section descriptor provides the base address of a 1MB block of memory.
ARM920T PROCESSOR M MU 3- 9 SECTION DESCRIPTOR Bits 3:2 (C & B) indicate whether the area of memory mapped by this section is treated as write-back cacheable, write-through cacheable, non-cached buffered or non-cached non-buffered. Bit 4 should be written to 1 for backward compatibility.
MMU ARM920T PROCESS OR 3- 10 TRANSLATING SECTION REFERENCES Figure 3-5 illustrates the complete section translation sequence. Note that access permissions contained in the level one descriptor must be checked before the physical address is generated.
ARM920T PROCESSOR M MU 3- 11 LEVEL TWO DESCRIPTOR If the level one fetch returns either a coarse page table descriptor or a fine page table descriptor, this provides the base address of the page table to be used. The page table is then accessed and a level two descriptor is returned.
MMU ARM920T PROCESS OR 3- 12 Bit 3:2 (C & B) indicate whether the area of memory mapped by this page is treated as write-back cacheable, write- through cacheable, non cached buffered or non-cached non-buffered. Domain access control on page 3 -19 and Fault checking sequence on page 3 -21 show how to interpret the access permission (ap) bits.
ARM920T PROCESSOR M MU 3- 13 31 0 Table index 19 20 Page index 0 31 0 Translation base Translation table base 13 14 31 0 Translation base 13 14 1 2 0 Table index 18 Level one descriptor 1 31 0 Coarse .
MMU ARM920T PROCESS OR 3- 14 TRANSLATING SMALL PAGE REFERENCES Figure 3-8 illustrates the complete translation sequence for a 4KB small page. If a small page descriptor is included in a fine page table, the upper two bits of the page index and low-order two bits of the fine page table index overlap.
ARM920T PROCESSOR M MU 3- 15 TRANSLATING TINY PAGE REFERENCES Figure 3-9 on page 3 -16 illustrates the complete translation sequence for a 1KB tiny page.
MMU ARM920T PROCESS OR 3- 16 31 0 Table index 19 20 Page index 0 31 0 Translation base Translation table base 13 14 31 0 Translation base 13 14 1 2 0 Table index 18 Level one descriptor 1 31 0 Fine pa.
ARM920T PROCESSOR M MU 3- 17 SUB-PAGES Access permissions can be defined for sub pages of small and large pages. If, during a page walk, a small or large page has a non-identical sub page permission, only the sub page being accessed is written into the TLB.
MMU ARM920T PROCESS OR 3- 18 FAULT ADDRESS AND FAULT STATUS REGISTERS On a data abort, the MMU places an encoded 4 bit value, FS[3:0], along with the 4 -bit encoded domain number, in the Data fault status register (FSR). Similarly, on a prefetch abort, in the Prefetch fault status register, intended for debug purposes only.
ARM920T PROCESSOR M MU 3- 19 DOMAIN ACCESS CONTROL MMU accesses are primarily controlled via domains. There are 16 domains and each has a 2-bit field to define access to it. Two types of user are supported, clients and managers. See Table 3-5. The domains are defined in the domain access control register.
MMU ARM920T PROCESS OR 3- 20 Table 3-6 shows how to interpret the access permission (AP) bits and how their interpretation is dependent upon the S and R bits (control register bits 8 and 9).
ARM920T PROCESSOR M MU 3- 21 FAULT CHECKING SEQUENCE The sequence by which the MMU checks for access faults is different for sections and pages. The sequence for both types of access is shown below. The conditions that generate each of the faults are described on the following pages.
MMU ARM920T PROCESS OR 3- 22 ALIGNMENT FAULT If alignment fault is enabled (A-Bit in CP15 register 1 set), the MMU will generate an alignment fault on any data word access the address of which is not word aligned, or on any halfword access the address of which is not halfword aligned, irrespective of whether the MMU is enabled or not.
ARM920T PROCESSOR M MU 3- 23 PERMISSION FAULT If the 2-bit domain field returns 01 (client) then access permissions are checked as follows: Section If the level one descriptor defines a section-mapped access, the AP bits of the descriptor define whether or not the access is allowed according to Table 3-6 on page 3 -20.
MMU ARM920T PROCESS OR 3- 24 EXTERNAL ABORTS In addition to the MMU-generated aborts the ARM920T can be externally aborted by the AMBA bus, which may be used to flag an error on an external memory access. However, not all accesses can be aborted in this way and the Bus Interface Unit (BIU) ignores external aborts that can not be handled.
ARM920T PROCESSOR M MU 3- 25 INTERACTION OF THE MMU AND CACHES The MMU is enabled and disabled using bit 0 of the CP15 control register. ENABLING THE MMU To enable the MMU: 1) Program the translation table base and doma in access control registers. 2) Program level 1 and level 2 page tables as required.
MMU ARM920T PROCESS OR 3- 26 NOTES.
ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 1 Appendix 4 CACHES, WRITE BUFFER ABOUT THE CACHES AND WRITE BUFFER The ARM920T includes an instruction cache, a data cache, a write buffer and a Physical Address TAG RAM to reduce the effect of main memory bandwidth and latency on performance.
CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 2 INSTRUCTION CACHE The ARM920T includes a 16KB instruction cache. The ICache has 512 lines of 32 bytes (8 words), arranged as a 64- way set-associative cache and uses modified virtual addresses, translated by CP15 register 13 (see Address translation on page 3 -4), from the ARM9TDMI core.
ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 3 INSTRUCTION CACHE ENABLE/DISABLE On reset, the ICache entries are all invalidated and the ICache is disabled.
CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 4 INSTRUCTION CACHE REPLACEMENT ALGORITHM The ICache and DCache replacement algorithm is selected by the RR bit in the CP15 control register (CP15 register 1, bit 14). Random replacement is selected at reset. Setting the RR bit to 1 selects round-robin replacement.
ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 5 DATA CACHE AND WRITE BUFFER The ARM920T includes a 16KB data cache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance.
CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 6 DATA CACHE AND WRITE BUFFER ENABLE/DISABLE On reset, all DCache entries are invalidated, the DCache is disabled, and the write buffer contents are discarded. There is no explicit write buffer enable bit implemented in ARM920T.
ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 7 Table 4-1. Data Cache and Write Buffer Configuration Ctt and Ccr Btt Data cache, write buffer and memory access behavior 0 (1) 0 Non-cached, non-buffered (NCNB) Reads and writes are not cached and always perform accesses on the ASB and may be externally aborted.
CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 8 A linefill performs an 8-word burst read from the ASB and places it as a new entry in the cache, possible replacing another line at the same location within the cache.
ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 9 DATA CACHE ORGANIZATION The DCache is organized as 8 segments, each containing 64 lines, and each line containing 8-words. The line's position within its segment is a number from 0 to 63 which is called the index.
CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 10 CACHE COHERENCE The ICache and DCache contain copies of information normally held in main memory. If these copies of memory information get out of step with each other because one is updated and the others are not updated, they are said to have become incoherent.
ARM920T PROCESSOR C ACHES, WRITE BUFFER 4- 11 Situations which necessitate cache cleaning and invalidating include: • writing instructions to a cacheable area of memory using STR or STM instructions.
CACHES, WRITE BUFFER ARM920T PROCESSOR 4- 12 CACHE CLEANING WHEN LOCKDOWN IS IN USE The clean D single entry (using index) and clean and invalidate D entry (using index) operations can leave the victim pointer set to the index value used by the operation.
ARM920T PROCESSOR C LOCK MODES 5- 1 Appendix 5 CLOCK MODES OVERVIEW The ARM920T has two functional clock inputs, BCLK and FCLK. Internally, the ARM920T is clocked by GCLK, which can be seen on the CPCLK output as shown in Figure 5-1.
CLOCK MODES ARM920T PROCESSOR 5- 2 F ASTBUS MODE In this mode of operation the BCLK input is the source for GCLK. The FCLK input is ignored. This mode is typically used in systems with high speed memory. SYNCHRONOUS MODE This mode is typically used in systems with low speed memory.
ARM920T PROCESSOR C LOCK MODES 5- 3 A SYNCHRONOUS MODE This mode is typically used in systems with low speed memory. In this mode of operation GCLK can be sourced from BCLK and FCLK. BCLK is used to control the AMBA memory interface. FCLK is used to control the internal ARM9TDMI processor core and any cache operations.
CLOCK MODES ARM920T PROCESSOR 5- 4 NOTES.
(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
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(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
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(For duplicate copies of this form, and for additional ordering information, please contact your local Sa m sung sales representative. Samsung sales offices are listed on the back cover of this book.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Samsung S3C2410A c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Samsung S3C2410A - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Samsung S3C2410A, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Samsung S3C2410A va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Samsung S3C2410A, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Samsung S3C2410A.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Samsung S3C2410A. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Samsung S3C2410A ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
