Manuel d'utilisation / d'entretien du produit PD754244 du fabricant NEC
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User’s Manual Printed in Japan µ PD754144, 754244 4-Bit Single-Chip Micr ocontr oller s µ PD754144 µ PD754244 Document No . U10676EJ3V0UM00 (3rd edition) Date Published Nov ember 2002 N CP(K) 199.
2 User’ s Manual U10676EJ3V0UM [MEMO].
3 User’ s Manual U10676EJ3V0UM EEPROM is a trademark of NEC Electronics Corporation. MS-DOS is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. IBM DOS, PC/AT, and PC DOS are trademarks of International Business Machines Corporation.
4 User ’ s Manual U10676EJ3V0UM These commodities, technology or software, must be exported in accordance with the export administration regulations of the exporting country. Diversion contrary to the law of that country is prohibited. The information in this document is current as of July, 2002.
5 User ’ s Manual U10676EJ3V0UM Regional Information • Device availability • Ordering information • Product release schedule • Availability of related technical literature • Development en.
6 User ’ s Manual U10676EJ3V0UM Major Revisions in This Edition Pages Description p.210 Correction of description in figure in 7.9 Application of Interrupt (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) p.
7 User’ s Manual U10676EJ3V0UM INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the µ PD754144 and 754244 and design application systems using these microcontrollers.
8 User’ s Manual U10676EJ3V0UM Related Documents The related documents indicated in this pub lication may include preliminary versions. Howe v er , preliminar y versions are not marked as such. Documents related to devices Document Name Document No.
9 User’ s Manual U10676EJ3V0UM T ABLE OF CONTENTS CHAPTER 1 GENERAL ..................................................................................................................... 17 1.1 Functional Outline .....................................
10 User’ s Manual U10676EJ3V0UM 4.6 Accumulator ........................................................................................................................ 7 0 4.7 Stack P ointer (SP) and Stac k Bank Select Register (SBS) ..............
11 User’ s Manual U10676EJ3V0UM CHAPTER 7 INTERRUPT AND TEST FUNCTIONS ........................................................................ 1 86 7.1 Configuration of Interrupt Controller ..........................................................
12 User’ s Manual U10676EJ3V0UM 11.4.10 Branch instructions ................................................................................................................ 2 79 11.4.11 Subroutine/stack control instructions .........................
13 User’ s Manual U10676EJ3V0UM LIST OF FIGURES (1/3) Figure No . Title P age 3-1 Selecting MBE = 0 Mode and MBE = 1 Mode .................................................................................. 33 3-2 Data Memory Configuration and Addressing Range for Each Addressing Mode .
14 User’ s Manual U10676EJ3V0UM LIST OF FIGURES (2/3) Figure No . Title P age 6-18 Example of Incorrect Resonator Connection ..................................................................................... 1 09 6-19 CPU Clock Switching Example .
15 User’ s Manual U10676EJ3V0UM LIST OF FIGURES (3/3) Figure No . Title P age 7-9 Interrupt Nesting by Changing Interrupt Status Flag ........................................................................ 1 99 7-10 Block Diagr am of KR4 to KR7 ...
16 User’ s Manual U10676EJ3V0UM LIST OF T ABLES T able No . Title P age 2-1 Pin Functions of Digital I/O P or ts ....................................................................................................... 2 4 2-2 Functions of Non-P or t Pins .
17 User’ s Manual U10676EJ3V0UM CHAPTER 1 GENERAL The µ PD754144 and 754244 are 4-bit single-chip microcontrollers in the NEC 75XL Series, the successor to the 75X Series that boasts a wealth of variations.
CHAPTER 1 GENERAL 18 User’ s Manual U10676EJ3V0UM 1.1 Functional Outline Item µ PD754144 µ PD754244 Instruction execution time • 4, 8, 16, 64 µ s (at f CC = 1.0 MHz) • 0.95, 1.91, 3.81, 15.3 µ s (at f X = 4.19 MHz) • 0.67, 1.33, 2.67, 10.7 µ s (at f X = 6.
CHAPTER 1 GENERAL 19 User’ s Manual U10676EJ3V0UM 1.2 Ordering Information Part Number Package µ PD754141GS- ××× -BA5 20-pin plastic SOP (7.62 mm (300)) µ PD754141GS- ××× -GJG 20-pin plastic SSOP (7.62 mm (300)) µ PD754244GS- ××× -BA5 20-pin plastic SOP (7.
CHAPTER 1 GENERAL 20 User’ s Manual U10676EJ3V0UM 1.4 Block Diagram Basic interval timer/watchdog timer 8-bit timer counter #0 8-bit timer counter #1 8-bit timer counter #2 Cascaded 16-bit timer cou.
CHAPTER 1 GENERAL 21 User ’ s Manual U10676EJ3V0UM 1.5 Pin Configuration (Top View) • Pin configuration of µ PD754144 • 20-pin plastic SOP (7.62 mm (300)) µ PD754144GS- ××× -BA5 • 20-pin plastic SSOP (7.
CHAPTER 1 GENERAL 22 User ’ s Manual U10676EJ3V0UM • Pin configuration of µ PD754244 • 20-pin plastic SOP (7.62 mm (300)) µ PD754244GS- ××× -BA5 • 20-pin plastic SSOP (7.62 mm (300)) µ PD754244GS- ××× -GJG IC: Internally Connected (Directly connect to V DD .
CHAPTER 1 GENERAL 23 User’ s Manual U10676EJ3V0UM Pin Name P30 to P33: Port 3 P60 to P63: Port 6 P70 to P73: Port 7 P80: Port 8 KR4 to KR7: Key return 4 to 7 INT0: External vectored interrupt 0 PTH0.
24 User’ s Manual U10676EJ3V0UM CHAPTER 2 PIN FUNCTIONS 2.1 Pin Functions of µ PD754244 Table 2-1. Pin Functions of Digital I/O Ports Pin Name I/O Alternate Function 8-Bit After Reset I/O Circuit F.
CHAPTER 2 PIN FUNCTIONS 25 User’ s Manual U10676EJ3V0UM Table 2-2. Functions of Non-Port Pins Pin Name I/O Alternate Function After Reset I/O Circuit Function Type Note PTO0 Output P3 0 Timer counter output pins. Input E-B PTO1 P31 PTO2 P32 INT0 Input P61 Edge-detected vectored interrupt input Input F -A (edge to be detected is selectable).
CHAPTER 2 PIN FUNCTIONS 26 User’ s Manual U10676EJ3V0UM 2.2 Description of Pin Functions 2.2.1 P30 to P33 (Port 3) ... I/O pins shared with PTO0 to PTO2 P60 to P63 (Port 6) .
CHAPTER 2 PIN FUNCTIONS 27 User’ s Manual U10676EJ3V0UM 2.2.4 INT0 ... input pin shared with port 6 This pin inputs the vectored interrupt signal detected by the edge. A noise eliminator is selectable for INT0. The edge to be detected can be specified by using the edge detection mode register (IM0).
CHAPTER 2 PIN FUNCTIONS 28 User’ s Manual U10676EJ3V0UM 2.2.8 AV REF ... input pin shared with port 6 This is a reference voltage input pin. An analog reference voltage for the programmable threshold port is input.
CHAPTER 2 PIN FUNCTIONS 29 User ’ s Manual U10676EJ3V0UM 2.2.12 IC The IC (Internally Connected) pin sets the test mode in which the µ PD754244 is tested before shipment. Usually, you should directly connect the IC pin to the V DD pin with as short a wiring length as possible.
CHAPTER 2 PIN FUNCTIONS 30 User ’ s Manual U10676EJ3V0UM 2.3 Pin I/O Circuits The following diagrams show the I/O circuits of the pins of the µ PD754244.
CHAPTER 2 PIN FUNCTIONS 31 User’ s Manual U10676EJ3V0UM 2.4 Processing of Unused Pins Table 2-3. Recommended Connection of Unused Pins Pin Recommended Connection P30/PTO0 Input: Independently connect to V SS or V DD via a resistor. P31/PTO1 Output: Leave open.
32 User’ s Manual U10676EJ3V0UM CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP The 75XL architecture employed for the µ PD754244 has the following features. • Internal RAM: 4K words × 4 bits MAX. (12-bit address) • Expandability peripheral hardware To realize these superb features, the following techniques have been employed.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 33 User’ s Manual U10676EJ3V0UM Figure 3-1. Selecting MBE = 0 Mode and MBE = 1 Mode Internal hardware and static RAM manipulation repeated.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 34 User ’ s Manual U10676EJ3V0UM 3.1.2 Addressing mode of data memory The 75XL architecture employed for the µ PD754244 provides the seven types of addressing modes shown in Table 3-1.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 35 User ’ s Manual U10676EJ3V0UM Figure 3-2. Data Memory Configuration and Addressing Range for Each Addressing Mode 000H 01FH 020H 07FH 0FFH 400H 4.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 36 User ’ s Manual U10676EJ3V0UM Table 3-1. Addressing Modes Addressing Mode Representation Specified Address • When MBE = 0 When mem = 00H to 7FH: MB = 0 When mem = 80H to FFH: MB = 15 • When MBE = 1: MB = MBS 4-bit direct addressing mem Address specified by MB and mem.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 37 User’ s Manual U10676EJ3V0UM (2) 4-bit direct addressing (mem) This addressing mode is used to directly address the entire memory space in 4-bit units by using the operand of an instruction.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 38 User ’ s Manual U10676EJ3V0UM Examples 1. To compare data 50H to 57H with data 60H to 67H DATA1 EQU 57H DATA2 EQU 67H SET1 MBE SEL MB0 MOV D, #DATA1 SHR 4 MOV HL, #DATA2 AND 0FFH LOOP : MOV A, @DL SKE A, @HL ; A = (HL)? BR NO ; NO DECS L ; YES, L ← L – 1 BR LOOP 2.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 39 User ’ s Manual U10676EJ3V0UM Figure 3-3. Updating Address of Static RAM 0XH FXH @DL 4-bit transfer DECS D INCS D DECS L INCS L @HL 4-bit manipul.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 40 User ’ s Manual U10676EJ3V0UM (5) 8-bit register indirect addressing (@HL) This addressing mode is used to indirectly address the entire data memory space in 8-bit units by using a data pointer (HL register pair).
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 41 User ’ s Manual U10676EJ3V0UM (6) Bit manipulation addressing This addressing mode is used to manipulate the entire memory space in bit units (such as Boolean processing and bit transfer).
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 42 User ’ s Manual U10676EJ3V0UM (b) Specific address bit register indirect addressing (pmem, @L) This addressing mode is to indirectly specify and successively manipulate the bits of the peripheral hardware units such as I/O ports.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 43 User ’ s Manual U10676EJ3V0UM (c) Special 1-bit direct addressing (@H+mem.bit) This addressing mode enables bit manipulation in the entire memory space.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 44 User ’ s Manual U10676EJ3V0UM (7) Stack addressing This addressing mode is used to save or restore data when interrupt servicing or subroutine processing is executed. The address of data memory bank 0 pointed to by the stack pointer (8 bits) is specified in this addressing mode.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 45 User ’ s Manual U10676EJ3V0UM RBE Register Bank Fixed to 0 Remark × = don ’ t care RBE is automatically saved or restored during subroutine processing and therefore can be set while subroutine processing is under execution.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 46 User ’ s Manual U10676EJ3V0UM Figure 3-4. Example of Using Register Banks <Main program> <Single interrupt> <Nesting of two interr.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 47 User ’ s Manual U10676EJ3V0UM (1) To use as 4-bit registers When the general-purpose register area is used as a 4-bit register area, a total of eight general-purpose registers, X, A, B, C, D, E, H, and L, specified by RBE and RBS can be used as shown in Figure 3-5.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 48 User ’ s Manual U10676EJ3V0UM Figure 3-5. Configuration of General-Purpose Registers (4-Bit Processing) X H D B X H D B X H D B X H D B 01H 03H 0.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 49 User ’ s Manual U10676EJ3V0UM Figure 3-6. Configuration of General-Purpose Registers (8-Bit Processing) XA HL DE BC XA' HL' DE' BC.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 50 User ’ s Manual U10676EJ3V0UM 3.3 Memory-Mapped I/O The µ PD754244 employs memory-mapped I/O that maps peripheral hardware units such as I/O ports and timers to addresses F80H to FFFH on the data memory space, as shown in Figure 3-2.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 51 User ’ s Manual U10676EJ3V0UM Figure 3-7 shows the I/O map of the µ PD754244. The meanings of the symbols shown in this figure are as follows. • Symbol ............ Name indicating the address of an internal hardware unit Can be written in operands of instructions • R/ W .
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 52 User’ s Manual U10676EJ3V0UM ................................................................................ ................................................................................ Figure 3-7.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 53 User ’ s Manual U10676EJ3V0UM Figure 3-7. µ PD754244 I/O Map (2/8) Hardware name (symbol) Number of bits that Bit Address R/W can be manipulated.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 54 User ’ s Manual U10676EJ3V0UM Figure 3-7. µ PD754244 I/O Map (3/8) Hardware name (symbol) Number of bits that Bit Address R/W can be manipulated manipulation Remarks b3 b2 b1 b0 1-bit 4-bit 8-bit addressing FA0H Timer counter 0 mode register (TM0) R/W (W) – mem.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 55 User ’ s Manual U10676EJ3V0UM ..................................................................
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 56 User ’ s Manual U10676EJ3V0UM Figure 3-7. µ PD754244 I/O Map (5/8) Hardware name (symbol) Number of bits that Bit Address R/W can be manipulated manipulation Remarks b3 b2 b1 b0 1-bit 4-bit 8-bit addressing FC0H Bit sequential buffer 0 (BSB0) R/W mem.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 57 User ’ s Manual U10676EJ3V0UM Figure 3-7. µ PD754244 I/O Map (6/8) Hardware name (symbol) Number of bits that Bit Address R/W can be manipulated manipulation Remarks b3 b2 b1 b0 1-bit 4-bit 8-bit addressing FD0H Unmounted to FD3H FD4H Programmable threshold port (PTH0) R – mem.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 58 User ’ s Manual U10676EJ3V0UM Figure 3-7. µ PD754244 I/O Map (7/8) Hardware name (symbol) Number of bits that Bit Address R/W can be manipulated.
CHAPTER 3 FEATURES OF ARCHITECTURE AND MEMORY MAP 59 User ’ s Manual U10676EJ3V0UM Figure 3-7. µ PD754244 I/O Map (8/8) Hardware name (symbol) Number of bits that Bit Address R/W can be manipulated manipulation Remarks b3 b2 b1 b0 1-bit 4-bit 8-bit addressing FF0H Unmounted to FF2H FF3H Port 3 (PORT3) R/W – fmem.
60 User’ s Manual U10676EJ3V0UM CHAPTER 4 INTERNAL CPU FUNCTION 4.1 Function to Select MkI and MkII Modes 4.1.1 Difference between MkI and MkII modes The CPU of the µ PD754244 has two modes to be selected: MkI and MkII. These modes can be selected by using bit 3 of the stack bank select register (SBS).
CHAPTER 4 INTERNAL CPU FUNCTION 61 User’ s Manual U10676EJ3V0UM 4.1.2 Setting stack bank select register (SBS) The MkI mode or MkII mode is selected by using the stack bank select register (SBS). Figure 4-1 shows the format of this register. The stack bank select register is set by using a 4-bit memory manipulation instruction.
CHAPTER 4 INTERNAL CPU FUNCTION 62 User ’ s Manual U10676EJ3V0UM 4.2 Program Counter (PC) ··· 12 bits This is a binary counter that holds an address of the program memory.
CHAPTER 4 INTERNAL CPU FUNCTION 63 User ’ s Manual U10676EJ3V0UM 4.3 Program Memory (ROM) ··· 4096 × 8 bits The program memory stores a program, interrupt vector table, the reference table of the GETI instruction, and table data. The program memory is addressed by the program counter.
CHAPTER 4 INTERNAL CPU FUNCTION 64 User ’ s Manual U10676EJ3V0UM Figure 4-3. Program Memory Map 76 0 MBE RBE Internal reset start address (higher 4 bits) Internal reset start address (lower 8 bits) .
CHAPTER 4 INTERNAL CPU FUNCTION 65 User ’ s Manual U10676EJ3V0UM 4.4 Data Memory (RAM) ... 128 words × 4 bits The data memory consists of data areas and a peripheral hardware area as shown in Figure 4-4. The data memory consists the following banks with each bank made up of 256 words × 4 bits.
CHAPTER 4 INTERNAL CPU FUNCTION 66 User ’ s Manual U10676EJ3V0UM 4.4.2 Specifying bank of data memory A memory bank is specified by a 4-bit memory bank select register (MBS) when bank specification is enabled by setting a memory bank enable flag (MBE) to 1 (MBS = 0, 4, or 15).
CHAPTER 4 INTERNAL CPU FUNCTION 67 User ’ s Manual U10676EJ3V0UM Figure 4-4. Data Memory Map 000H 01FH 020H 07FH 080H 0FFH 400H 41FH 420H 4FFH F80H FFFH 128 × 4 Not incorporated 16 × 8 Not incorpo.
CHAPTER 4 INTERNAL CPU FUNCTION 68 User ’ s Manual U10676EJ3V0UM The contents of the data memory are undefined at reset. Therefore, they must be initialized at the beginning of program execution (RAM clear).
CHAPTER 4 INTERNAL CPU FUNCTION 69 User ’ s Manual U10676EJ3V0UM 0 3 B 0 3 C 0 3 D 0 3 E 0 3 H 0 3 L 0 3 X 0 3 A One bank 000H 001H 002H 003H 004H 005H 006H 007H 008H 00FH 010H 017H 018H .
CHAPTER 4 INTERNAL CPU FUNCTION 70 User ’ s Manual U10676EJ3V0UM 4.6 Accumulator With the µ PD754244, the A register or XA register pair functions as an accumulator. The A register plays a central role in 4-bit data processing, while the XA register pair is used for 8-bit data processing.
CHAPTER 4 INTERNAL CPU FUNCTION 71 User ’ s Manual U10676EJ3V0UM When 00H is set to SP as the initial value, memory bank 0 specified by SBS is used as the stack area, starting from the highest address (07FH). The stack area can be used only in memory bank 0.
CHAPTER 4 INTERNAL CPU FUNCTION 72 User ’ s Manual U10676EJ3V0UM Figure 4-9. Data Saved to Stack Memory (MkI Mode) Stack SP – 1 SP PUSH instruction Stack PC11-PC8 PC3-PC0 PC7-PC4 CALL, CALLF instr.
CHAPTER 4 INTERNAL CPU FUNCTION 73 User ’ s Manual U10676EJ3V0UM Figure 4-11. Data Saved to Stack Memory (MkII Mode) Stack SP – 1 SP PUSH instruction Stack PC11-PC8 PC3-PC0 PC7-PC4 CALL, CALLA, CA.
CHAPTER 4 INTERNAL CPU FUNCTION 74 User ’ s Manual U10676EJ3V0UM 4.8 Program Status Word (PSW) ... 8 Bits The program status word (PSW) consists of flags closely related to the operations of the processor.
CHAPTER 4 INTERNAL CPU FUNCTION 75 User ’ s Manual U10676EJ3V0UM Table 4-4. Carry Flag Manipulation Instruction Instruction (Mnemonic) Operation and Processing of Carry Flag Carry flag manipulation .
CHAPTER 4 INTERNAL CPU FUNCTION 76 User ’ s Manual U10676EJ3V0UM (3) Interrupt status flags (IST1 and IST0) The interrupt status flags record the status of the processing under execution (for details, refer to Table 7-3 IST, IST0, and Interrupt Servicing ).
CHAPTER 4 INTERNAL CPU FUNCTION 77 User ’ s Manual U10676EJ3V0UM (5) Register bank enable flag (RBE) This flag specifies whether the register bank of the general-purpose registers is expanded or not. RBE can be set or reset at any time by using a bit manipulation instruction, regardless of the setting of the memory bank.
CHAPTER 4 INTERNAL CPU FUNCTION 78 User ’ s Manual U10676EJ3V0UM 4.9 Bank Select Register (BS) The bank select register (BS) consists of a register bank select register (RBS) and a memory bank select register (MBS) which specify the register bank and the memory bank to be used, respectively.
CHAPTER 4 INTERNAL CPU FUNCTION 79 User ’ s Manual U10676EJ3V0UM RBE Register Bank (2) Register bank select register (RBS) The register bank select register specifies a register bank to be used as general-purpose registers. It can select bank 0 to 3.
80 User’ s Manual U10676EJ3V0UM CHAPTER 5 EEPROM The µ PD754244 incorporates not only a 128-word × 4-bit static RAM but also a 16-word × 8-bit EEPROM (Electrically Erasable PROM) as data memory. EEPROM, unlike static RAM, can retain its contents when the power is turned off.
CHAPTER 5 EEPROM 81 User’ s Manual U10676EJ3V0UM 5.3 EEPROM Write Control Register (EWC) The EEPROM write control register (EWC) is an 8-bit register used to control manipulation of EEPROM.
CHAPTER 5 EEPROM 82 User ’ s Manual U10676EJ3V0UM Cautions 1. The write time depends on the system clock oscillation frequency. 2. Set EWTC4-EWTC6 so that the write time is as follows. With µ PD754144 ··· 18 × 2 8 /f CC (4.6 ms: f CC = 1.0 MHz) With µ PD754244 ··· 4.
CHAPTER 5 EEPROM 83 User ’ s Manual U10676EJ3V0UM 5.5 EEPROM Manipulation Method 5.5.1 EEPROM manipulation instructions Instructions that can be used to manipulate the EEPROM are shown below, divided into read instructions and write instructions.
CHAPTER 5 EEPROM 84 User ’ s Manual U10676EJ3V0UM 5.5.2 Read manipulation The following procedure is used to read EEPROM. EWST, ERE and EWE can be set simultaneously by an 8-bit memory manipulation instruction to EWC. <1> Check that the write status flag (EWST) is 0 (write enabled = writing is currently not being performed).
CHAPTER 5 EEPROM 85 User ’ s Manual U10676EJ3V0UM 5.5.3 Write manipulation Use the following procedure to write to EEPROM. Any instruction other than one related to EEPROM writing can be executed even during an EEPROM write operation. EWST, EWTC and EWE can be set simultaneously by an 8-bit memory manipulation instruction to EWC.
CHAPTER 5 EEPROM 86 User ’ s Manual U10676EJ3V0UM Example Set the write time to 18 × 2 8 /f X and after checking the EEPROM write status flag (EWST), write 8-bit data (0AH) at 08H of memory bank 4.
CHAPTER 5 EEPROM 87 User ’ s Manual U10676EJ3V0UM 5.6 Cautions on EEPROM Writing Cautions on EEPROM writing are shown below. Be sure to read these before writing to EEPROM. Cautions 1. Before writing, make sure that EWST is 0. While EEPROM is being written, if a write instruction is executed again, the instruction executed later is ignored.
88 User’ s Manual U10676EJ3V0UM CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 6.1 Digital I/O Ports The µ PD754244 uses memory mapped I/O, and all the I/O ports are mapped to the data memory space.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 89 User ’ s Manual U10676EJ3V0UM 6.1.1 Types, features, and configurations of digital I/O ports Table 6-1 shows the types of digital I/O ports. Figures 6-2 to 6-9 show the configuration of each port. Table 6-1.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 90 User ’ s Manual U10676EJ3V0UM Figure 6-2. P3n Configuration (n = 0 to 2) Input buffer MPX Output latch PM3n PTOn Output buffer Input buffer POGA bit 3 V DD Pull-up resistor P-ch P3n/PTOn Internal bus Figure 6-3.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 91 User ’ s Manual U10676EJ3V0UM Figure 6-4. P60 Configuration Input buffer MPX Output latch PM60 Output buffer POGA bit 6 V DD Pull-up resistor P-ch P60/AV REF AV REF Input buffer with hysteresis characteristics Internal bus Figure 6-5.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 92 User ’ s Manual U10676EJ3V0UM Figure 6-6. P62 Configuration Input buffer Output latch PM62 POGA bit 6 V DD Pull-up resistor P-ch P62/PTH00 PTH00 Internal bus MPX Output buffer Input buffer with hysteresis characteristics Figure 6-7.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 93 User’ s Manual U10676EJ3V0UM Figure 6-8. P7n Configuration (n = 0 to 3) One-shot pulse generator Key return reset V DD Pull-up resistor (mask option) P70/KR4 P71/KR5 P72/KR6 P73/KR7 Interrupt control Falling edge detector Internal bus Input buffer Input buffer with hysteresis characteristics Figure 6-9.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 94 User ’ s Manual U10676EJ3V0UM 6.1.2 Setting I/O mode The input or output mode of each I/O port is set by the corresponding port mode register as shown in Figure 6- 10. Ports 3 and 6 can be set to the input or output mode in 1-bit units by using port mode register group A (PMGA).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 95 User ’ s Manual U10676EJ3V0UM Figure 6-10. Format of Each Port Mode Register Specification 0 Input mode (output buffer off) 1 Output mode (output buffer on).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 96 User ’ s Manual U10676EJ3V0UM 6.1.3 Digital I/O port manipulation instruction Because all the I/O ports of the µ PD754244 are mapped to the data memory space, they can be manipulated by using data memory manipulation instructions.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 97 User ’ s Manual U10676EJ3V0UM Table 6-2. I/O Pin Manipulation Instructions PORT PORT3 PORT6 PORT7 PORT8 Instruction IN A, PORTn Note 1 IN XA, PORTn Note 1 .
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 98 User ’ s Manual U10676EJ3V0UM 6.1.4 Operation of digital I/O port The operations of each port and port pin when a data memory manipulation instruction is executed to manipulate a digital I/O port differ depending on whether the port is set to the input or output mode (refer to Table 6-3 ).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 99 User ’ s Manual U10676EJ3V0UM Table 6-3. Operation When I/O Port Is Manipulated Operation of Port and Pin Input mode Output mode SKT <1> Tests pin dat.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 100 User ’ s Manual U10676EJ3V0UM 6.1.5 Connecting pull-up resistor Each port pin of the µ PD754244 can be connected to a pull-up resistor. Some pins can be connected to a pull- up resistor via software and others can be connected by a mask option.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 101 User ’ s Manual U10676EJ3V0UM 6.1.6 I/O timing of digital I/O port Figure 6-12 shows the timing at which data is output to the output latch and the timing at which the pin data or the data of the output latch is loaded to the internal bus.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 102 User ’ s Manual U10676EJ3V0UM Figure 6-13. ON Timing of Internal Pull-up Resistor Connected via Software Instruction execution Pull-up resistor specificati.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 103 User ’ s Manual U10676EJ3V0UM 6.2 Clock Generator The clock generator supplies various clocks to the CPU and peripheral hardware units and controls the operation mode of the CPU. 6.2.1 Configuration of clock generator Figure 6-14 shows the configuration of the clock generator.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 104 User ’ s Manual U10676EJ3V0UM Figure 6-14. Block Diagram of Clock Generator (2/2) (b) µ PD754244 Crystal/Ceramic Oscillation X1 X2 System clock oscillator.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 105 User ’ s Manual U10676EJ3V0UM 6.2.2 Function and operation of clock generator The clock generator generates the following types of clocks and controls the operation mode of the CPU in the standby mode.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 106 User ’ s Manual U10676EJ3V0UM (1) Processor clock control register (PCC) PCC is a 4-bit register that selects the CPU clock Φ with the lower 2 bits and controls the CPU operation mode with the higher 2 bits (refer to Figure 6-15 ).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 107 User ’ s Manual U10676EJ3V0UM Figure 6-15. Format of Processor Clock Control Register PCC3 3210 FB3H Address PCC Symbol PCC2 PCC1 PCC0 CPU operating mode c.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 108 User ’ s Manual U10676EJ3V0UM X1 X2 V SS Crystal or ceramic resonator PD754244 µ X1 X2 External clock PD754244 µ (2) System clock oscillator (a) µ PD754144 (RC oscillation) The system clock oscillator oscillates by means of a resistor (R) and capacitor (C) connected to the CL1 and CL2 pins.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 109 User ’ s Manual U10676EJ3V0UM Cautions 1. The X2 pin of the µ PD754244 is internally pulled up to V DD by a resistor of 50 k Ω (typ.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 110 User ’ s Manual U10676EJ3V0UM Figure 6-18. Example of Incorrect Resonator Connection (2/3) (b) Crossed signal line µ PD754144 CL1 CL2 V SS PORTn (n = 3, 6.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 111 User ’ s Manual U10676EJ3V0UM Figure 6-18. Example of Incorrect Resonator Connection (3/3) (d) Current flowing through power line of oscillator (potential .
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 112 User’ s Manual U10676EJ3V0UM 6.2.3 Setting CPU clock (1) Time required to switch CPU clock The CPU clock can be switched by using the lower 2 bits of PCC.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 113 User’ s Manual U10676EJ3V0UM Figure 6-19. CPU Clock Switching Example <1> Wait time Note 1 to secure the oscillation stabilization time in response to RESET signal generation. <2> The CPU starts operating at the lowest system clock speed Note 2 .
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 114 User ’ s Manual U10676EJ3V0UM 6.3 Basic Interval Timer/Watchdog Timer The µ PD754244 has an 8-bit basic interval timer/watchdog timer that has the following functions.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 115 User ’ s Manual U10676EJ3V0UM 6.3.2 Basic interval timer mode register (BTM) BTM is a 4-bit register that controls the operation of the basic interval timer (BT). This register is set by a 4-bit memory manipulation instruction.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 116 User ’ s Manual U10676EJ3V0UM Figure 6-21. Format of Basic Interval Timer Mode Register Note In the µ PD754244 only, wait time is selectable when standby mode is released. In the µ PD754144, wait time is always fixed to 2 9 /f CC (512 µ s at 1.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 117 User ’ s Manual U10676EJ3V0UM 6.3.3 Watchdog timer enable flag (WDTM) WDTM is a flag that enables assertion of the reset signal when an overflow occurs. This flag is set by a bit manipulation instruction. Once this flag has been set, it cannot be cleared by an instruction.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 118 User’ s Manual U10676EJ3V0UM 6.3.4 Operation as basic interval timer When WDTM is reset to “0”, the interrupt request flag (IRQBT) is set by the overflow of the basic interval timer (BT), and the basic interval timer/watchdog timer operates as the basic interval timer.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 119 User’ s Manual U10676EJ3V0UM Initial setting 6.3.5 Operation as watchdog timer The basic interval timer/watchdog timer operates as a watchdog timer that asserts the internal reset signal when an overflow occurs in the basic interval timer (BT), if WDTM is set to “1”.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 120 User ’ s Manual U10676EJ3V0UM Example To use the µ PD754244 as a watchdog timer with a time interval of 5.46 ms (at f X = 6.0 MHz). Note Divide the program into several modules, each of which is completed within the set time of BTM (5.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 121 User ’ s Manual U10676EJ3V0UM 6.3.6 Other functions The basic interval timer/watchdog timer has the following functions, regardless of the operations as the basic interval timer or watchdog timer.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 122 User’ s Manual U10676EJ3V0UM 6.4 Timer Counter The µ PD754244 incorporates a three-channel timer counter.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 123 User’ s Manual U10676EJ3V0UM Figure 6-23. Block Diagram of Timer Counter (Channel 0) Note Execution of the instruction Caution Be sure to clear bits 1 and 0 to 0 when setting data to TM0.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 124 User ’ s Manual U10676EJ3V0UM Figure 6-24. Block Diagram of Timer Counter (Channel 1) Note Execution of the instruction 8 Internal bus TM16 – TM15 TM14 T.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 125 User’ s Manual U10676EJ3V0UM Figure 6-25. Block Diagram of Timer Counter (Channel 2) Note Execution of the instruction Caution Be sure to clear bit 7 to 0 when setting data to TC2.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 126 User ’ s Manual U10676EJ3V0UM (1) Timer counter mode registers (TM0, TM1, TM2) A timer counter mode register (TMn) is an 8-bit register that controls the corresponding timer counter. Figures 6-26 to 6-28 show the formats of the various mode registers.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 127 User ’ s Manual U10676EJ3V0UM Figure 6-26. Format of Timer Counter Mode Register (Channel 0) Note Be sure to clear bits 0 and 1 to 0 when setting data to TM0.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 128 User ’ s Manual U10676EJ3V0UM Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (1/2) 765432 10 PD754244: f X = 6.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 129 User ’ s Manual U10676EJ3V0UM Figure 6-27. Format of Timer Counter Mode Register (Channel 1) (2/2) TM13 Clears counter and IRQT1 flag when "1" is written. Starts count operation if bit 2 is set to "1".
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 130 User ’ s Manual U10676EJ3V0UM Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (1/2) 765432 10 PD754244: f X = 6.0 MHz TM20 TM21 TM23 TM22 TM24 TM25 TM26 – Address TM2 F90H Symbol Count pulse (CP) select bit TM26 Count pulse (CP) TM25 0 f X /2 (3.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 131 User ’ s Manual U10676EJ3V0UM Figure 6-28. Format of Timer Counter Mode Register (Channel 2) (2/2) TM23 Clears counter and IRQT2 flag when "1" is written. Starts count operation if bit 2 is set to "1".
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 132 User ’ s Manual U10676EJ3V0UM (2) Timer counter output enable flags (TOE0, TOE1) Timer counter output enable flags TOE0 and TOE1 enable or disable output to the PTO0 and PTO1 pins in the timer out F/F (TOUT F/F) status.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 133 User ’ s Manual U10676EJ3V0UM (3) Timer counter control register (TC2) The timer counter control register (TC2) is an 8-bit register that controls the timer counter (channel 2). Figure 6-30 shows the format of this register.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 134 User’ s Manual U10676EJ3V0UM 6.4.2 Operation in 8-bit timer counter mode In this mode, the timer counter is used as an 8-bit timer counter. In this case, the timer counter operates as an 8-bit programmable interval timer or counter.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 135 User ’ s Manual U10676EJ3V0UM Figure 6-31. Setting of Timer Counter Mode Register (1/3) (a) Timer counter (channel 0) 765432 10 Count pulse (CP) select bit.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 136 User ’ s Manual U10676EJ3V0UM Figure 6-31. Setting of Timer Counter Mode Register (2/3) (b) Timer counter (channel 1) 765432 10 TM10 TM11 TM13 TM12 TM14 TM15 TM16 – Address TM1 FA8H Symbol TM13 Clears counter and IRQT1 flag when "1" is written.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 137 User ’ s Manual U10676EJ3V0UM Figure 6-31. Setting of Timer Counter Mode Register (3/3) (c) Timer counter (channel 2) 765432 10 TM20 TM21 TM23 TM22 TM24 TM25 TM26 – Address TM2 F90H Symbol TM23 Clears counter and IRQT2 flag when "1" is written.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 138 User ’ s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the 8-bit timer counter mode, set TC2 as shown in Figure 6-32 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register ).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 139 User ’ s Manual U10676EJ3V0UM [Timer set time] (cycle) is calculated by dividing [contents of modulo register + 1] by [count pulse (CP) frequency] selected by the mode register.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 140 User ’ s Manual U10676EJ3V0UM Table 6-7. Resolution and Longest Set Time (8-Bit Timer Counter Mode) (2/3) (TM10 = 0, TM11 = 0, TM20 = 0, TM21 = 0) 8-bit timer counter (channel 2) Mode Register 8-bit Timer Counter (Channel 2) TM26 TM25 TM24 Resolution Longest set time 0 1 0 333 ns 85.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 141 User ’ s Manual U10676EJ3V0UM Table 6-7. Resolution and Longest Set Time (8-Bit Timer Counter Mode) (3/3) (TM10 = 0, TM11 = 0, TM20 = 0, TM21 = 0) (c) µ PD754144: at 1.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 142 User ’ s Manual U10676EJ3V0UM (3) Timer counter operation (8-bit) The timer counter operates as follows. Figure 6-34 shows the configuration when the timer counter operates.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 143 User ’ s Manual U10676EJ3V0UM Figure 6-34. Configuration When Timer Counter Operates MPX Internal clock Timer counter modulo register (TMODn) Comparator Timer counter count register (Tn) CP TOUT F/F PTOn Coinci- dence Clear INTTn (lRQTn set signal) Figure 6-35.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 144 User ’ s Manual U10676EJ3V0UM (4) Application of 8-bit timer counter mode As an interval timer that generates an interrupt at 50 ms intervals Note • Set the higher 4 bits of the timer counter mode register (TMn) to 0100B, and select 62.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 145 User ’ s Manual U10676EJ3V0UM 6.4.3 Operation in PWM pulse generator mode (PWM mode) In this mode, the timer counter (channel 2) is used as a PWM pulse generator. The timer counter operates as an 8-bit PWM pulse generator.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 146 User’ s Manual U10676EJ3V0UM Figure 6-36. Setting of Timer Counter Mode Register 765432 10 TM20 TM21 TM23 TM22 TM24 TM25 TM26 – Address TM2 F90H Symbol TM23 Clears counter and IRQT2 flag when "1" is written.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 147 User ’ s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the PWM mode, set TC2 as shown in Figure 6-37 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register) .
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 148 User ’ s Manual U10676EJ3V0UM (2) PWM pulse generator operation The timer counter (channel 2) in PWM pulse generator mode has two registers, a high-level period setting timer counter modulo register (TMOD2H) and a low-level period setting timer counter modulo register (TMOD2).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 149 User ’ s Manual U10676EJ3V0UM Figure 6-38. PWM Pulse Generator Operating Configuration Note This is the IRQT2 set signal.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 150 User ’ s Manual U10676EJ3V0UM . . (3) Application of PWM mode To output a pulse with a frequency of 38.0 kHz (cycle of 26.3 µ s) and a duty factor of 1/3 to the PTO2 pin Note • Set the higher 4 bits of the timer counter mode register (TM2) to 0011B and select 61.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 151 User’ s Manual U10676EJ3V0UM 6.4.4 Operation in 16-bit timer counter mode In this mode, two timer counter channels, 1 and 2, are used in combination to implement 16-bit programmable interval timer or event timer operation.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 152 User’ s Manual U10676EJ3V0UM Figure 6-40. Setting of Timer Counter Mode Registers TM20 TM21 TM23 TM22 TM24 TM25 TM26 – TM2 F90H TM23 Clears counter and IRQTn flag when "1" is written. Starts count operation if bit 2 is set to "1".
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 153 User ’ s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the 16-bit timer counter mode, set TC2 as shown in Figure 6-41 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register ).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 154 User’ s Manual U10676EJ3V0UM (2) Time setting of timer counter [Timer set time] (cycle) is calculated by dividing [contents of modulo register + 1] by [count pulse (CP) frequency] selected by the mode register.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 155 User ’ s Manual U10676EJ3V0UM Table 6-8. Resolution and Longest Set Time (16-Bit Timer Counter Mode) (2/2) (TM10 = 0, TM11 = 1, TM20 = 0, TM21 = 1) (c) µ PD754244: at 4.19 MHz Mode Register 16-Bit Timer Counter TM26 TM25 TM24 Resolution Longest Set Time 0 1 0 477 ns 31.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 156 User’ s Manual U10676EJ3V0UM (3) Timer counter operation (at 16-bit) The timer counter operates as follows.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 157 User’ s Manual U10676EJ3V0UM Figure 6-42. Configuration When Timer Counter Operates Other internal clock is ignored MPX Timer counter modulo register (TMOD.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 158 User ’ s Manual U10676EJ3V0UM Figure 6-43. Timing of Count Operation Remark m: Set value of timer counter module register (TMOD1) n: Set value of timer cou.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 159 User ’ s Manual U10676EJ3V0UM (4) Application of 16-bit timer counter mode As an interval timer that generates an interrupt at 5-second intervals Note • Set the higher 4 bits of the mode register (TM1) to 0010B, and select the overflow of timer counter count register (T2).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 160 User ’ s Manual U10676EJ3V0UM 6.4.5 Operation in carrier generator mode (CG mode) In the PWM mode, timer counter channels 1 and 2 operate in combination to implement an 8-bit carrier generator operation. When using CG mode, use it in combination with channel 1 and channel 2 of the timer counter.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 161 User ’ s Manual U10676EJ3V0UM Figure 6-44. Setting of Timer Counter Mode Register (n = 1, 2) TM20 TM21 TM23 TM22 TM24 TM25 TM26 – TM2 F90H TMn3 Clears counter and IRQTn flag when "1" is written.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 162 User ’ s Manual U10676EJ3V0UM (b) Timer counter control register (TC2) In the CG mode, set the timer counter output enable flag (TOE1) and TC2 as shown in Figure 6-45 (for the format of TC2, refer to Figure 6-30 Format of Timer Counter Control Register ).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 163 User ’ s Manual U10676EJ3V0UM (2) Carrier generator operation The carrier generator operation is performed as follows. Figure 6-47 shows the configuration of the timer counter in the carrier generator mode.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 164 User ’ s Manual U10676EJ3V0UM <4> The operations <2> and <3> are repeated. <5> The no return zero data is reloaded from NRZB to NRZ when timer counter channel 1 generates an interrupt.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 165 User ’ s Manual U10676EJ3V0UM Figure 6-47. Configuration in Carrier Generator Mode Other internal clock is ignored MPX Timer counter modulo register (TMOD1.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 166 User ’ s Manual U10676EJ3V0UM Figure 6-48. Carrier Generator Operation Timing <1> Timer (channel 2) operation and carrier clock (Modulo register H (T.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 167 User ’ s Manual U10676EJ3V0UM Remark If a timer (channel 1) interrupt is generated when the PTO2 pin is low and the carrier clock is high (NRZ = 0, carrier clock = high level), the carrier is output to the PTO2 pin from the pulse after the carrier clock.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 168 User ’ s Manual U10676EJ3V0UM (3) Application of CG mode To use the timer counter as a carrier generator for remote controller signal transmission The examples shown below apply to the operation of the µ PD754244 at f X = 4.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 169 User ’ s Manual U10676EJ3V0UM <2> To output a leader code with a 9 ms period to output a carrier clock and a 4.5 ms period to output a low level (Refer to the figure below.) • Set the higher 4 bits of the timer counter mode register (TM1) to 0110B and select 15.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 170 User ’ s Manual U10676EJ3V0UM <3> To output a custom code with a 0.56 ms period to output a carrier clock when data is “ 1 ” , a 1.69 ms to output a low level, a 0.56 ms to output a carrier clock when data is “ 0 ” , and a 0.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 171 User ’ s Manual U10676EJ3V0UM <Program example> In the following example, it is assumed that the output latch of the PTO2 pin is cleared to “ 0 ” and that the output mode has been set.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 172 User ’ s Manual U10676EJ3V0UM BR SEND_1_F ; If data is 0, proceeds to transmission processing of next data with PTO2 pin outputting low level CALL !SEND_D_1 BR SEND_1_F SEND_END : ; Completes transmission of 16 bits of data ; <subroutine> GET_DATA: ; Searches data of BSB indicated by @L.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 173 User’ s Manual U10676EJ3V0UM 6.4.6 Notes on using timer counter (1) Error when timer starts After the timer has been started (bit 3 of TMn has been set to .
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 174 User ’ s Manual U10676EJ3V0UM (2) Note on starting timer Usually, count register Tn and interrupt request flag IRQTn are cleared when the timer is started (bit 3 of TMn is set to “ 1 ” ).
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 175 User ’ s Manual U10676EJ3V0UM (3) Notes on changing count pulse When it is specified to change the count pulse (CP) by rewriting the contents of the timer counter mode register (TMn), the specification becomes valid immediately after execution of the instruction that commands the specification.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 176 User ’ s Manual U10676EJ3V0UM (4) Operation after changing modulo register The contents of the timer counter modulo register (TMODn) and high-level period setting timer counter modulo register (TMOD2H) are changed as soon as an 8-bit data memory manipulation instruction has been executed.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 177 User ’ s Manual U10676EJ3V0UM (5) Note on application of carrier generator (on starting) When the carrier clock is generated, after the timer has been star.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 178 User ’ s Manual U10676EJ3V0UM (6) Notes on application of carrier generator (reload) To output a carrier to the PTO2 pin, the time required for the initial.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 179 User ’ s Manual U10676EJ3V0UM (7) Notes on application of carrier generator (restarting) If forced reloading is performed by directly rewriting the content.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 180 User’ s Manual U10676EJ3V0UM 6.5 Programmable Threshold Port (Analog Input Port) The µ PD754244 provides analog input pins (PTH00, PTH01) whose threshold voltage (reference voltage) is selectable within sixteen steps.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 181 User’ s Manual U10676EJ3V0UM Figure 6-49. Block Diagram of Programmable Threshold Port PTH00 PTH01 AV REF 1 2 R R R 1 2 R MPX V REF PTHM7 PTHM PTHM6 PTHM5 .
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 182 User’ s Manual U10676EJ3V0UM 0.5 16 15.5 16 6.5.2 Programmable threshold port mode (PTHM) register PTHM is an 8-bit register that controls the programmable threshold port operation, and it is set by an 8-bit memory manipulation instruction.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 183 User ’ s Manual U10676EJ3V0UM 6.5.3 Programmable threshold port application (1) An analog input voltage input to the PTH00 pin is A/D converted with 4-bit resolution. Figure 6-51. Application Example of Programmable Threshold Port PTH00 input voltage Reference voltage (V REF ) AV REF 7.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 184 User ’ s Manual U10676EJ3V0UM 6.6 Bit Sequential Buffer ... 16 Bits The bit sequential buffer (BSB) is a special data memory used for bit manipulation. It can manipulate bits by sequentially changing the address and bit specification.
CHAPTER 6 PERIPHERAL HARDWARE FUNCTION 185 User ’ s Manual U10676EJ3V0UM Example For serial output of the 16-bit data of BUFF1, 2 from bit 0 of port 3 CLR1 MBE MOV XA, BUFF1 MOV BSB0, XA ; Sets BSB0.
186 User’ s Manual U10676EJ3V0UM CHAPTER 7 INTERRUPT AND TEST FUNCTIONS The µ PD754244 has six vectored interrupt sources and one test input that can be used for various applications. The interrupt controller of the µ PD754244 has unique features and can service interrupts at extremely high speed.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 187 User’ s Manual U10676EJ3V0UM Figure 7-1. Block Diagram of Interrupt Controller Notes 1. Noise eliminator (Standby release is disable when noise eliminator is selected.) 2. Does not have the INT2 pin. The interrupt request flag (IRQ2) is set at the KRn pin falling edge when IM20 = 1 and IM21 = 0.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 188 User ’ s Manual U10676EJ3V0UM 7.2 Types of Interrupt Sources and Vector Table The µ PD754244 has the following six interrupt sources and nesting of interrupts can be controlled by software.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 189 User ’ s Manual U10676EJ3V0UM Figure 7-2. Interrupt Vector Table MBE MBE MBE MBE MBE Address 0002H 0004H 0006H 0008H 000AH 000CH 000EH RBE RBE RBE RBE RBE .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 190 User’ s Manual U10676EJ3V0UM 7.3 Hardware Controlling Interrupt Function (1) Interrupt request flag and interrupt enable flag The µ PD754244 has the following six interrupt request flags (IRQ ××× ) corresponding to the respective interrupt sources.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 191 User ’ s Manual U10676EJ3V0UM Table 7-2. Signals Setting Interrupt Request Flags Interrupt Request Flag Signal Setting Interrupt Request Flag Interrupt Enable Flag Set by reference time interval signal from basic interval timer watchdog timer Set by detection of edge of INT0/P61 pin input signal.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 192 User ’ s Manual U10676EJ3V0UM Figure 7-3. Interrupt Priority Select Register IPS3 IPS2 IPS1 IPS0 32 1 0 IPS Symbol FB2H Address 00 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 1 0 1 0 1 0 1 No interrupts are handled as higher-priority interrupts.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 193 User ’ s Manual U10676EJ3V0UM (3) Hardware of INT0 (a) Figure 7-4 shows the configuration of INT0, which is an external interrupt input that can be detected at the rising or falling edge depending on the specification.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 194 User ’ s Manual U10676EJ3V0UM Figure 7-4. Configuration of INT0 Internal bus 4 IM0 Noise eliminator INT0/P61 Selector Selector Φ f X /64 IM03 Edge detector INT0 (IRQ0 set signal) IM00, IM01 IM02 Specifies edge to be detected.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 195 User’ s Manual U10676EJ3V0UM Figure 7-6. Format of INT0 Edge Detection Mode Register (IM0) 3210 IM00 IM01 IM02 IM03 Address IM0 FB4H Symbol IM01 Specifies .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 196 User ’ s Manual U10676EJ3V0UM (4) Interrupt status flag The interrupt status flags (IST0 and IST1) indicate the status of the processing currently being executed by the CPU and are included in PSW.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 197 User’ s Manual U10676EJ3V0UM 7.4 Interrupt Sequence When an interrupt occurs, it is processed according to the procedure illustrated below.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 198 User ’ s Manual U10676EJ3V0UM 7.5 Nesting Control of Interrupts The µ PD754244 can nest interrupts by the following two methods. (1) Nesting with interrupt having high priority specified This method is the standard nesting method of the µ PD754244.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 199 User ’ s Manual U10676EJ3V0UM (2) Nesting by changing interrupt status flags Nesting can be implemented if the interrupt status flags are changed by program. In other words, nesting is enabled when IST1 and IST0 are cleared to “ 0, 0 ” by an interrupt servicing program, and status 0 is set.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 200 User ’ s Manual U10676EJ3V0UM 7.6 Servicing of Interrupts Sharing Vector Address Because interrupt sources INTT1 and INTT2 share vector tables, you should select one or both of the interrupt sources in the following way.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 201 User ’ s Manual U10676EJ3V0UM Examples 1. To use both INTT1 and INTT2 as having higher priority, and give priority to INTT2 DI SKTCLR IRQT2 ; IRQT2=1? BR VSUBBT EI RETI : VSUBBT: CLR1 IRQT1 EI RETI 2.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 202 User’ s Manual U10676EJ3V0UM 7.7 Machine Cycles Until Interrupt Servicing The number of machine cycles required from when an interrupt request flag (IRQxxx) has been set until the interrupt routine is executed is as follows.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 203 User ’ s Manual U10676EJ3V0UM (2) If IRQxxx is set while instruction other than (1) is executed (a) If IRQxxx is set at the last machine cycle of the instr.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 204 User ’ s Manual U10676EJ3V0UM 7.8 Effective Usage of Interrupts Use the interrupt function effectively as follows. (1) Use different register banks for the normal routine and interrupt routine. The normal routine uses register banks 2 and 3 with RBE = 1 and RBS = 2.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 205 User ’ s Manual U10676EJ3V0UM (1) Enabling or disabling interrupt Reset . . . <1> EI IE0 EI IET1 <2> EI .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 206 User ’ s Manual U10676EJ3V0UM (2) Example of using INTBT and INT0 (falling edge active): not nested (all interrupts have higher priority) SEL <1> Reset INT0 <4> RB2 MOV MOV CLR1 <2> A, #1 IM0, A IRQ0 EI EI EI EI .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 207 User ’ s Manual U10676EJ3V0UM (3) Nesting of interrupts with higher priority (INTBT has higher priority and INTT0 and INTT2 have lower priority) <1> Reset INTT0 <2> SEL EI EI EI MOV MOV . . . . .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 208 User ’ s Manual U10676EJ3V0UM (4) Executing pending interrupt - interrupt input while interrupts are disabled - Reset EI IE0 . . . . . . . . . . . . EI . . . . . . . . . . . . . . . . . . . . EI IET0 . . . .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 209 User ’ s Manual U10676EJ3V0UM (5) Executing pending interrupt - two interrupts with lower priority occur simultaneously - Reset EI IET0 EI IE0 EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 210 User’ s Manual U10676EJ3V0UM (6) Executing pending interrupt - interrupt occurs during interrupt service (INTBT has higher priority and INTT0 and INTT2 have lower priority) - Reset EI IEBT EI IET0 EI IET2 MOV A, #9 MOV IPS, A .
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 211 User ’ s Manual U10676EJ3V0UM (7) Enabling nesting of two interrupts - INTT0 and INT0 are nested doubly and INTBT and INTT2 are nested singly - Reset INTBT.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 212 User’ s Manual U10676EJ3V0UM 7.10 Test Function 7.10.1 Types of test sources The µ PD754244 has a test source, INT2. INT2 is an edge-detection testable input. Table 7-5. Types of Test Sources Test Source Internal/External INT2 (detects falling edge of input to KR4 to KR7 pins) External 7.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 213 User ’ s Manual U10676EJ3V0UM Figure 7-10. Block Diagram of KR4 to KR7 KR7/P73 KR6/P72 KR5/P71 KR4/P70 Nothing is assigned (in reset mode) Key return reset.
CHAPTER 7 INTERRUPT AND TEST FUNCTIONS 214 User ’ s Manual U10676EJ3V0UM Figure 7-11. Format of INT2 Edge Detection Mode Register (IM2) 3210 IM20 IM21 0 0 Address IM2 FB6H Symbol IM21 INT2 test source IM20 0 Assigned nothing 0 01 Other Test input pin – KR4-KR7 Inputs falling edge of any of KR4/P70 to KR7/P73 pin Setting prohibited Cautions 1.
215 User’ s Manual U10676EJ3V0UM CHAPTER 8 STANDBY FUNCTION The µ PD754244 possesses a standby function that reduces the power consumption of the system. This standby function can be implemented in the following two modes. • STOP mode • HALT mode The functions of the STOP and HALT modes are as follows.
CHAPTER 8 STANDBY FUNCTION 216 User’ s Manual U10676EJ3V0UM 8.1 Settings and Operating Statuses of Standby Mode Table 8-1. Operating Statuses in Standby Mode STOP Mode HALT Mode Instruction to be se.
CHAPTER 8 STANDBY FUNCTION 217 User’ s Manual U10676EJ3V0UM The STOP mode is set by the STOP instruction, and the HALT mode is set by the HALT instruction (the STOP and HALT instructions respectively set bits 3 and 2 of PCC). Be sure to write a NOP instruction after the STOP and HALT instructions.
CHAPTER 8 STANDBY FUNCTION 218 User’ s Manual U10676EJ3V0UM 8.2 Releasing Standby Mode Both the STOP and HALT modes can be released when an interrupt request signal occurs that is enabled by the corresponding interrupt enable flag, or when the RESET signal is asserted.
CHAPTER 8 STANDBY FUNCTION 219 User ’ s Manual U10676EJ3V0UM Figure 8-1. Releasing Standby Mode (2/2) (c) Releasing HALT mode by RESET signal RESET signal Clock HALT instruction Operation mode HALT .
CHAPTER 8 STANDBY FUNCTION 220 User’ s Manual U10676EJ3V0UM <3> Clear again the IRQ used to release STOP mode to enter STOP mode. In this STOP mode, IRQ of the selected interrupt is set and HALT mode is entered. Then, after a wait time, the system returns to the normal operating mode.
CHAPTER 8 STANDBY FUNCTION 221 User ’ s Manual U10676EJ3V0UM Figure 8-3. STOP Mode Release by Key Return Reset or RESET Input IE ×××← 0 STOP NOP Key return reset or RESET input The differences between release by a key return reset and release by RESET input are as follows.
CHAPTER 8 STANDBY FUNCTION 222 User ’ s Manual U10676EJ3V0UM 8.3 Operation After Release of Standby Mode (1) When the standby mode has been released by the RESET signal, the normal reset operation is performed.
CHAPTER 8 STANDBY FUNCTION 223 User ’ s Manual U10676EJ3V0UM (1) Application example of STOP mode (when using the µ PD754244 at f X = 6.0 MHz) <When using the STOP mode under the following conditions> • The STOP mode is set at the falling edge of INT0 and released at the rising edge.
CHAPTER 8 STANDBY FUNCTION 224 User ’ s Manual U10676EJ3V0UM <Program example> (INT0 servicing program, MBE = 0) VSUB0: SKT PORT6.1 ; P61 = 1? BR PDOWN ; Power down SET1 BTM.3 ; Power on WAIT: SKT IRQBT ; Waits for 21.8 ms BR WAIT SKT PORT6.1 ; Checks chattering BR PDOWN MOV A, #0011B MOV PCC, A ; Sets high-speed mode MOV XA.
CHAPTER 8 STANDBY FUNCTION 225 User ’ s Manual U10676EJ3V0UM (2) Application example of HALT mode (when using the µ PD754244 at f X = 6.0 MHz) <To perform intermittent operation under the following conditions> • The standby mode is set at the falling edge of INT0 and released at the rising edge.
CHAPTER 8 STANDBY FUNCTION 226 User ’ s Manual U10676EJ3V0UM <Program example> BTAND4: SKTCLR IRQ0 ; INT0 = 1? BR VSUBBT ; N O SKT PORT6.1 ; P61 = 1? BR PDOWN ; Power down SET1 BTM.3 ; Starts BT WAIT: SKT IRQBT ; Waits for 175 ms BR WAIT SKT PORT6.
227 User’ s Manual U10676EJ3V0UM CHAPTER 9 RESET FUNCTION 9.1 Configuration and Operation of Reset Function Three types of reset signals are used: the external reset signal (RESET), a reset signal from the basic interval timer/watchdog timer, and a key return reset.
CHAPTER 9 RESET FUNCTION 228 User’ s Manual U10676EJ3V0UM Figure 9-2. Reset Operation by RESET Signal RESET signal HALT mode Operation mode or standby mode Internal reset operation Operation mode Wait Note Note µ PD754244: The following two times can be selected by the mask option.
CHAPTER 9 RESET FUNCTION 229 User ’ s Manual U10676EJ3V0UM When RESET Signal Asserted in Standby Mode When RESET Signal Asserted During Operation Hardware Basic inter- val timer/ watchdog timer Timer counter (T0) Timer counter (T1) Table 9-1. Status of Each Hardware Unit After Reset (1/3) Notes 1.
CHAPTER 9 RESET FUNCTION 230 User ’ s Manual U10676EJ3V0UM Counter (T2) Modulo register (TMOD2) High-level period setting modulo register (TMOD2H) Mode register (TM2) TOE2, TOUT F/F REMC, NRZ, NRZB .
CHAPTER 9 RESET FUNCTION 231 User ’ s Manual U10676EJ3V0UM 9.2 Watchdog Flag (WDF), Key Return Flag (KRF) WDF and KRF are mapped to bit 2 and 3 of address FC6H respectively. The contents of WDF and KRF are undefined initially, but they are initialized to “ 0 ” by external RESET signal generation.
CHAPTER 9 RESET FUNCTION 232 User ’ s Manual U10676EJ3V0UM Figure 9-4. KRF Operation in Generating Each Signal External RESET KRF Operation mode Operation mode HALT mode Operation mode Internal rese.
233 User’ s Manual U10676EJ3V0UM CHAPTER 10 MASK OPTIONS The µ PD754144 and 754244 have the following mask options. Table 10-1. Selection of Mask Options Item µ PD754144 µ PD754244 P70/KR4 to P73.
234 User’ s Manual U10676EJ3V0UM CHAPTER 11 INSTRUCTION SET The instruction set of the µ PD754244 is based on the instruction set of the 75X Series and therefore maintains compatibility with the 75X Series, but with the following improved features.
CHAPTER 11 INSTRUCTION SET 235 User’ s Manual U10676EJ3V0UM 11.1.2 Bit manipulation instruction The µ PD754244 has reinforced bit test, bit transfer, and bit Boolean (AND, OR, and XOR) instructions, in addition to the ordinary bit manipulation (set and clear) instructions.
CHAPTER 11 INSTRUCTION SET 236 User’ s Manual U10676EJ3V0UM 11.1.4 Base number adjustment instruction Some applications require that the result of addition or subtraction of 4-bit data (which is carried out in binary) be converted into a decimal number or into a number with a base of 6, such as time.
CHAPTER 11 INSTRUCTION SET 237 User’ s Manual U10676EJ3V0UM 11.1.5 Skip instruction and number of machine cycles required for skipping The instruction set of the µ PD754244 configures a program where instructions may be or may not be skipped if a given condition is satisfied.
CHAPTER 11 INSTRUCTION SET 238 User’ s Manual U10676EJ3V0UM Representation Description reg X, A, B, C, D, E, H, L reg1 X, B, C, D, E, H, L rp XA, BC, DE, HL rp1 BC, DE, HL rp2 BC, DE rp' XA, BC.
CHAPTER 11 INSTRUCTION SET 239 User’ s Manual U10676EJ3V0UM (2) Conventions for explanation of operation A: A register; 4-bit accumulator B: B register C: C register D: D register E: E register H: H.
CHAPTER 11 INSTRUCTION SET 240 User’ s Manual U10676EJ3V0UM *1 MB = MBE MBS (MBS = 0, 4, 15) *2 MB = 0 *3 MBE = 0: MB = 0 (000H to 07FH) MB = 15 (F80H to FFFH) MBE = 1: MB = MBS (MBS = 0, 4, 15) *4 .
CHAPTER 11 INSTRUCTION SET 241 User’ s Manual U10676EJ3V0UM (4) Explanation of machine cycle field S indicates the number of machine cycles required for an instruction with skip to execute the skip operation. The value of S varies as follows. • When skip is executed .
CHAPTER 11 INSTRUCTION SET 242 User’ s Manual U10676EJ3V0UM Transfer MOV A, #n4 1 1 A ← n4 String effect A reg1, #n4 2 2 reg1 ← n4 XA, #n8 2 2 XA ← n8 String effect A HL, #n8 2 2 HL ← n8 Str.
CHAPTER 11 INSTRUCTION SET 243 User’ s Manual U10676EJ3V0UM Machine Cycle Instructions Mnemonic Operand Bytes Operation Skip Condition Addressing Area MOVT XA, @PCDE 1 3 XA ← (PC 11-8 + DE) ROM XA, @PCXA 1 3 XA ← (PC 11-8 + XA) ROM XA, @BCDE 1 3 XA ← (BCDE) ROM Note *6 XA, @BCXA 1 3 XA ← (BCXA) ROM Note *6 Bit transfer MOV1 CY, fmem.
CHAPTER 11 INSTRUCTION SET 244 User’ s Manual U10676EJ3V0UM RORC A 1 1 CY ← A 0 , A 3 ← CY, A n–1 ← A n NOT A2 2 A ← A INCS reg 1 1 + S reg ← reg + 1 reg = 0 rp1 1 1 + S rp1 ← rp1 + 1 .
CHAPTER 11 INSTRUCTION SET 245 User’ s Manual U10676EJ3V0UM Machine Cycle Instructions Mnemonic Operand Bytes Operation Skip Condition Addressing Area AND1 CY, fmem.bit 2 2 CY ← CY (fmem.bit) *4 CY, pmem.@L 2 2 CY ← CY (pmem 7-2 + L 3-2 .bit(L 1-0 )) *5 CY, @H + mem.
CHAPTER 11 INSTRUCTION SET 246 User’ s Manual U10676EJ3V0UM Subrou- tine/stack control Machine Cycle Instructions Mnemonic Operand Bytes Operation Skip Condition Addressing Area CALLA Note !addr1 3 .
CHAPTER 11 INSTRUCTION SET 247 User’ s Manual U10676EJ3V0UM Machine Cycle Instructions Mnemonic Operand Bytes Operation Skip Condition Addressing Area Subrou- tine/stack control Interrupt control PU.
CHAPTER 11 INSTRUCTION SET 248 User’ s Manual U10676EJ3V0UM 11.3 Opcode of Each Instruction (1) Description of symbol of opcode R 2 R 1 R 0 reg 000 A 001 X 010L 011 H 100 E 101 D 110 C 111 B reg reg.
CHAPTER 11 INSTRUCTION SET 249 User’ s Manual U10676EJ3V0UM (2) Opcode for bit manipulation addressing *1 in the operand field indicates the following three types. • fmem.bit • pmem.@L • @H+mem.bit The second byte *2 of the opcode corresponding to the above addressing is as follows.
CHAPTER 11 INSTRUCTION SET 250 User’ s Manual U10676EJ3V0UM Instruction Mnemonic Operand Opcode B 1 B 2 B 3 Transfer MOV A , # n 4 0111I 3 I 2 I 1 I 0 reg1, #n4 10011010 I 3 I 2 I 1 I 0 1R 2 R 1 R 0.
CHAPTER 11 INSTRUCTION SET 251 User’ s Manual U10676EJ3V0UM Opcode B 1 B 2 B 3 Operation ADDS A , # n 4 0110I 3 I 2 I 1 I 0 XA, #n8 10111001I 7 I 6 I 5 I 4 I 3 I 2 I 1 I 0 A , @ H L 11010010 XA, rp&.
CHAPTER 11 INSTRUCTION SET 252 User’ s Manual U10676EJ3V0UM Opcode B 1 B 2 B 3 INCS r e g 11000 R 2 R 1 R 0 r p 1 10001 P 2 P 1 P 0 @ H L 1001100100000010 m e m 10000010 D 7 D 6 D 5 D 4 D 3 D 2 D 1 .
CHAPTER 11 INSTRUCTION SET 253 User’ s Manual U10676EJ3V0UM Opcode B 1 B 2 B 3 Branch BR !addr 1010101100 addr $addr1 0000 A 3 A 2 A 1 A 0 1111 S 3 S 2 S 1 S 0 PCDE 1001100100000100 PCXA 10011001000.
CHAPTER 11 INSTRUCTION SET 254 User’ s Manual U10676EJ3V0UM 11.4 Instruction Function and Application This section describes the functions and applications of the respective instructions. The instructions that can be used and the functions of the instructions differ between the MkI and MkII modes of the µ PD754144, and 754244.
CHAPTER 11 INSTRUCTION SET 255 User’ s Manual U10676EJ3V0UM 11.4.1 Transfer instructions MO V A, #n4 Function: A ← n4 n4 = I 3-0 : 0-FH Transfers 4-bit immediate data n4 to the A register (4-bit accumulator).
CHAPTER 11 INSTRUCTION SET 256 User’ s Manual U10676EJ3V0UM MO V A, @HL Function: A ← (HL) Transfers the contents of the data memory content addressed by register pair HL is transferred to the A register.
CHAPTER 11 INSTRUCTION SET 257 User’ s Manual U10676EJ3V0UM MO V XA, @HL Function: A ← (HL), X ← (HL+1) Transfers the contents of the data memory addressed by register pair HL to the A register, and the contents of the next memory address to the X register.
CHAPTER 11 INSTRUCTION SET 258 User’ s Manual U10676EJ3V0UM MO V mem, A Function: (mem) ← A mem = D 7-0 : 00H to FFH Transfers the contents of the A register to the data memory addressed by 8-bit immediate data mem.
CHAPTER 11 INSTRUCTION SET 259 User’ s Manual U10676EJ3V0UM XCH A, @HL Function: A ↔ (HL) Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL.
CHAPTER 11 INSTRUCTION SET 260 User’ s Manual U10676EJ3V0UM XCH XA, @HL Function: A ↔ (HL), X ↔ (HL+1) Exchanges the contents of the A register with the contents of the data memory addressed by register pair HL, and the contents of the X register with the contents of the next address.
CHAPTER 11 INSTRUCTION SET 261 User’ s Manual U10676EJ3V0UM 11.4.2 Table reference instructions MO V XA, @PCDE Function: XA ← ROM (PC 11-8 +DE) Transfers the lower 4 bits of the table data in the .
CHAPTER 11 INSTRUCTION SET 262 User’ s Manual U10676EJ3V0UM Caution The MOVT XA, @PCDE instruction usually references the table data in page where the instruction exists. If the instruction is at address ×× FFH, however, the table data in the next page is referenced instead of the table data in the page where the instruction exists.
CHAPTER 11 INSTRUCTION SET 263 User ’ s Manual U10676EJ3V0UM MO VT XA, @PCXA Function: XA ← ROM (PC 11-8 +XA) Transfers the lower 4 bits of the table data in the program memory addressed when the .
CHAPTER 11 INSTRUCTION SET 264 User ’ s Manual U10676EJ3V0UM MO VT XA, @BCXA Function: XA ← ROM (BCXA) Transfers the lower 4 bits of the table data (8-bit) in the program memory addressed by the B register and the contents of registers C, X, and A, to the A register, and the higher 4 bits to the X register.
CHAPTER 11 INSTRUCTION SET 265 User ’ s Manual U10676EJ3V0UM 11.4.3 Bit transfer instructions MO V1 CY , fmem.bit MO V1 CY , pmem.@L MO V1 CY , @H+mem.bit Function: CY ← (bit specified by operand) Transfers the contents of the data memory addressed in the bit manipulating addressing mode (fmem.
CHAPTER 11 INSTRUCTION SET 266 User’ s Manual U10676EJ3V0UM 11.4.4 Operation instructions ADDS A, #n4 Function: A ← A+n4; Skip if carry. n4 = l 3-0 : 0 to FH Adds 4-bit immediate data n4 to the contents of the A register. If a carry occurs as a result, the next instruction is skipped.
CHAPTER 11 INSTRUCTION SET 267 User’ s Manual U10676EJ3V0UM ADDC A, @HL Function: A, CY ← A+ (HL) +CY Adds the contents of the data memory addressed by register pair HL to the contents of the A register, including the carry flag. If a carry occurs as a result, the carry flag is set; if not, the carry flag is reset.
CHAPTER 11 INSTRUCTION SET 268 User’ s Manual U10676EJ3V0UM SUBS XA, rp’ Function: XA ← XA – rp’; Skip if borrow. Subtracts the contents of register pair rp’ (XA, HL, DE, BC, XA’, HL’, DE’, or BC’) from the contents of register pair XA, and sets the result to register pair XA.
CHAPTER 11 INSTRUCTION SET 269 User’ s Manual U10676EJ3V0UM SUBC rp’1, XA Function: rp’1, CY ← rp’1 – XA – CY Subtracts the contents of register pair XA from the contents of register pair rp’1 (HL, DE, BC, XA’, HL’, DE’, or BC’), including the carry flag, and sets the result to specified register pair rp’1.
CHAPTER 11 INSTRUCTION SET 270 User’ s Manual U10676EJ3V0UM OR A, #n4 Function: A ← A n4 n4 = l 3-0 : 0-FH ORs 4-bit immediate data n4 with the contents of the A register, and sets the result to the A register.
CHAPTER 11 INSTRUCTION SET 271 User’ s Manual U10676EJ3V0UM XOR A, @HL Function: A ← A (HL) Exclusive-ORs the contents of the data memory addressed by register pair HL with the contents of the A register, and sets the result to the A register.
CHAPTER 11 INSTRUCTION SET 272 User’ s Manual U10676EJ3V0UM 11.4.5 Accumulator manipulation instructions R ORC A Function: CY ← A 0 , A n-1 ← A n , A 3 ← CY (n = 1-3) Rotates the contents of the A register (4-bit accumulator) 1 bit to the left with the carry flag.
CHAPTER 11 INSTRUCTION SET 273 User ’ s Manual U10676EJ3V0UM 11.4.6 Increment/decrement instructions INCS reg Function: reg ← reg+1; Skip if reg = 0 Increments the contents of register reg (X, A, H, L, D, E, B, or C). If reg = 0 as a result, the next instruction is skipped.
CHAPTER 11 INSTRUCTION SET 274 User ’ s Manual U10676EJ3V0UM 11.4.7 Compare instructions SKE reg, #n4 Function: Skip if reg = n4 n4 = I 3-0 : 0-FH Skips the next instruction if the contents of register reg (X, A, H, L, D, E, B, or C) are equal to 4-bit immediate data n4.
CHAPTER 11 INSTRUCTION SET 275 User ’ s Manual U10676EJ3V0UM 11.4.8 Carry flag manipulation instructions SET1 CY Function: CY ← 1 Sets the carry flag. CLR1 CY Function: CY ← 0 Clears the carry flag. SKT CY Function: Skip if CY = 1 Skips the next instruction if the carry flag is 1.
CHAPTER 11 INSTRUCTION SET 276 User ’ s Manual U10676EJ3V0UM 11.4.9 Memory bit manipulation instructions SET1 mem.bit Function: (mem.bit) ← 1 mem = D 7-0 : 00H to FFH, bit = B 1-0 : 0-3 Sets the bit specified by 2-bit immediate data bit at the address specified by 8-bit immediate data mem.
CHAPTER 11 INSTRUCTION SET 277 User ’ s Manual U10676EJ3V0UM SKT fmem.bit SKT pmem.@L SKT @H+mem.bit Function: Skip if (bit specified by operand) = 1 Skips the next instruction if the bit of the data memory addressed in the bit manipulation addressing mode (fmem.
CHAPTER 11 INSTRUCTION SET 278 User ’ s Manual U10676EJ3V0UM AND1 CY , fmem.bit AND1 CY , pmem.@L AND1 CY , @H+mem.bit Function: CY ← CY (bit specified by operand) ANDs the content of the carry flag with the contents of the data memory addressed in the bit manipulation addressing mode (fmem.
CHAPTER 11 INSTRUCTION SET 279 User ’ s Manual U10676EJ3V0UM 11.4.10 Branch instructions BR addr Function: P C 11-0 ← addr addr = 0000H to 0FFFH Branches to an address specified by immediate data addr.
CHAPTER 11 INSTRUCTION SET 280 User’ s Manual U10676EJ3V0UM BR $addr1 Function: P C 11-0 ← addr1 addr1 = (PC–15) to (PC–1), (PC+2) to (PC+16) This is a relative branch instruction that has a branch range of (–15 to –1) and (+2 to +16) from the current address.
CHAPTER 11 INSTRUCTION SET 281 User ’ s Manual U10676EJ3V0UM BR PCDE Function: P C 11-0 ← PC 11-8 + DE PC 7-4 ← D, PC 3-0 ← E Branches to an address specified by the lower 8 bits of the program counter (PC 7-0 ) replaced with the contents of register pair DE.
CHAPTER 11 INSTRUCTION SET 282 User ’ s Manual U10676EJ3V0UM BR BCDE Function: P C 11-0 ← BCDE Example To branch to an address specified by the contents of the program counter replaced by the contents of registers B, C, D, and E However, the PC of the µ PD754244 is 12 bits.
CHAPTER 11 INSTRUCTION SET 283 User ’ s Manual U10676EJ3V0UM 11.4.11 Subroutine/stack control instructions CALLA !addr1 Function: (SP – 2) ← × , × , MBE, RBE, (SP – 3) ← PC 7-4 (SP – 4) .
CHAPTER 11 INSTRUCTION SET 284 User ’ s Manual U10676EJ3V0UM CALLF !faddr Function: [MkI mode] (SP – 1) ← PC 7-4 , (SP – 2) ← PC 3-0 (SP – 3) ← MBE, RBE, 0, 0 (SP – 4) ← PC 11-8 , SP.
CHAPTER 11 INSTRUCTION SET 285 User’ s Manual U10676EJ3V0UM RET Function: [MkI mode] PC 11-8 ← (SP), MBE, RBE, 0, 0 ← (SP+1) PC 3-0 ← (SP+2) PC 7-4 ← (SP+3), SP ← SP+4 [MkII mode] PC 11-8 .
CHAPTER 11 INSTRUCTION SET 286 User ’ s Manual U10676EJ3V0UM PUSH rp Function: (SP – 1) ← rp H , (SP – 2) ← rp L , SP ← SP – 2 Saves the contents of register pair rp (XA, HL, DE, or BC) to the data memory (stack) addressed by the stack pointer (SP), and then decrements the contents of the SP.
CHAPTER 11 INSTRUCTION SET 287 User ’ s Manual U10676EJ3V0UM 11.4.12 Interrupt control instructions EI Function: IME (IPS.3) ← 1 Sets the interrupt mask enable flag (bit 3 of the interrupt priority select register) to “ 1 ” to enable interrupts.
CHAPTER 11 INSTRUCTION SET 288 User’ s Manual U10676EJ3V0UM 11.4.13 Input/output instructions IN A, PORTn Function: A ← PORTn n = N 3-0 : 3, 6, 7, 8 Transfers the contents of a port specified by PORTn (n = 3, 6, 7, 8) to the A register. Caution When this instruction is executed, it is necessary that MBE = 0 or (MBE = 1, MBS = 15).
CHAPTER 11 INSTRUCTION SET 289 User’ s Manual U10676EJ3V0UM 11.4.14 CPU control instruction HAL T Function: PCC.2 ← 1 Sets the HALT mode (this instruction sets the bit 2 of the processor clock control register). Caution Make sure that a NOP instruction follows the HALT instruction.
CHAPTER 11 INSTRUCTION SET 290 User ’ s Manual U10676EJ3V0UM 11.4.15 Special instructions SEL RBn Function: RBS ← n n = N 1-0 : 0-3 Sets 2-bit immediate data n to the register bank select register (RBS). SEL MBn Function: MBS ← n n = N 3-0 : 0, 4, 15 Transfers 4-bit immediate data n to the memory bank select register (MBS).
CHAPTER 11 INSTRUCTION SET 291 User’ s Manual U10676EJ3V0UM References the 2-byte data at the program memory address specified by (taddr), (taddr+1) and executes it as an instruction. The area of the reference table consists of addresses 0020H to 007FH.
CHAPTER 11 INSTRUCTION SET 292 User ’ s Manual U10676EJ3V0UM Replaced by GETI ......... ......... ......... ......... Application example MOV HL, #00H MOV XA, #FFH CALL SUB1 BR SUB2 ORG 20H HL00: MO.
293 User’ s Manual U10676EJ3V0UM APPENDIX A DEVELOPMENT TOOLS The following development tools are available to support development of systems using the µ PD754244. With the 75XL Series, a relocatable assembler that can be used in common with any model in the series is used in combination with a device file dedicated to the model being used.
APPENDIX A DEVELOPMENT TOOLS 294 User’ s Manual U10676EJ3V0UM EV-9500GS-20 EV-9501GS-20 Debugging Tools In-circuit emulators (IE-75000-R and IE-75001-R) are available as the debugging tools for the µ PD754244. The following table shows the system configuration of the in-circuit emulators.
APPENDIX A DEVELOPMENT TOOLS 295 User’ s Manual U10676EJ3V0UM OS of IBM PC The following OSs are supported as the OS for IBM PCs. OS Version PC DOS TM Ver.5.02 to Ver.6.3 J6.1/V Note to J6.3/V Note MS-DOS Ver.5.0 to Ver.6.22 5.0/V Note to 6.2/V Note IBM DOS TM J5.
APPENDIX A DEVELOPMENT TOOLS 296 User’ s Manual U10676EJ3V0UM Development Tool Configuration In-circuit emulator IE-75000-R or IE-75001-R Emulation board IE-75300-R-EM Note 1 IE control program Host.
297 User’ s Manual U10676EJ3V0UM APPENDIX B ORDERING MASK ROM After your program has been developed, you can place an order for mask ROM using the following procedure. <1> Reservation for mask ROM ordering Inform NEC Electronics of when you intend to place an order for the mask ROM.
298 User’ s Manual U10676EJ3V0UM APPENDIX C INSTRUCTION INDEX C.1 Instruction Index (By Function) [Table reference instruction] MOVT XA, @PCDE ... 243, 261 MOVT XA, @PCXA ... 243, 263 MOVT XA, @BCDE ... 243, 263 MOVT XA, @BCXA ... 243, 264 [Bit transfer instruction] MOV1 CY, fmem.
APPENDIX C INSTRUCTION INDEX 299 User’ s Manual U10676EJ3V0UM AND A, @HL ... 243, 269 AND XA, rp' ... 243, 269 AND rp'1, XA ... 243, 269 OR A, #n4 ... 243, 270 OR A, @HL ... 243, 270 OR XA, rp' ... 243, 270 OR rp'1, XA ... 243, 270 XOR A, #n4 .
APPENDIX C INSTRUCTION INDEX 300 User’ s Manual U10676EJ3V0UM BR PCXA ... 245, 281 BR BCDE ... 245, 282 BR BCXA ... 245, 282 BRA !addr1 ... 245, 279 BRCB !caddr ... 245, 280 TBR addr ... 247, 282 [Subroutine/stack control instruction] CALLA !addr1 .
APPENDIX C INSTRUCTION INDEX 301 User’ s Manual U10676EJ3V0UM C.2 Instruction Index (Alphabetical Order) [A] ADDC A, @HL ... 243, 267 ADDC rp'1, XA ... 243, 267 ADDC XA, rp' ... 243, 267 ADDS A, #n4 ... 243, 266 ADDS A, @HL ... 243, 266 ADDS rp'1, XA .
APPENDIX C INSTRUCTION INDEX 302 User’ s Manual U10676EJ3V0UM MOV A, @rpa1 ... 242, 256 MOV HL, #n8 ... 242, 255 MOV mem, A ... 242, 258 MOV mem, XA ... 242, 258 MOV reg1, A ... 242, 258 MOV reg1, #n4 ... 242, 255 MOV rp'1, XA ... 242, 258 MOV rp2, #n8 .
APPENDIX C INSTRUCTION INDEX 303 User’ s Manual U10676EJ3V0UM SKT @H+mem.bit ... 244, 277 SKTCLR fmem.bit ... 244, 277 SKTCLR pmem.@L ... 244, 277 SKTCLR @H+mem.bit ... 244, 277 STOP ... 247, 289 SUBC A, @HL ... 243, 268 SUBC rp'1, XA ... 243, 268 SUBC XA, rp' .
304 User’ s Manual U10676EJ3V0UM APPENDIX D HARDWARE INDEX [B] BS ... 78 BSB0 to BSB3 ... 184 BT ... 114 BTM ... 115 [C] CY ... 74 [E] ERE ... 81 EWC ... 81 EWE ... 81 EWST ... 81 EWTC4 to EWTC6 ... 81 [I] IE0 ... 190 IE2 ... 212 IEBT ... 190 IEEE .
APPENDIX D HARDWARE INDEX 305 User’ s Manual U10676EJ3V0UM [S] SBS ... 61, 70 SK0 to SK2 ... 75 SP ... 70 [T] T0, T1 ... 54 T2 ... 53 TC2 ... 133, 138 TM0 ... 127 TM1 ... 128 TM2 ... 130 TMOD0, TMOD1 ... 54 TMOD2 ... 53 TMOD2H ... 52 TOE0, TOE1 ... 132 TOE2 .
306 User’ s Manual U10676EJ3V0UM APPENDIX E REVISION HISTORY The revision history is shown below. “Location” indicates the corresponding chapters in the preceding edition.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté NEC PD754244 c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du NEC PD754244 - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation NEC PD754244, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le NEC PD754244 va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le NEC PD754244, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du NEC PD754244.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le NEC PD754244. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei NEC PD754244 ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
