Manuel d'utilisation / d'entretien du produit MN102F85K du fabricant Lucent Technologies
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MICR OCOMPUTER MN102H MN102H75K/F75K/85K/F85K LSI User’ s Manual Pub .No .22385-011E.
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PanaXSerie s is a t rademark o f Matsushita Elect ric Industr ial Co., L td. The other corporat ion names, logotyp e and product names written in this book are trademark s or registe red trademarks of their corresp ondin g corp oratio ns.
Contents MN102H75 K/F75K LSI Use r Manual Panasonic Semiconductor Develo pment Company 3 Panas onic Contents About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Using This Manual.
Contents Panasonic Semicond uctor Dev elopment Com pany MN102H75 K/F75K LSI User Manual 4 Panas onic 4.5.1 Setting Up an Ev ent Counter Using T imer 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 4.5.2 Setting Up an Interv al T imer Using T imers 1 and 2 .
Contents MN102H75 K/F75K LSI Use r Manual Panasonic Semiconductor Develo pment Company 5 Panas onic 6.4.2 Single Channel/Single Co n version T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 6.4.3 Multiple Channel/Single Con v ersi on T iming .
Contents Panasonic Semicond uctor Dev elopment Com pany MN102H75 K/F75K LSI User Manual 6 Panas onic 7.13.3 Controlling Shutter ing Ef fects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 7.
Contents MN102H75 K/F75K LSI Use r Manual Panasonic Semiconductor Develo pment Company 7 Panas onic 11 I/O P or t s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 11.
Contents Panasonic Semicond uctor Dev elopment Com pany MN102H75 K/F75K LSI User Manual 8 Panas onic B.4.2 Circuit Requireme nts for the T arg et Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 B.4.3 Microcontroller Hardw are Used in Onb oard Serial Programming .
List of T able s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 9 Panas onic List of T ables 1-1 General Specif ications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Table s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 10 Panas onic 8-5 IR Remote Signal Recei ver Re gisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figur es MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 11 Panas onic List of Figures 1-1 Con vention al vs. MN102H Series Cod e Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of F igures Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 12 Panas onic 4-20 One-Shot Pulse Outpu t T iming (16-Bit T imers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figur es MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 13 Panas onic 5-12 Serial Interface C lock T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of F igures Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 14 Panas onic 7-31 Shuttered Area Setup Exam ples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Figur es MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 15 Panas onic 11-16 P30/CLH and P33/C LL (Port 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
About This Manual Using This Manual Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 16 Panas onic Abou t This Manual This manual is intended fo r assembly-lan guage programming engineers. It describ es the inte rnal conf iguration and hardware fu nctions of the MN102H75 K and MN102H85 K microcont rollers .
About This Manual Related Documents MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 17 Panas onic Related Documents ■ MN102H S eries LSI Us er Manua l (Describes the core hardw are.) ■ MN102H S eries In struction Ma nual (Describes the instruction set.
General Description MN102H Series Overview Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 18 Panasonic 1 General Description 1.1 MN102H S eries Over view The 16-bit MN102H seri es is the hi gh-speed l inear addr essing v ersio n of the MN10200 series.
General Description MN102H Se ries Feature s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 19 Panasonic ■ Single-byte basic instr uction lengt h The M.
General Description MN102H Series Feature s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 20 Panasonic ■ Fast interrupt response MN102H series de vices can stop execu ting instructions, e ven those with long e xecution c ycles, to service interrupts immediately .
General Description MN1 02H Seri es De scriptio n MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 21 Panasonic ■ Outstanding po wer savings The MN102H s.
General Description MN102 H Serie s Descrip tion Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 22 Panasonic NX: Exte nsion ne gativ e flag If the most significant bit of the result of an operation has the value 1, this flag is set; if that bit is 0, th is flag is reset.
General Description MN1 02H Seri es De scriptio n MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 23 Panasonic ■ Internal regis ters, memory , and spec ial function re gisters Note: 1. This all o cation is a r ep resent a t i ve example.
General Description MN102 H Serie s Descrip tion Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 24 Panasonic ■ Addre ss spa ce The memory in the MN102H series is conf igured as linear address space.
General Description MN1 02H Seri es De scriptio n MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 25 Panasonic ■ Interrupt contr oller An interrupt con troller e xternal to the core co ntrols all nonmaskable and maskable interrupts e xcept reset.
General Description General Specifications Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 26 Panasonic 1.4 Gener al Spec ifi cations T able 1-1 General Specific.
General Description General Specifications MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 27 Panasonic Timer/counters F our 8-bit timers: ♦ Cascading f.
General Description Block Diagram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 28 Panasonic 1.5 Block Diagram Figure 1-8 F unctional Block Diagram A1 A0 A3 A2.
General Description Block Diagram MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 29 Panasonic T able 1-2 Bloc k Diagram Explan ation Bloc k Description Clock generator An oscillation circuit connected to a n e x ternal cr ystal supplies the clock to all blocks withi n the CPU.
General Description Pin Descriptions Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 30 Panasonic 1.6 Pin Descriptions 1.6.1 MN102 H85K Pin Description Notes: 1. Pins marked with an as terisk (*) are N-channel , open-drain pins.
General Description Pin D escrip tions MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 31 Panasonic 1.6.2 MN102 H75K Pin Description Notes: 1. Pins marked with an aste risk (*) are N-chann el, open-drain pins.
General Description Pin Descriptions Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 32 Panasonic T able 1-3 Pin Functions Bloc k Pin Name I/O Pin Count Descript.
General Description Pin D escrip tions MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 33 Panasonic I/O ports MN102H75K/HF75K: total 66 pins MN102H85K/HF8.
General Description Pin Descriptions Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 34 Panasonic ■ Consideration s f or pow er suppl y , c lock, and res et pins ■ Connection th e PLL circu it The MN102H75K/85 K contains an internal PLL circuit.
General Description Bus Interface MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 35 Panasonic 1.7 Bus Int erface 1.7.1 Descrip tion The b us interface op erates in external e xtension mode. Figure 1-15 pr ovides the memory space fo r the MCU in this mode.
General Description Bus Interface Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 36 Panasonic 1.7.2 Bus Interface Control Registe rs The ex ternal memory wa i t regis ter (EXWMD) and memo ry mode regi ster 1 (MEMMD1) control the bus interf ace.
Inter r upts Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 37 Panasonic 2 Inte rru pts 2.1 Des cription The most important f actor in real-time cont rol is an MCU’ s speed in servicing interrupt s.
Interrupts Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 38 Panasonic Figure 2-2 In terrupt V ector Gro up and Class Assignments Group Interrupt V .
Inter r upts Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 39 Panasonic Figure 2-3 Inte rrupt Servicing Time T able 2-2 Handler Pr epr ocess.
Interrupts Interrupt Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 40 Panasonic 2.2 Interrupt Setup Exampl es 2.
Inter r upts Interrupt Setup Exa mples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 41 Panasonic 3. Enable interrupts by writing a 1 to the interrupt enable flag (IE) in the PSW and setting th e interrupt masking level (IM[2:0]) to 7 (b’111’).
Interrupts Interrupt Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 42 Panasonic 2.2.2 Setting U p a W atchdog T imer Inter rupt The watchd og time r int err upt is provided fo r detec ting a nd hand ling racing.
Inter r upts Interrupt Setup Exa mples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 43 Panasonic The main program normally gen- erates and branches to the inter- rupt star t address. If the CPU accepts an interrupt, th e program br anches to address x’080 008’.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 44 Panasonic 2.3 Interrupt Contr ol Registers A control re gister is assigned to each interrupt v ector group.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 45 Panasonic XnICL (System Interrupt) IR: Interrupt requ est flag.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 46 Panasonic T able 2-4 Inte rrupt Contr ol Register s Register Address R/.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 47 Panasonic ADM3ICL ADM3ICH ADM2ICL ADM2ICH ADM1ICL ADM1ICH ADM0.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 48 Panasonic IA GR: Accept ed Inte rrupt Group Numb er Regis te r x’00 FC0E ’ IA GR returns the group number of an accepted interru pt, indicated in the 6-bit GN f ield.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 49 Panasonic PIICR: Undefin ed Instruction Int err upt Cont rol Regi ster x’00 FC44 ’ PIICR is an 8-bit access re gister .
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 50 Panasonic IQ0ICH: External Interrupt 0 Inte rr upt Control Regis ter (High) x ’00F C49’ IQ0ICH sets the priority level for and enables external interrupt 0.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 51 Panasonic IQ2ICL: Ex ternal Interrupt 2 Interrupt Control Register (Low ) x’ 00F C50’ IQ2ICL requ ests and v erifies interrup t requests for e xternal interrupt 2.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 52 Panasonic IQ3ICH: External Interrupt 3 Inte rr upt Control Regis ter (High) x ’00F C53’ IQ3ICH enables ex ternal interrupt 3.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 53 Panasonic IQ5ICL: Ex ternal Interrupt 5 Interrupt Control Register (Low ) x ’00FC5A’ IQ5ICL requ ests and v erifies interrup t requests for e xternal interrupt 5.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 54 Panasonic TM4CBI CH: Timer 4 Compar e/Capture B Interr upt Contr ol Register ( High) x’00FC61’ TM4CBICH sets the priority le vel for and enables timer 4 compare/capture B interrupts.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 55 Panasonic TM4UDICL: Timer 4 Underfl ow I nterrupt Control Regis ter (Lo w) x’00 FC64 ’ TM4UDICL detects and requests timer 4 und erflow interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 56 Panasonic VBIICH: VBI (1) Inte rrupt Control Re gister (High ) x’00 FC67 ’ VBIICH enables VBI (1) interru pts. It is an 8-bit access re gister .
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 57 Panasonic TM5CAI CL: Ti mer 5 Co mpare/Cap ture A Interr upt Con trol Register (Low) x’00FC6A ’ TM5CAICL detects and requ ests timer 5 compare/capture interr upts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 58 Panasonic TM5UDICH: Timer 5 Underflo w Interrupt Control Reg ister (High) x’00FC6D’ TM5UDICH enables timer 5 underflo w interrupt s.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 59 Panasonic TM2UDICL: Timer 2 Underfl ow I nterrupt Control Regis ter (Lo w) x’00 FC70 ’ TM2UDICL re gister detects and request s timer 2 underflo w interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 60 Panasonic TM1UDICH: Timer 1 Underflo w Interrupt Control Reg ister (High) x’00 FC73 ’ TM1UDICH enables timer 1 underflo w interrupt s.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 61 Panasonic RMCICL: Remo te Sig nal Rece ive Inter ru pt Co ntro l Reg iste r (Low ) x’00F C76’ RMCICL detects and requests remote signal recei ve interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 62 Panasonic ADM3ICH: Address 3 Matc h Interrupt Contro l Register (High) x’00 FC79 ’ ADM3ICH sets the prio rit y level for and enables address match 3 in ter- rupts.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 63 Panasonic ADM1ICL: Address 1 Match Inte rr upt Control R egiste r (Lo w) x’00FC7C’ ADM1ICL detects and requests address match 1 interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 64 Panasonic ADM0ICH: Address 0 Matc h Interrupt Contro l Register (High) x’00 FC7F ’ ADM0ICH enables address match 0 interru pts.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 65 Panasonic SCT0ICL: Serial 0 T ransmis sion End Interrupt Co ntrol Regis ter (Lo w) x’00 FC82 ’ SCT0ICL detects and requests serial 0 transmission end interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 66 Panasonic SCR0ICH: Serial 0 Reception End Inte rrupt Control Re gister (High) x ’00 FC85 ’ SCR0ICH enables serial 0 reception end interrupts.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 67 Panasonic VBIVWICL: VBIVSYNC (2) In terrupt Control Regis ter (Low) x’00FC8A’ VBIVWICL detects and requests VB IVSYNC (2) interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 68 Panasonic TM3UDICH: Timer 3 Underflo w Interrupt Control Reg ister (High) x’00FC8D’ TM3UDICH enables timer 3 underflo w interrupt s.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 69 Panasonic OSDCICL: OSD (T e xt) Interrupt Con trol Regi ster (Lo w) x’00F C92’ OSDCICL detects and requests OSD (tex t) interrupts.
Interrupts Interrupt Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 70 Panasonic SCT1ICH: Serial 1 T ransmiss ion En d Interrupt Control Register (High) x’00F C99’ SCT1ICH sets the prio rity le vel for and enab les serial 1 transmiss ion end interrupts.
Inter r upts Interrupt Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 71 Panasonic I2CICL: I 2 C Inter ru pt Co ntro l Regi ste r (Low) x’00FC9C’ I2CICL detects and requests I 2 C interru pts.
Low-Power Modes CPU Mode s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 72 Panasonic 3 Low-P ower Modes The MN102H75K/85 K provides tw o ways to reduce p ower.
Low-P owe r Mod es CPU Modes MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 73 Panasonic 3.1.2 Exiting from S LO W Mode to NORMAL Mode The MN102H75K/85K rec ov ers from pow er up and reset in SLOW mode. F or nor mal opera- tion, the progr am must s witch the MCU from SLO W to NOR- MAL mode.
Low-Power Modes CPU Mode s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 74 Panasonic 3.1.3 Notes on In v oking a nd Exiting STOP and HAL T Modes ■ When in v oking ST OP and HAL T modes.
Low-P owe r Mod es Turning I ndividual Func tions On an d Off MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 75 Panasonic 3.2 T urning Individual Functions On and Off Y ou c annot set the PLL fun ction control bit during NORMAL mode .
Low-Power Modes CPU Cont rol Regist er Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 76 Panasonic 3.3 CPU Control Register CPUM: CPU Mode Control Register x’00 FC00 ’ This r egis ter controls the in v oking of all of the CPU modes.
Time rs 8-Bit Timer Desc ription MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 77 Panasonic 4T i m e r s 4.
Timers 8-Bit Timer Fe atures Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 78 Panasonic 4.2 8-Bit Timer Features T able 4-1 8-Bit Timer Func tions and Fe ature.
Time rs 8-Bit Timer Block Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 79 Panasonic 4.3 8-Bit Ti mer Block Diagrams Figure 4-3 Ti mer 0 Block .
Timers 8-Bit Timer Block Diagrams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 80 Panasonic Figure 4-5 Ti mer 2 Block Dia gram Figure 4-6 Ti mer 3 Block Dia g.
Time rs 8-Bit Timer Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 81 Panasonic 4.4 8-Bit Timer Timing Figure 4-7 Ev ent Timer Input Timing (8-Bit.
Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 82 Panasonic 4.5 8-Bit Timer Setup Examples 4.5.1 Setting Up an Event Counte r Using T imer 0 In this example, timer 0 generates an underflow interrupt on the fourth rising edge of the TM0 IO signal.
Time rs 8-Bit Timer Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 83 Panasonic TM0UDICL (e xample) x’00 FC74 ’ TM0UDICH (e xample) x’00 FC75 ’ 4. Set the divide-by ratio for timer 0.
Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 84 Panasonic 4.5.2 Setting Up an Interva l T imer Usin g T ime rs 1 and 2 In this ex ample, timers 1 and 2 are cascaded to di vide B OSC /4 b y 60,000 an d generate an underflo w interrupt.
Time rs 8-Bit Timer Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 85 Panasonic TM2UDICH (e xample) x’00 FC71 ’ TM2UDICL (e xample) x’00 FC70 ’ TM1UDICH (e xample) x’00 FC73 ’ TM1UDICL (e xample) x’00 FC72 ’ 3.
Timers 8-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 86 Panasonic TM2MD (e xample) x’00 FE22 ’ In the bank and l inear address- ing v ersions of the MN102 series, it was necessary to set TM0EN and TM0LD to 0 between steps 4 and 5, to ensure stable oper ation.
Time rs 8-Bit Timer Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 87 Panasonic 4.6 8-Bit Timer Control Register s T able 4-2 s ho ws the re gister s used to co ntrol the 8-bit timers.
Timers 16-Bit Timer Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 88 Panasonic 4.7 16-Bit Timer Description The MN102H75K/85 K contains two 16-b it up/d own ti mers, timers 5 an d 6.
Time rs 16-Bit Timer Fe atures MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 89 Panasonic 4.8 16-Bit Timer Features T able 4-3 16-Bit Timer Functions a .
Timers 16-Bit Timer Block Diagrams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 90 Panasonic 4.9 16-Bit Timer Bloc k Diagrams 4.
Time rs 16- Bit Time r Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 91 Panasonic Figure 4-18 Si ngle-Phase PWM Outp ut Timing with Data Chang e .
Timers 16-Bit Timer Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 92 Panasonic Figure 4- 21 Extern al Count Direction Control Timing ( 16-Bit Ti mers) F.
Time rs 16- Bit Time r Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 93 Panasonic Figure 4- 24 T wo-Phase Capture I nput T iming (16-B it Timers).
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 94 Panasonic 4.11 16-Bit Timer Setup Examples 4.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 95 Panasonic TM4CA (e xample) x’00 FE84 ’ 3. Set the phase dif ference for timer 4. F or a 2-c ycle phase dif ference, write x’0001’ to timer 4 compare/capture re gi ster B (TM4CB).
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 96 Panasonic 4.11.2 Setting U p a Sing le-Phase PWM Outp ut Signal Using Ti me r 4 In this example, timer 4 is used to divide B OSC by 5 a nd generate a f iv e-cyc le, single-phase PWM signal.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 97 Panasonic P2DIR (e xample) x’00FFE 2’ ■ T o set up time r 4: Use the MO V instruction for this setup and only use 16-bit write operations .
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 98 Panasonic 6. Set the TM4NLD bit of the TM4MD register to 1 and th e TM4EN bit to 0. This enables TM4BC and the S-R flip-flop. This step ensures stable opera- tion.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 99 Panasonic Figur e 4-30 bel o w sho ws the out put wa vefor ms for TM4O A. Both A and B interrupts can occur, b ut B interrupts can only occur if the TM4CB setting is from 0 to less than TM4C A.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 100 Panasonic T wo potential types of errors are inherent with PWM o utput. First, because of the circuit conf iguration, direction errors can occur .
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 101 Panasonic 4.11.3 Setting Up a T wo-Ph ase PWM Output Sign al Using Ti me r 4 In this e xample, timer 4 is used to di vide timer 0 underflo w by 5 and g enerate a fi ve- cycle, two-phase PWM s ignal.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 102 Panasonic P2DIR (e xample) x’00FFE 2’ ■ T o set up time r 0: 1. Disable timer 0 count ing in the timer 0 mode regis ter (TM0MD).
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 103 Panasonic ■ T o set up time r 4: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM4BC count and clears both TM 4BC and the S-R flip-flop to 0.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 104 Panasonic 6. Set the TM4NLD bit of the TM4MD register to 1 and th e TM4EN bit to 0. This enables TM4BC and the S-R flip-flop.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 105 Panasonic W ith PWM output, the duty cycle can chan ge dynami cally , which can cau s e the PWM wa veform t o skip a pu lse (see the sin g le buf fering section of fi gure 4-34 belo w).
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 106 Panasonic 4.11.4 Setting U p a Sing le-Phase Capture Input Using Timer 4 In this example, timer 4 is used to divide B OSC /4 by 6 5,536 and measure ho w long the TM4IA inp ut signal stays high .
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 107 Panasonic change an y other operati ng modes du ring t his step. When TM4MD[1:0] = b’10’ (dur- ing capture), TM4CA and TM4CB become read-only regis- ters.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 108 Panasonic 4.11.5 Setting Up a T wo-Ph ase Capture Inp ut Using Tim er 4 In.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 109 Panasonic TM0BR (e xample) x’00 FE10 ’ Do not change the cloc k source once you select it.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 110 Panasonic ■ T o service the inte rrupts and calculate the signal wi dth: 1. Run the interrupt service routine. Th e rout ine must determine the int errupt group, then clear th e interrupt request flag.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 111 Panasonic 4.11.6 Setting Up a 4x T wo-Phase Encod er Input Using Timer 5 In this ex ample, timer 5 inputs a 4 x two-phase en coded signal that makes it count up and do wn.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 112 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 113 Panasonic ■ T o service the inte rrupts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 114 Panasonic 4.11.7 Sett ing Up a 1 x T wo- Phase Encod er Input U s i n g Ti m e r 5 In this ex ample, timer 5 inputs a 1 x two-phase en coded signal that makes it count up and do wn.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 115 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 116 Panasonic ■ T o service the inte rrupts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 117 Panasonic 4.11.8 Setting U p a On e-Shot Pulse Ou tput Using T imer 5 In this e xample, timer 5 o utputs a one-s hot pulse.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 118 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 119 Panasonic T imer 5 can output a one-shot pulse. T imer 5 do es no t o pera te in STOP mo de , when B OSC is o ff. If you use an e xternal clock, it mus t be synchro nized t o B OSC .
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 120 Panasonic 4.11.9 Setting Up an Extern al Coun t Direction Contr oller Using T im er 5 In this ex ample, timer 5 counts B OSC /4 and the T M5IA pin controls the count direction (up o r down).
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 121 Panasonic ■ T o set up time r 5: Use the MO V instruction for this setup and only use 16-bit write operations . This step stops the TM5BC count and clears both TM 5BC and the S-R flip-flop to 0.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 122 Panasonic ■ T o service the inte rrupts: Run the interrupt s ervice routine. The routi ne must determine the in terrupt group, then clear the interru pt request flag.
Time rs 16-Bit Timer Setup Ex ample s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 123 Panasonic 4.11.10 S etting Up Extern al Reset Contro l Using T imer 5 In this example, timer 5 is reset by an e xternal signal while countin g up.
Timers 16-Bit Timer Setup Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 124 Panasonic TM5CA (e xample) x’00 FE94 ’ 3. Set the TM5NLD bit of the TM5MD register to 1 and th e TM5EN bit to 0. This enables TM5BC and the S-R flip-flop.
Time rs 16-Bit Timer Con trol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 125 Panasonic 4.12 16-Bi t Timer Con trol Registers T able 4-6 sho ws the register s used to control the 16 -bit timers.
Timers 16-Bit Timer Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 126 Panasonic TM4MD/TM5M D: Time r n Mode Re gister x’00F E80’/x’00FE.
Serial Interfaces Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 127 Panasonic 5 Serial Interfaces 5.1 Des cription The MN102H75K/85 K contains two g eneral-pur pose serial interfaces with syn- chronous serial, U AR T , and I 2 C modes.
Serial Interfaces Connecting the Serial Interfaces Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 128 Panasonic 5.3 Connecting the Serial Interfaces Figures 5-2, 5-3, and 5 -4 illustrate six different methods of connectin g the serial interface.
Serial Interfaces UART Mode Baud Ra tes MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 129 Panasonic 5.4 U ART Mode Baud Rates In U AR T mode, the serial inter face transfer clock is set to 16 times the baud rate clock.
Serial Interfaces Serial Interfac e Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 130 Panasonic 5.5.2 U ART Mode Timing In these timing charts, the character leng th is 8 bits, the parity is none, and the stop bit is 2-b it.
Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 131 Panasonic 5.6 Seri al Inte rface S etup Ex ample s 5.6.1 Setting U p U ART T rans mission Using S erial Interface 0 Y ou must use an 8-bit timer to set the tr ans fer cloc k.
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 132 Panasonic ■ T o set up seria l interface 0: 1. Config ure the t ransmissi on sett ings in the se rial port 0 contro l re gister (SC0CTR).
Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 133 Panasonic ■ T ransmission s e quence: 1. Write the first data byte to SC0TRB. Once th is data is in the register , trans- missio n begi ns, syn chronized to ti mer 0.
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 134 Panasonic 5.
Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 135 Panasonic 5.6.3 Setting Up the Ser ial Interface Clock This e xample demonstr ates how to set up a 19,200 bps transfer clock for the U AR T inte rfac e by usin g timer 1 to di vide B OSC /4 by 39.
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 136 Panasonic Do not change the cloc k source once you select it. Selecting t he clock source while you set up the count operati on control will corrupt the value in the binar y counter .
Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 137 Panasonic 5.6.4 Setting U p I 2 C T r ansmissio n Using Serial Inte rface 0 This example illustrates the microco ntroller as a master transmitter in the I 2 C mode, usin g the SBO0 and SBT0 pins.
Serial Interfaces Ser ial In terfac e Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 138 Panasonic Reception must be enabled f or the circuit to det ect a stop sequence. 2. When you perfor m step 1, the SBT0 output sign al goes high.
Serial Interfaces Serial Inter face Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 139 Panasonic 5.6.5 Setting U p I 2 C Recep tion Using Seria l Interface 0 This e xample illustrates the microcontroller as a master recei ver in the I 2 C mode, using th e SBO 0 a nd SBT 0 pins.
Serial Interfaces Ser ial In terfac e Co ntrol Regist ers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 140 Panasonic 5.
Serial Interfaces Serial Interface Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 141 Panasonic SCnICM: Serial por t n I 2 C mode sel e.
Serial Interfaces Ser ial In terfac e Co ntrol Regist ers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 142 Panasonic SC0STR/SC1STR: Serial P or t n Status R egister x’0 0FD83’/x’00F D8B’ SCnSTR contains the error d etection and status flags for the serial inter- faces.
Analog-to- Digital Converter Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 143 Panasonic 6 Analo g-to-Dig ital C on ver ter 6.1 Des cription The MN102H75K/85 K contains an 8-bit char ge redistrib ution A/D con v erter (ADC) that can process up to 12 channels.
Analog-to-Digital Converter Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 144 Panasonic 6.3 Block Diagram 6.
Analog-to- Digital Converter A/D Conver sion Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 145 Panasonic 6.4.2 Sin gle Channe l/Single Con version T imin g When ANMD[1:0] = b’00’, th e ADC con verts one ADIN input signal a single time.
Analog-to-Digital Converter A/D Conversion Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 146 Panasonic 6.4.4 Sin gle Channe l/Continuo us Con version T iming When ANMD[1:0] = b’10’, th e ADC con verts one ADIN input signal contin- uously .
Analog-to- Digital Converter ADC Setup Ex amples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 147 Panasonic 6.5 ADC Set up Examples 6.5.1 Setting Up Softw are-Controlled Single -Channel A/D Con v ersion This example illustrates si ng le-channel con version controlled by the software.
Analog-to-Digital Converter ADC Setup Exam ples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 148 Panasonic AN6BUF (e x ample) x’00FF1 4’ 6.5.2 Setting Up Hardware- Controlle d Intermit tent Three-Channel A/D Con ver sion This example illustrates multip le-channel con version controlled by the hardware.
Analog-to- Digital Converter ADC Setup Ex amples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 149 Panasonic ■ T o set up the i nput port: Set the P0DIR[5:3] bi ts of the port 0 I/O cont rol register (P0DIR) to 0.
Analog-to-Digital Converter ADC Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 150 Panasonic 6.6 ADC Cont r ol Re gisters The ADC contains thirteen re gisters—one control re gister (ANCTR) and twelv e data b uf f ers (each asso ciated with one of the ADIN pins).
Analog-to- Digital Converter ADC Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 151 Panasonic ANCTR: ADC Control Register x’00FF0 0.
Analog-to-Digital Converter Cautions abo ut Analog-to-Digita l Converter Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 152 Panasonic 6.
On-Screen Display Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 153 Panasonic 7 On-Screen Displa y If you use the OSD function, the DMA function ex ecutes for both the te xt and graphics la yers, e ven if y our program does not use one of these la yers .
On-Screen Display Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 154 Panasonic 7.3 Block Diagram Figure 7-1 O SD Block Diagram VSYNC Vertical po.
On-Screen Display Power-Saving Considerations in the OSD Blo ck MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 155 Panasonic 7.4 P ower -Sav ing Considerations in the OSD Bloc k T able 7-2 sho ws bits that can decrease the power consumption of the OSD block.
On-Screen Display OSD O per ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 156 Panasonic 7.5 OSD Operation This sect ion descr ibes the basi c operation of the OSD block. The remainder of section 7 pro v i des more det ai le d specif ications.
On-Screen Display OSD Opera tion MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 157 Panasonic ■ Graphi cs la yer The graphics layer contains tiled images. In the 16-color mode, each 4-bit dot on a tile can display one of 16 colo rs.
On-Screen Display OSD O per ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 158 Panasonic 7.5.7 Co n ditions for V RAM Writes ■ T ext layer Set CHP , CVP , GHP , and GVP f or ev ery line in the VRAM. If you do not, a soft ware processing error may occur .
On-Screen Display Standa rd and Exten ded Display Mode s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 159 Panasonic 7.6 Standard and Extended Di spla y Modes T wo modes are a vailable for the graphics and cursor layers, standard and e xtended.
On-Screen Display Standard and Extended Dis play Mode s Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 160 Panasonic In standard mode, STC 0 is the only cursor tile co de register that is enabled.
On-Screen Display Display Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 161 Panasonic 7.7 Display Setup Examples 7.7.1 Se tting Up the Graph ics Layer This sect ion sho ws ho w to set up the graphics display data in the VRAM.
On-Screen Display Display Setu p Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 162 Panasonic Figure 7 -4 Graph ics Displ ay Ex ample Line 1 HSZ= 1 (2x.
On-Screen Display Display Setup Examples MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 163 Panasonic 7.7.2 Se tting Up the T ext Layer This section sh ows ho w to set up the text display data in th e VRAM.
On-Screen Display Display Setu p Examples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 164 Panasonic The te xt displa y starts one dot to the right of the HP setting.
On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 165 Panasonic 7.8 VRAM 7.8. 1 VRAM Oper ati on ■ T ext Layer CC: Charac ter Code ID Code: 0 0 CCH[9:0] Specifi es the address of one o f 1024 character s stored in the R OM.
On-Screen Display VRAM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 166 Panasonic BLINK Specifies character blink ing. 0: Disa ble 1: Enable BCOL[3:0] Specifi es the backgroun d color (1 of 16 color s). CCOL[3 :0] Specifi es the fore ground (character) color (1 of 16 colors).
On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 167 Panasonic CHP: Char acter H orizontal P osition C ontrol Co de ID Code: 1 1 CHSZ[1:0] Specifies the H size of the characters on the next line.
On-Screen Display VRAM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 168 Panasonic GCB[3:0] Specif i es the number o f times (up to 16) a blank or graphi c til e is repeated. GPRT Specifies grap hics color palette 1 or 2 .
On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 169 Panasonic 7.8.2 VRAM Organiz ation Notes: 1. A ll addre sses are e xpressed in he x notation. Other v alues are de cimal. 2. G RAMEND: Graph ics RAM end ad dress (programma ble to any address) 3.
On-Screen Display VRAM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 170 Panasonic A. GE XTE = 1 B. GE XTE = 0 Figure 7-7 Graphic s VRAM Organ ization for T w .
On-Screen Display VRAM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 171 Panasonic 7.8.3 Ca utions about the number of displa y code set to VRAM When th.
On-Screen Display ROM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 172 Panasonic 7.9 ROM 7.9.1 R OM Or ganizatio n Notes: 1. A ll addre sses are e xpressed in he x notation. Other v alues are de cimal. 2. G R OM END: Graphics R OM end ad dress (prog r ammable to any addr ess) 3.
On-Screen Display ROM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 173 Panasonic 7.9.2 Graph ics ROM Organ izatio n in Different Color Modes The graphics layer supports up to sixteen colors, in the 16-color mode, but also supports 2-, 4- , and 8-color modes.
On-Screen Display ROM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 174 Panasonic Figure 7-11 G raphics R OM in the Fou r Color Modes (1 6W x 16H Tiles) ROMEND.
On-Screen Display ROM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 175 Panasonic Figure 7-12 G raphics R OM in the Fou r Color Modes (1 6W x 18H Tiles).
On-Screen Display ROM Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 176 Panasonic Figure 7- 13 Graphics R OM Orga nization in 16-Color Mo de (16W x 16H Tiles) .
On-Screen Display ROM MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 177 Panasonic Figure 7- 17 Graphics R OM Orga nization in 16-Color Mo de (16W x 18H .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 178 Panasonic 7.10 S etting Up t he O SD 7.10.1 Setting U p the OS D Display Colo rs This section des cribes how to set up the display colors for the OSD.
On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 179 Panasonic ■ T o set up the te xt displa y color s: Write to the fields described below . ♦ CCOL[3:0] (CO L bits 3 to 0 in the RAM dat a) sets the color of th e charac- ter .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 180 Panasonic T r ansluce ncy Selecting YS palette output, by setting the YSPL T bit of OSD1 (x’007F06’) to 1, disab les the PR YM bit.
On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 181 Panasonic T able 7-9 RGB, YM, and YS Output Contr ol Settings YSP.
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 182 Panasonic Figure 7-21 OSD Signal W avef orm TV Graphics la yer Color pal.
On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 183 Panasonic Figure 7-22 OSD Sig nal Output Switches *** YM3 Bit 15 .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 184 Panasonic 7.10.2 T ext La yer Function s This section describes the cha racter enhancement functions a vailable in the te xt layer .
On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 185 Panasonic ■ Bo x shadowing In normal mode, writing a 1 to b it 12 (BSHAD1) o f the COL s etting in the VRAM causes a box shado w to appear around all ch aracters follo wing that COL.
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 186 Panasonic ■ Italicizin g In closed-caption mod e, writ ing a 1 to bit 10 (IT ALIC) of the CO L settin g in the VRAM italicizes all characters follo wing that COL.
On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 187 Panasonic 7.10.3 Display S izes ■ Graphic ti le siz es The settings shown are f or interlaced displays .
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 188 Panasonic ■ Characte r sizes The settings sho wn are for interlaced displa ys. In progressiv e displa ys, the v er tical size sett ings (CVSZ[1:0]) are as f ollows: 01 = 1x, 10 = 2x, and 11 = 3x.
On-Screen Display Setting Up the OSD MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 189 Panasonic 7.10.4 Setting U p the OS D Display P osition This sect ion descr ibes ho w to control th e positioni ng of t he OSD.
On-Screen Display Setting Up the OSD Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 190 Panasonic ■ T o set up the v ertical position: Cursor ♦ Write the vertical position of the cursor to th e SVP[9 :0] field (x’007F14 ’).
On-Screen Display DMA and Inte rrupt Timing MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 191 Panasonic 7.11 DMA and Interrupt Timing This sect ion descr ibes ho w the MN102H75K/85K han dles the ti ming of di rect memory access (DMA) transfers of OSD data and OSD interrupts.
On-Screen Display DMA and Inte rrupt Timing Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 192 Panasonic Figure 7-30 DMA an d Interrupt Timing f or the OSD Text.
On-Screen Display Selecting the OSD Dot Clock MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 193 Panasonic 7.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 194 Panasonic 7.13 Contr olling the Shuttering Effect The MN102H75K/ 85K OSD achi e ve s a shut tering eff ect using four pro- grammable shutters — two v er tical and tw o h orizo ntal.
On-Screen Display Controlling the Shu ttering Effect MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 195 Panasonic Figure 7-3 1 Shuttered Area Se tup Exam.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 196 Panasonic 7.
On-Screen Display Controlling the Shu ttering Effect MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 197 Panasonic Figure 7- 32 Shutter Mo vement Setup Ex.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 198 Panasonic 7.13.3 Controlling S huttering Effects Through register set tings, yo u can inde pendently control s hutter ing for t e xt, te xt backgroun d, graphi cs, and col or backgroun d.
On-Screen Display Controlling the Shu ttering Effect MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 199 Panasonic ■ T o shutter the co lor bac kground: Set the color backg rou nd shutter con trol bit, COLBSHT , of the shut ter cont rol re gister , SHTC (x’00 7F28’) to 1.
On-Screen Display Controlling the Shuttering Effect Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 200 Panasonic 7.
On-Screen Display Field Detection Circuit MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 201 Panasonic 7.14 Field Detection Cir cuit 7.14.1 Block Diagr am 7.14.2 D escription The 7-bit field counter in this block reset s e very HSYNC interval to count the system clock.
On-Screen Display Field Detection Circuit Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 202 Panasonic 7.14.3 Considera tions for Interlaced Displays ■ Switch ing the displ ay start field The OSD is constructed so the display start p osition is the field (f ield 1) where the EOMON bit is 1.
On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 203 Panasonic 7.15 OSD Re gisters All registers in OSD block canno t be written by byte (by word only). Read by byte is poss ible.
On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 204 Panasonic is x’900F ’ to x’9FFF ’, with a programmabl e range from x’0 0’ to x’ FF’.
On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 205 Panasonic STC3: Cursor Tile Code Register 3 x’007E2E’ SPR T3: Cur.
On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 206 Panasonic 00: 1 dot = 1 VCLK peri od 01: 1 dot = 2 VCLK peri ods 10: 1 dot = .
On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 207 Panasonic CIVSZ[1:0]: T e xt initia l ver tical s ize CIVP[9:0] : T e.
On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 208 Panasonic OSD1: OSD Regi ster 1 x’00 7F06’ A write to the OS D bit of OSD1 takes eff ect on the ne xt leading edge of VSYNC.
On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 209 Panasonic OSD2: OSD Regi ster 2 x’007F0 8’ SPEXT: Cursor ex tende.
On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 210 Panasonic OSD3: OSD Regi ster 3 x’007F 0A’ BLINK: Characte r bli nking c ontrol Controls blinking for text-layer characters with BLINK set in the COL code.
On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 211 Panasonic VSHT1: V er tical Shutter 1 Register x ’007F2 2’ VSON1:.
On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 212 Panasonic HSHT1: Horizo ntal Shutter 1 Regis ter x’007F26’ HSON: Horizo n.
On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 213 Panasonic CPT0 – CPTF: T ext P alet te Colors 0 – 15 Re gisters x’007F80 ’ – x’007F9 E’ These reg isters contain the colors used in the text layer .
On-Screen Display OSD Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 214 Panasonic BBSHD: Blac k Bo x Shadowing R egi ste r x’007F A4’ This re gister con t ains the color used as black in bo x shad o wing.
On-Screen Display OSD Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 215 Panasonic GPT20 – GPT2F: Graphics P alette 2 Colors 0 – 15 Registers x’007FE0’ – x’007FFE’ These re gisters contain one of tw o sets of colors used in the graphics laye r .
IR Remote Signal Receiver Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 216 Panasonic 8 IR Remo te Signal Receiver 8.
IR Remote Signal Receiver Block Diagram MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 217 Panasonic 8.2 Block Diagram Figure 8 -1 IR Remot e Signal Receiver B loc k Diagram 54 3 2 1 0 MUX CK CK 765 4 3210 MUX CK MUX R CK 4 RMTC: x’007E04’ Frequency division counter PWM3 (375 kHz, 2.
IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 218 Panasonic 8.3 IR Remote Signal Re ceiver Operation 8.3.1 O perating Modes The IR remote signal recei ver has three operatin g modes: HEAMA, 5-/6- bit, and HEAMA – 5-/6 -bit automatic detect .
IR Remote Signal Receiver IR Remo te Signal Receiver Operation MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 219 Panasonic 8.3.3 8-B it Data Reception Resetting the 8-bit data reception counter allows the microcontroller to receiv e 8- bit data, eith er with or without a leader .
IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 220 Panasonic 8.3.4 I dentifying the Data F o rmat The microcontrol ler determines the l ogic le v els o f the data by testin g the interval between remote signal edges.
IR Remote Signal Receiver IR Remo te Signal Receiver Operation MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 221 Panasonic 8.
IR Remote Signal Receiver IR Remote Signal Receiver Oper ation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 222 Panasonic 8.3.6 Co ntrolling the SL O W Mode Use bit 7 (SP) in the RMLD reg- ister to toggle the noise filter sampling frequency between PWM6/PWM8 and PWM3/ PWM5.
IR Remote Signal Receiver IR Remo te Signal Receiver Control Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 223 Panasonic 8.4 IR Remot e Signal Receiver Control Regis- ters All re gisters in RMC block cann ot be writ ten by byte (by w ord only).
IR Remote Signal Receiver IR Remote Signal Receiver Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 224 Panasonic All re gisters in RMC block cann ot be writ ten by byte (by w ord only). Read by byte is poss ible.
IR Remote Signal Receiver IR Remo te Signal Receiver Control Regis ters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 225 Panasonic RMIS: Remote Signa l Interrupt Status Register x’00 7EA0 ’ RMIR in dicates th e detection and oper ation st atus of r emote si gnal in ter- rupts.
IR Remote Signal Receiver IR Remote Signal Receiver Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 226 Panasonic RMLD: Remote Sig nal Lead er V alue Set Register x’007EA C’ RMLD is a 16-bit access re gister .
Closed-Caption Decoder Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 227 Panasonic 9 Closed-Caption D ecoder 9.1 Des cription The MN102H75K/85K contain s two identical closed-cap tion decoder circuits, CCD0 and CCD1.
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 228 Panasonic 9.3 Functional Description 9.3.1 An alog-to-Digital Co n verter The const an ts shown in figures 9-2 to 9-4 ar e re comm e nded values only .
Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 229 Panasonic 9.
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 230 Panasonic T able 9-5 pro vides th e re gisters used to control and mo nitor the clamp ing cir cuit. See the page number ind icated for re gist er and bit descriptions.
Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 231 Panasonic Figure 9-6 Sync Separator Ci rcuit Blo ck Diag.
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 232 Panasonic 9.3.3.1 HSYNC Se parator The HSYNC separator e xtracts the HSYNC signal from the co mposite sync signal u sing the s amplin g clock gen erated b y the sy nc separato r clock pu lse gen- erator .
Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 233 Panasonic 9.3.3 .2 VSYNC Separator The VSYNC separator e xtracts the VSYNC signal from the co mposite signal.
Closed-Caption Decoder Functional Des cription Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 234 Panasonic T able 9-7 pro vides the registers used to control and moni tor the data slicer . See the page number ind icated for re gist er and bit descriptions.
Closed-Caption Decoder Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 235 Panasonic 9.3.5.1 CRI Detection for Sampling Clock Generation The decoder cap tures the caption data on the rising edge of the CRI pulse.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 236 Panasonic 9.4 Closed-C aption Decoder Register s All registers in Closed-caption Decoder block cannot be written by byte (by word only).
Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 237 Panasonic For desig ns using the closed -cap- tion de coder, alw ays tie the FCC NT register to x’0008’ .
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 238 Panasonic MAXMIN: CRI Int er v al Max imum and Mi.
Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 239 Panasonic HNUM: HSYNC Count Register x.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 240 Panasonic CRIF A: CRI F requency Wi dth Register .
Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 241 Panasonic CRI1E: CRI Cap ture Stop Ti mi.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 242 Panasonic DA T A E : Data Cap ture Stop Timing Co.
Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 243 Panasonic FQSEL: F requency Select R egi.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 244 Panasonic Use this register to specify the position for capturing the pedestal level v alue used during pe destal clamping .
Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 245 Panasonic BSP[5:0]: Sy nc separ ator l e vel f or pedestal clampin g Sync separator level = (sync tip le vel/2) + BSP[5:0] .
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 246 Panasonic HSEP1: HSYNC Separ ator Control Registe.
Closed-Caption Decoder Close d-Cap tio n Deco der Re gist ers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 247 Panasonic HDISTW: Sy nc Separ ator Detec.
Closed-Caption Decoder Clos ed-Ca ption De coder Reg isters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 248 Panasonic CLPCND1: Clamping Control Si gnal Statu.
Pulse Width Modulator Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 249 Panasonic 10 Pulse Width Modulator 10.1 De scripti on F or inf or mation on the SLO W mode, see section 3.1, “CPU Modes.
Pulse Width Modu lator Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 250 Panasonic Not using internal pullup func- tion,Figuer10-2 connect the e x ter nal pullup registance 10.2 Block Diagram 10.
I/O Ports Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 251 Panasonic 11 I/O P orts 11.1 De scripti on The MN102H75K/85 K contains 50 pins th at form gen eral-purp ose I/O port s. Ports 0, 1 , 2, 3, 4, and 5 are 8-b it ports , and port 6 is a 2-bi t por t.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 252 Panas onic 11.2 I/ O P ort Circuit Dia g rams Figure 11- 1 P00/RMIN/IRQ.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 253 Panasonic Figure 11-2 P03/ADIN0 to P0 7/ADIN4 (P or t 0) P0PUPn 0.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 254 Panas onic Figure 11-3 P10/ADIN5/IRQ1, P11/ ADIN6/IRQ2, and P12/ADIN7/I.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 255 Panasonic Figure 11-4 P1 3/ADIN8/WDOUT and P14/ADIN9/ST OP (P or .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 256 Panas onic Figure 11-5 P15/AD IN10/PWM0 an d P16/ADIN11 /PWM1 (P ort 1).
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 257 Panasonic Figure 11-6 /PWM2 (P ort 1), P20/PWM3, P21 /PWM4, P22/P.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 258 Panas onic Figure 11- 7 P24/TM4IC/SBT1 (P ort 2) P2PUP4 0: Pullup off 1.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 259 Panasonic Figure 11-8 P27/TM0IO (P or t 2) P2PUP7 0: Pullup off 1.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 260 Panas onic Figure 11-9 P3 5/D AROUT/ R, P36/D A GOUT/G, P37/D ABOUT/B (.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 261 Panasonic Figure 11-1 0 P25/TM4IOB/SBI1/SBD1 and P 26/TM4IO A/SBO.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 262 Panas onic Figure 11-1 1 P55 and P5 6 (P ort 5) P5PUP5 0: Pullup off 1:.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 263 Panasonic Figure 11-12 P 57/SBT0 (P or t 5) P5PUP7 0: Pullup off .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 264 Panas onic Figure 11-1 3 P02/SCL1 (P or t 0) and P61/ SCL0 (P ort 6) P0.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 265 Panasonic Figure 11-14 P01/SD A1 (P ort 1) and P60/SD A0 (P ort 6.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 266 Panas onic Figure 11-15 P31/CVBS0 and P32/CVBS1 (Port 3) P3PUPn 0: Pull.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 267 Panasonic Figure 11-16 P30/CLH and P3 3/CLL (P ort 3) P3PUPn 0: P.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 268 Panas onic Figure 11-17 P34/VREF (P or t 3) P3PUP4 0: Pullup off 1: Pul.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 269 Panasonic Figure 11-18 P 41/TM1IO , P42/TM5IO A, and P4 3/TM5IOB/.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 270 Panas onic Figure 11-20 P45/OSDXO and P46/OSDXI (P or t 4) P4PUP6 (0: Cut,1: Connect) 0: Pullup off 1: Pullup on LCCNT is the OSDXI/O oscillation control signal from the OSD.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 271 Panasonic Figure 11-21 P47/HSYNC (P or t 4) P4PUP7 0: Pullup off .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 272 Panas onic Figure 11-22 P50/SYSCLK (P or t 5) P5PUP0 0: Pullup off 1: P.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 273 Panasonic Figure 11-23 P51/YS (P or t 5) P5PUP1 0: Pullup off 1: .
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 274 Panas onic Figure 11-24 P52/IRQ4/VI0 (P or t 5) P5PUP2 0: Pullup off 1:.
I/O Ports I/O Port Circ uit Diagrams MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 275 Panasonic Figure 11 -25 P53/RST (P ort 5) P5PUP3 0: Pullup off 1:.
I/O Ports I/O Port Ci rcuit Diagr ams Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 276 Panas onic Figure 11-26 P54/IRQ5/VSYNC (P ort 5) P5PUP4 0: Pullup off 1.
I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 277 Panasonic 11.3 I/ O P ort Contr ol Register s Do not activ ate the pullup resis- tors when the pins are in output mode.
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 278 Panas onic P0IN – P5IN: P or ts 0 – 5 Input Registers x’00FF D0’.
I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 279 Panasonic P0MD: P ort 0 Output M ode Regi ster x’00FFF 0’ P0MD is an 8-bit access reg ister .
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 280 Panas onic P1MD: P ort 1 Output M ode Regi ster x’00 FFF2’ P1MD is a 16-bit access reg is ter .
I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 281 Panasonic P2MD: P ort 2 Output M ode Regi ster x’00FFF 4’ P2MD is a 16-bit access reg is ter . P2MD14 : P27 func tion s witch T o use TM0IO as an output p in, set this b it to 1 and set th e P2DIR7 bit to 1.
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 282 Panas onic P3MD: P ort 3 Output M ode Regi ster x’00 FFF6’ P3MD is an 8-bit access reg ister . P3MD7: P37 output switch If you set this field to 1, select D AB OUT or B in the RGBC bit of ODS 1.
I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 283 Panasonic P4MD: P ort 4 Output M ode Regi ster x’00FFF 8’ P4MD is an 8-bit access reg ister . P4MD7: P47 function s witch 0: P47/NHSYNC 1: NHSYNC P4MD6 This bit exists, but contains no funct ion.
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 284 Panas onic P5MD: P ort 5 Output M ode Regi ster x’00FFF A’ P5MD is an 8-bit access reg ister . P5MD7: P57 output switch T o use SBT0 as an input pin , set this f ield to 0 and se t the P5DIR7 bit to 0.
I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 285 Panasonic PCNT0: P or t Control Re gister 0 x’00 FF90’ PCNT0 is a 16-bit access register . Enable PWM (set PCNT1 bit 1 to 1) if you are outputt ing f SY- SCLK /2 14 .
I/O Ports I/O Port Control Registers Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 286 Panas onic T o turn off the OSD b loc k to sa ve powe r : 1. Write a 0 to OSD (OSD1, b it 10). 2. W ait f or the ne xt VSYNC input.
I/O Ports I/O Port C ontrol Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 287 Panasonic PCNT2: P or t Control Re gister 2 x’00 FF92’ Alwa ys set bits 7 to 3 of PCNT2 to 0. Y ou cannot read from or write to the registers associated with a function that is disabled.
ROM Correction Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 288 Panasonic 12 R OM Correction 12.1 De scripti on The R OM correction func t ion can co rrect the p rog ram data in an y address within the 256-kilobyte R OM.
ROM Correction Block Diagram MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 289 Panasonic 12.2 Block Diagram Figur e 12- 3 i s a blo ck di agr am of the R O M cor rect ion ci rcu i t. A match detect io n circuit constantly monitor s the R OM address specified by the CPU instruction pointer (IP).
ROM Correction ROM Correction Control Re gisters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 290 Panasonic 12.4 R OM Correction Contr ol Registers T able 12-1 sho ws the organization o f the address match and data re gisters for R OM correction.
ROM Correction ROM Corr ection Control Re gisters MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 291 Panasonic R OMCEN12 : Addres s 12 R OM correct ion e.
ROM Correction ROM Correction Control Re gisters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 292 Panasonic AMCHIH0 – AMCHIHF: ROM C orrection Addres s Match Re gister n (H igh) AMCHIHn is an 8-bit access re gister .
I 2 C Bus Controller Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 293 Panasonic 13 I 2 C Bus Controller 13.1 De scripti on The MN102H75K/85 K contains one I 2 C b us controller , fully complian t with the I 2 C specif ication, that can control o ne of two I 2 C b u s connections.
I 2 C Bus Controller Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 294 Panasonic Figure 13-2 sho ws an e xample of an I 2 C bus con figurati on usi ng tw o micro con- trollers.
I 2 C Bus Controller Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 295 Panasonic Figure 13-3 sho ws the MN102H75K/85K op eration sequence in each o f these modes.
I 2 C Bus Controller Bloc k Diag ram Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 296 Panasonic 13.2 Block Diagram 13.3 Functional Description The I 2 C b us controlle r contains the regis ters sho wn in tabl e 13-3.
I 2 C Bus Controller Functional Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 297 Panasonic ■ Register settings con ver sions to I 2 C pr otocol The I 2 C b us controller con verts the data in the I2CDTRM register to the I 2 C protoco l.
I 2 C Bus Controller Setting Up the I 2 C Bus Con nection Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 298 Panasonic 13.4 S etting Up t he I 2 C Bus Connection Set the I 2 C connection in the I2CSEL0 and I2CSEL1 b its of the PCNT0 re gis ter (x’00FF90’).
I 2 C Bus Controller SDA and SCL W a veform Char acteristics MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 299 Panasonic 13.
I 2 C Bus Controller I 2 C In terf ace Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 300 Panasonic 13.
I 2 C Bus Controller I 2 C Interfac e Setup Example s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 301 Panasonic 13.
I 2 C Bus Controller I 2 C In terf ace Se tup Ex amples Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 302 Panasonic 13.6.2 Setting Up a T r ansition from Slave Receiver to Slave T ransmitter This e xample demonstrates ho w to set up a data transfer when changing from slav e recei ver to sla ve transmitter .
I 2 C Bus Controller I 2 C Interfac e Setup Example s MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 303 Panasonic 13.6.2.3 Setting Up the Second I nterrupt The master sends an A CK = 0 signal, so the m icrocontroller must send the ne xt data byte.
I 2 C Bus Controller I 2 C Bu s Inte rfac e Regis ters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 304 Panasonic 13.7 I 2 C Bus Int erface R egister s All registers in I 2 C bloo k cannot be wri tten by byte ( by wo rd onl y).
I 2 C Bus Controller I 2 C Bus Interface Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 305 Panasonic I2CDREC: I 2 C Recepti on Data Register x’00 7E42’ The I2CDREC re gis ter contains the status bits for monitoring the d evice and the reception data.
I 2 C Bus Controller I 2 C Bu s Inte rfac e Regis ters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 306 Panasonic I2CCLK: I 2 C Cloc k Control Register x’007E4 6’ T o conform to the specification, the clock signal must be between 0 and 100 kHz.
H Counter Description MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 307 Panasonic 14 H Counter 14.1 De scripti on The MN102H75K/85K contain s two H coun ter circuits that can be u sed to count the HSYNC signal.
H Counter H Counter Operation Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 308 Panasonic Figure 14-3 shows the input timing for the count sou rce and reset signals. Nev er input a count so urce signal in less th an 2 45 ns (t 1 ) af ter the reset signal input.
H Counter H Counter Operation MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 309 Panasonic The H counter counts the HSYNC signal for the interv al set in.
H Counter H Counter Control Re gisters Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 310 Panasonic 14.4 H Counter Contr ol Register s All registers in H Counter block cannot be written by by te (by word only). Read by byte is po ssibl e .
H Counter H Counter Control Registers MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 311 Panasonic HCD0: H Counter D ata Re gister 0 x’00 7EB4 ’ HCD[90:00]: Count from HI0 source signal This f ield stor es the HI0 clock source cou n t.
Register Map Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 312 Panasonic Appendix A Register Map T able A-1 Re gister Map: x ’007E00’ to x ’007FFF’ (Registers in this area cannot be written b y by te onl y b y word .
Register Map MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 313 Panasonic T able A- 2 Registe r Map: x’00F C00’ to x’00FD FF’ 20 MSBs 4 LSBs Desc.
Register Map Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 314 Panasonic T able A-3 Re gister Map: x ’00FE00’ to x ’00FFFF ’ 20 MSBs 4 LSBs Description.
Register Map MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 315 Panasonic.
MN102HF75K Flash EEPRO M Version Description Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 316 Panasonic Appendix B MN102HF 75K Flash EEPR OM V er sion B.1 Descri ption The MN102HF75K and MN102HF85K are electrically pro grammable, 256- kilobyte f l ash R OM v ersions of the MN102 H75K and MN102H85 K.
MN102HF75K Flash EEPROM Ve rsion Benefits MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 317 Panasonic B.
MN102HF75K Flash EEPRO M Version Using the PROM Writer Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 318 Panasonic Check th e follo wing web page of our microcomputer di visio n for the writer matching info rmation.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 319 Panasonic B.
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 320 Panasonic B.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 321 Panasonic B.4.2 Circuit R equirements for the T arget Boa rd ■ Duri ng pro gram ming , the s e rial w rite r s upp lie s V PP to the microcon troller .
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 322 Panasonic B.4.3 Microcont roller Hardware Used in O nboard Serial Pro- grammin g B.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 323 Panasonic B.4.4 Microcont roller Memo ry Map Used During On board Serial Progra mming B.
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 324 Panasonic ■ Branch in struct.
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 325 Panasonic B.4.6 Setting Up the Onbo ard Serial Pr ogramming Mod e T o enter s erial pro gramming m ode, the micro controller mu st be i n write mo de.
MN102HF75K Flash EEPRO M Version Using the O nboard Se rial Pro gramming Mo de Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 326 Panasonic ■ Start routin e f or the load pr ogram Condi tions: 1. After the load program initiates a res e t start, SB D must be low and SBT high .
MN102HF75K Flash EEPROM Ve rsion Using the Onboard Serial Programming M ode MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 327 Panasonic B.
MN102HF75K Flash EEPRO M Version Reprogram ming Flow Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 328 Panasonic B.5 Repr ogramming Flow Figur e B-12 sho ws the flo w for reprog ramming (erasing and programming) t he flash memory .
page Line defini- Description of Changes tion Former version New version Cover Pub number C 22385-010E 22385-011E Colophon C September, 2001 1st Edition October, 2001 1st Edition 1st Printing Sales office C Latest version MN102H75K/F75K/85K/F85K LSI User's Manual Description Record of Changes (Ver.
MN102H75K/F75K/85K/F85K LSI User’s Manual Modified Points From MN102H75K/F75K To MN102H75K/F75K/85K/F85K MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 1 Panasonic page Before Modify page Af ter Modify P16 This manual is intended for assembly-lan guage programming engineers.
Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 2 Panasonic P30 1.6 Pin De scriptions 1.6.1 MN102H85K Pin Description Notes : 1. Pins marked with an as terisk (*) are N-channel, open-drain pins. 2. Pin 25 is V DD in the MN102H85K and V PP in the MN102HF85K.
MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 3 Panasonic P33 The MN102H75K contains an inter nal PLL circ uit. T o use this circuit, you must connect it to an external (lag-lead) f ilter . P34 The MN102 H75K/85K contains an i nternal PLL cir cuit.
Panasonic Semiconductor Development Company MN102H75K /F75K/85K /F85K LSI Us er Manual 4 Panasonic P77 The MN102H75K contains four 8-bit timers t hat can serve as inte rv al timers, event timer/counters, cl ock generators ( di vide-by-2 output of the underflow), reference clocks for the serial interfaces, or start timers for A/D con versions.
MN102H75 K /F75K/85K /F85K LSI Us er Manua l Panaso nic Se miconduc tor Developm ent C ompany 5 Panasonic P307 The MN102H75K contains two H counter cir cuits that can b e used to count the HSYNC signal.
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Issued by Matsushita Electric Industrial Co., Ltd. Matsushita E lectric I ndustrial Co., Ltd. MN10 2H75 K/F75K /85K /F85K LSI U ser ’s M anual October ,2001 1st E d ition 1 st Printi ng.
Semiconductor Company, Matsushita Electric Industrial Co., Ltd. Nagaokakyo, Kyoto, 617-8520 Japan Tel: (075) 951-8151 http://www.panasonic.co.jp/semicon/ SALES OFFICES ■ NORTH AMERICA ● U.S.A. Sales Office: Panasonic Industrial Company [PIC] • New Jersey Office: Two Panasonic Way Secaucus, New Jersey 07094 U.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Lucent Technologies MN102F85K c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Lucent Technologies MN102F85K - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Lucent Technologies MN102F85K, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Lucent Technologies MN102F85K va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Lucent Technologies MN102F85K, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Lucent Technologies MN102F85K.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Lucent Technologies MN102F85K. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Lucent Technologies MN102F85K ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
