Manuel d'utilisation / d'entretien du produit AD9912 du fabricant Analog Devices
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1 GSPS Direct Digi tal Synthesizer with 14 - Bit DAC AD9912 Rev. D Info rmation fu rnished by A nalog Devic es is believed to be ac curate an d reliable . Ho wev er , no respo nsibility is assumed by An alog Devices fo r its use, nor for any infringements of p atents or other rights of third parties that may resu lt from its use .
AD9912 Rev. D | Page 2 of 40 T ABLE OF CONTENTS Fea tures .............................................................................................. 1 A pplica tions .............................................................................
AD9912 Rev. D | P age 3 of 40 SPECIFICA TIONS DC SPE CIFICATI ONS A VDD = 1.8 V ± 5% , A V DD3 = 3.3 V ± 5%, DVDD = 1.8 V ± 5%, DVDD_I/O = 3.3 V ± 5% , A VSS = 0 V , D VS S = 0 V , u nless o therwise noted. Tabl e 1 . Paramet er Min Ty p Max Uni t T est Conditio ns/ Co mments SUPPL Y VOL T AGE DVDD_I/O (Pin 1) 3.
AD9912 Rev. D | P age 4 of 40 Paramet er Min Ty p Max Uni t T est Conditio ns/ Co mments SYSTEM CLOCK INPU T Syste m clock in puts sho uld alwa ys be ac - coupl ed (b oth s ingl e - ended and diff erentia l) SYSCLK PLL Bypas sed In put Capaci tance 1.
AD9912 Rev. D | P age 5 of 40 AC SPECIFI CATIONS f S = 1 GHz, DA C R SET = 10 k Ω , u nless otherwis e noted . P ower suppl y pins within the range sp ecif ied in the DC Spec ifications se ctio n.
AD9912 Rev. D | P age 6 of 40 Paramet er M in Typ Max Un it Test Conditions/Comments CMOS Output Driver (AVDD3/Pi n 37) @ 1. 8 V Freq uency Ra nge 0.008 40 MHz See Figur e 28 f or maximum togg le rate Duty Cyc le 45 55 65 % With 20 pF load and up to 40 MHz Rise Time /Fall Ti me (20% to 80% ) 5 6.
AD9912 Rev. D | P age 7 of 40 ABSOLUTE MAXIMUM RA T INGS Table 3. Paramet er Rating Analog Su pply V oltag e (A VDD) 2 V Digital Su pply Voltag e (DVDD ) 2 V Digital I/ O Supply Vo ltage (DVDD_I/O) 3.6 V DA C Supply Voltage ( A VDD3 Pin s ) 3.6 V Maximu m Digital I nput V oltage −0.
AD9912 Rev. D | P age 8 of 40 PIN CONFIGURA TION AND FUNCTION DE SCRIPTI ONS PIN 1 INDI C A T OR 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 NC NC A V DD NC NC NC A V DD A V DD A V DD A V DD SYSCL.
AD9912 Rev. D | P age 9 of 40 P i n N o. Input / Output P i n Ty p e Mnemonic Descriptio n 32 I 1.8 V CMO S CLK MODE SEL Clock Mode Selec t. Set to GND whe n connecting a cr ystal to the system clock inp ut (P in 27 and P in 28). P ull up to 1.8 V whe n using ei ther an oscillator or an external cloc k sourc e .
AD9912 Rev. D | P age 10 of 40 TYPICAL PERFORMA NCE CHARACTERIST ICS AV D D , AV D D 3 , a n d D VDD a t nominal supp ly vol tage; DAC R SET = 10 k Ω, unless otherwis e noted. See Fig ure 26 for 1 GHz re fe re nce pha s e n oi se used for gen era ting these p lo ts .
AD9912 Rev. D | P age 11 of 40 06763-009 19.85 19. 95 20. 05 20.15 20.25 20. 35 FREQUENCY (MH z) 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 SI G NAL P O W E R ( d Bm) 20.1M Hz –95dBc 500kHz 300Hz 1kHz CARRIE R: SF DR: FRE Q .
AD9912 Rev. D | P age 12 of 40 06763-015 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –100 –110 –120 –130 –140 –150 PHASE N OISE (d Bc/Hz) 800MHz 600MHz RMS JI TT ER (100Hz T O 100M Hz) : 600MHz: 800MHz: 585fs 406fs Figure 15 .
AD9912 Rev. D | P age 13 of 40 06763-051 100 1k 10k 100k 1M 10M 100M FREQUENCY OFFSET (Hz) –125 –115 –135 –145 –155 –165 –175 PHASE N OISE (d Bc/Hz) RMS JI TT ER (100Hz T O 20M Hz) : 50MHz: 200MHz: 400MHz: 62fs 37fs 31fs 200MHz 400MHz 50MHz Figure 21 .
AD9912 Rev. D | P age 14 of 40 06763-021 0 200 400 600 800 FREQUENCY (MH z) 650 600 550 500 450 AMPLITUDE (mV) NOM S KE W 25°C, 1. 8V S UP P L Y WORST CASE (SLOW SKEW 90°C, 1.7V SUPPLY) Figure 27 . HSTL Out pu t Driver Single - En ded Peak -to- Pe ak Amplitud e vs.
AD9912 Rev. D | P age 15 of 40 INPUT/OUTPUT TER MINA TION RECOMM EN DA TIONS DOW NST REAM DEVI CE (H IGH-Z) AD9912 1.8V HST L OUT PUT 100 Ω 06763-027 0.01µ F 0.01µ F Figure 33 . AC - Coupled HST L Output Driver DOW NST REAM DEVI CE (H IGH-Z) AD9912 1.
AD9912 Rev. D | P age 16 of 40 THEOR Y OF OPERA TION 06763-031 DDS/ DAC FRE QUENCY TUNI NG W O RD ÷S 2× DIGI TAL SY NTHES IS CORE CONT ROL LOGIC LOW NOIS E CLO CK MU LTIPLIER AMP SYSCLK PORT EXT ERN.
AD9912 Rev. D | P age 17 of 40 06763-032 DAC (14-BI T) AN GLE TO AMPL IT UDE CONVE RSI ON 14 19 19 48 48 48 14 PHASE OFFSET Q D 48-BIT ACCUMUL ATO R FREQ UENCY TUNI NG W O RD (FTW) f S DAC_RSET DAC_OUT DAC_OUT B DAC I-S E T REGISTERS AN D LOGIC Figure 40 .
AD9912 Rev. D | P age 18 of 40 PRI MARY SI GNAL FILTER RESPONSE SIN(x)/x ENVELOPE SPURS IMAGE 0 IMAGE 1 IMAGE 2 IMAGE 3 IMAGE 4 0 –20 –40 –60 –80 –100 MAG NIT UDE (d B) f s /2 f s 3 f s /2 2 f s 5 f s /2 f BASE BAND 06763-034 Figure 42 . DAC Spectrum vs.
AD9912 Rev. D | P age 19 of 40 SYSC LK INPUTS Funct i onal D escription A n exter nal ti me base connects to the AD9912 at the SY SCLK pins t o genera te the in ternal hig h frequenc y system clock (f S ).
AD9912 Rev. D | P age 20 of 40 SYSCLK PLL Multiplier When the SY SCLK PLL multiplier path is employ ed, the freq uency a pp lied to t he S Y SCLK inp ut pin s m ust be limi ted so as n ot t o ex ceed the maxi mu m in pu t freq uency of the S Y SCLK PLL p hase detecto r .
AD9912 Rev. D | P age 21 of 40 N ote t ha t the SY SCLK PLL b ypassed a nd S Y SCLK P LL ena bl ed input pat hs a re in te rna lly biase d to a d c level of ~1 V . Care should be taken to ensure that an y external connections do not disturb the dc bias be cause this may sign ifica ntl y degra de perform ance.
AD9912 Rev. D | P age 22 of 40 Although the worst spurs tend to be harmonic in origin , the fact that the D AC is part of a sampled system results in the poss ibility of sp urs ap pearing in the outp ut spec tru m that are not harmoni - cally r elated to t he fundamen tal.
AD9912 Rev. D | P age 23 of 40 THERMAL PERFOR MANCE Table 7 . Thermal Paramete rs Symbo l Therm al Char acterist ic Us ing a JE DEC51 - 7 Plus JE DEC51 - 5 2S 2P T est B oard Valu e Unit θ JA Ju nc t i on - to - ambient t hermal r esistance , 0.0 m/s ec a ir flow per JE DEC JESD51 - 2 (still ai r) 25.
AD9912 Rev. D | P age 24 of 40 POWER-UP POWER - ON RESET On initial power - up, t h e AD991 2 in terna lly genera tes a 75 ns RESET pulse. The puls e is initiated when b oth o f the following two condition s are met: • The 3.3 V supp ly is gr eater than 2.
AD9912 Rev. D | P age 25 of 40 POWER SUPPL Y PAR TITI ONING The AD9912 feat ures m ultiple pow er supp lies, and their power consum ption varies with its configuration. This s ection covers which power supp lies can be grouped together and how the powe r cons u mpti on of each blo ck v ar ies with f requency .
AD9912 Rev. D | P age 26 of 40 SERIAL CONTROL PORT The AD9912 se rial contr ol port is a flexible, synchro nous, serial co m m unications port that allows an easy interface with many indus tr y - standard microcon trollers and micr op rocessors.
AD9912 Rev. D | P age 27 of 40 Read If the instr ucti on wor d is for a rea d operation (I15 = 1), the next N × 8 SCLK cy cles c lock ou t the da ta from t he address specified in the instruction word, where N is 1, 2, 3, or 4, as deter mined by [ W1:W0 ] .
AD9912 Rev. D | P age 28 of 40 Table 10 . Serial Control Port, 16 - Bit Instr uction Word , MSB F irst MSB LS B I15 I14 I13 I 12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 R/ W W1 W0 A12 A11 A10 A9 A8 A7 A.
AD9912 Rev. D | P age 29 of 40 06763-048 CSB SCL K SDI O t H IGH t LOW t CLK t S t DS t DH t H BIT N BIT N + 1 Figure 56 . Serial Co ntrol Port Timing — Write Table 11 .
AD9912 Rev. D | P age 30 of 40 I/O REGISTER MAP All address and bi t location s that ar e left blank in Ta b l e 12 ar e unu sed . Table 12 . Addr (Hex) Type 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) Serial port con figuration and pa rt i dentification 0x0000 Serial c onfi g.
AD9912 Rev. D | P age 31 of 40 Addr (Hex) Type 1 Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default (Hex) Calibration (user - acc essibl e t rim) 0x0400 to 0x040A Reserv ed 0x00 0x040B DAC f.
AD9912 Rev. D | P age 32 of 40 I/O REGISTER DESC RIP TION S SERI AL PORT C ONFIGUR ATION (R EG IS TER 0x 0000 TO REG IST ER 0x 0005) Regist er 0x0000 —Serial P ort Config urat ion Table 13 . Bits B it Name Descript ion [7:4] These b its ar e the mirror imag e of Bit s[3:0 ].
AD9912 Rev. D | P age 33 of 40 Regist er 0x0011 — Reserved Regist er 0x0012 — Res et ( Autoc learing) To reset t he en tir e chi p , the user c an use the (non - auto cl eari ng) soft r es et bit in Register 0x0000. Table 17 . Bits B it Name Descript ion 0 DDS r eset R eset of the d irect d igital s ynt hes is block.
AD9912 Rev. D | P age 34 of 40 CMOS O UTPUT DIVIDE R (S -DIVIDER) (REG ISTER 0x 0100 TO REG ISTER 0x 0106) Regist er 0x 0100 to Registe r 0x0103 — Reserv ed Regist er 0x0104 —S- Di vider Table 21 . Bits B it Name Descript ion [7:0] S-d ivider CMOS out put divider .
AD9912 Rev. D | P age 35 of 40 Regist er 0x01A9 — FTW0 ( Fr equen cy T unin g W ord) (Con ti nued) Table 27 . Bit s Bit Name Desc riptio n [31:24] FT W0 These r egist ers conta in the FT W (fr equency tu ning w ord) f or the D DS. The FT W det ermin es the ratio of the A D9912 outpu t frequ ency to it s DA C sys tem c lock.
AD9912 Rev. D | P age 36 of 40 DOUBLER AND O UTPUT D RIVER S (RE G ISTE R 0x 0200 TO REG IS TE R 0x 0201) Regist er 0x0200 — HSTL Driver Table 32 . Bits B it Name Descript ion 4 OPOL Out put pola rity . Sett ing th is bit inv er ts the HS TL driv er output po larity .
AD9912 Rev. D | P age 37 of 40 Regist er 0x0503 — Sp ur A (C ontin ued) Table 38 . Bit s Bit Na me Descr iptio n [7:0] Spur A phase Linear o ffs et fo r Spu r B phas e. Regist er 0x0504 — Sp ur A (C ontin ued) Table 39 . Bits B it Name Descript ion [8] Sp ur A p h as e Linear of fs et for S pur A phase .
AD9912 Rev. D | P age 38 of 40 OUTLINE DIMENSIO NS PIN 1 INDI C A T OR T OP VIEW 8. 75 BSC SQ 9.00 BSC SQ 1 64 16 17 49 48 32 33 0.50 0.40 0.30 0.50 BS C 0. 20 RE F 12° M AX 0.80 M AX 0.65 T Y P 1.00 0.85 0.80 7.50 REF 0.05 M AX 0.02 NO M 0.60 M AX 0.
AD9912 Rev. D | P age 39 of 40 ORDERING GUIDE Model T emper atu re Rang e Package De scription P ackage Op tion AD9912A B C PZ 1 , 2 −40°C to +85° C 64 - Lea d Lea d F rame Ch ip Scal e P ackage [.
AD9912 Rev. D | P age 40 of 40 NOTES © 2007 – 2009 Anal og De vice s, Inc. All rights reserved. Tradema rks and registe red trad emarks are the pro perty of their resp ective o wners.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Analog Devices AD9912 c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Analog Devices AD9912 - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Analog Devices AD9912, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Analog Devices AD9912 va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Analog Devices AD9912, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Analog Devices AD9912.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Analog Devices AD9912. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Analog Devices AD9912 ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
