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inter iAPX 432 Interface Processor Architecture Reference Manual 171863-001.
INTEL iAPX 432 INTERFACE P~OR Manual Orner Number 171863-001 Release 1.1 Oamponents Cb~right (C) 1981, Intel Corporation Intel Corporation, 3065 Bowers Avenue, Santa Clara, California 95051.
Additional oopies of this manual or other Intel literature may be obtained from: Literature Department Intel Corporation 3065 BCMers Avenue Santa Clara, CA 95051 The information in this document is subject to change without notice.
PREFACE Understanding any complex comp.lting system, such as the Intel iAPX 432, requires the assimilation of a great deal of technical information. Before reading this manual on the architecture of the 432 Interface Processor, the reader should have conmand of the general 432 concepts.
TABLE OF CCNl'ENI'S TITLE 1. KE'Y' crncEP'l'S ...•.....•.•..•....••.....•••.•••••••••.
3. ~ ••••••••••••••••••••••••••••••••••••••••••••••••••••• 3-1. WindCM AttribJtes 3-2. 3-3. 3-4. 3-5. Wioo~ Status ••••••••••••••.
APPENDICES APPENDICES A. SYS'm1 ~ S~ ••••••••••••••••••••••••••••••••••••••• A-I. A-2. A-3. Context Objects Process Objects Processor Objects . ........................
TITLE 1-1. 2-1. 2-2. 2-3. 3-1. B-1. B-2. B-3. D-l. E-l. TABLES PAGE Printer Example Legend ••••••••••••••••••••••••••••••••••• 1-1.
TITLE 1-1. 1-2. 1-3. 1-4. 1-5. 1-6. 1-7. 1-8. 3-1. 3-2. 3-3. 3-4. 3-5. 3-6. 4-1. 4-2. 4-3. 4-4. 4-5. 4-6. 6-1. 0-1. E-l. F-l. F-2. F-3. F-4. F-5. F-6 viii FIGURES 432 System and Peripheral Subsystems .
CHAPTER 1 KEY CCNCEPTS This chapter introduces the iAPX 432 Interface Processor (IP). The first four sections cover the IP as it is used normally in connection with inIXlt/output operations.
iAPX 432 Interface Processor Architecture Reference Manual 432 Memory 432 System/Peripheral Subsystem Boundary Figure 1-1 432 System and Peripheral SljbSystems 1-2.
KEY CCHE?TS In a 432-based system, the bulk of processing required to support inplt/out];Xlt operations is delegated to Peripheral Subsystems; this includes device control, timing, interrupt handling .
iAPX 432 Interface Processor Architecture Reference Manual It is ~rtant to note that both the window and function facilities utilize and strictly enforce the standard 432 addressing and protection systems. Thus, a window provides protected access to an object, and a function provides a E.
432 System o Procesa O. Process running on GDP needs I/O service 1. Process formulates message describing service, sends it to device task 2. Device task receives service order, interprets it Service Order Messaqe Service Reply Message KEY CONCEP'IS Peripheral Subayatem ------------------- Device Task (:;' -V 3.
1-6 iAPX 432 Interface Processor Architecture Reference Manual 432 System -------Peripheral Subsystem ------------ Figure 1-3 Peripheral Subsystem Interface Device Task f.
1- 3. PERIPHERAL SUBSYS'lm INTERFACE A Peripheral Subsystem interface is a collection of hardware and software that acts as an ad.aptor which enables message-based oammunication between a process in the 432 system and a device task in a Peripheral Subsystem.
432 Memory 1-8 iAPX 432 Interface Processor Architecture Reference Manual 432 System "tt H o (1 en UI UI o H I 3: (1) :I o H '< H ::s rt en H (1 o ::s ::s (1) n rt --------.~ ~~~--------- Peripheral Subsystem "tt co t1 Optional DMA ontrolle ~.
KEY COOCEPTS Continuing the notion of the logical I/O processor, the Attached Processor fetches instructions, provides the instructions needed to alter the flow of execution, and performs arithmetic, logic and data transfer operations within the Peripheral Subsystem.
iAPx 432 Interface Processor Architecture Reference Manual To sunmar ize, the Attached Processor and the Interface Processor interact with each other by means of address references generated by the AP and interrupts generated by the IP.
KEY CXNCEP'IS The Interface Processor provides a process addressing environment within the 432 system which supports the operation of the I/O controller in the 432 system. This environment is embodied as a set of system objects that ·"are used and manipulated by the IP.
iAPX 432 Interface Processor Architecture Reference Manual -f-Peripheral Subsystem Memory space---"I ~ 432 System Memory Space --. Local Memory Addresses Interface Processor ( IP window maps a subrange of peripheral subsystem addresses onto an object in 432 memory .
KEY CCNCEPTS Since a windCM is referenced like memory, any individual transfer may be between an obj ect and PS memory, an object and a PS processor register, or an object and an I/O device. The latter may be appealing from the standpoint of "efficiency," rut it should be used with caution.
iAPX 432 Interface Processor Architecture Reference Manual The IP's function set permits the I/O controller to: o alter windows; o exchange messages with GOP processes via the standard 432 interprocess communication facility; o manitulate objects.
KEY CONCEPTS _ Peripheral Sub8 Y 8tem_l_ Peripheral Subsystem Interface --lI-1 0+- 432 < Port Object> (1) System -. Action Data Location Input --- ...... ~. I ~.~-----output I Message 0 0 ~ ____ J~--"··~_B_u_~_~_e_r_~··IIf-----1·"O""4:l------I"·1(M~~~:~!)I""-----I··O _____ C_o_p.
iAPx 432 Interface Processor Architecture Reference Manual I/O EXAMPLE To illustrate the operation of the 432 I/O model more specifically, this section provides a simple example which shows how line printer output might be implemented. Of course, the example describes only one of many possible awroaches that might be taken.
CDP Proeeaa KEY CONCEPTS 432 Memory Peripheral subayatem Memory 432 'Syat_---- --- ____ .eripheral Subayatelll Intertace-----I_ .eripheral .ubayaUIII ____ _ Figure 1-7 Printer EKarnple 'rint.
iAPX 432 Interface Processor Architecture Reference Manual Item SEND,/R:ErnIVE .Table 1-1 Pr inter Example Legend Description Object (message) descr ibing pr int operation fram requesting process's point of view (see figure 1-8). 432 communications port assigned by convention to queue print objects.
KEY <XNCEPTS Figure 1-8 shows hOil the message sent by the GOP process might be organized. It oonsists of two parts, an object reference part and a text part. The object references are for the text part of the object, the 432 port at which the process will wait for the message to be returned, arrl a reference for the process itself (GOP or IP).
iAPX 432 Interface Processor Architecture Reference Manual Text~ Print Data CI Object References".,.;; __ Print Status Text Command Figure 1-8 Example Print Object 1-20.
KEY CONCEPTS Printer Server Task Perspective The printer server task may be viewed as a "front end" to the pr inter task which is responsible for translating the message sent by the GOP process into the form expected by the printer task. The printer server loops through the following steps: 1.
iAPX 432 Interface Processor Architecture Reference Manual 1-5. SUPPLEMENTARY INTERFACE ProcESSOR FACILITIES The preceding sections have described the Interface Processor as it is used most of the time. The IP provides two additional capabilities which are typically used less frequently, often only in exceptional circumstances.
The IP (like a GOP) requires two register interconnect space to be defined for any system: o the processor ID register (interconnect o the interprocessor communication (interconnect address 2) KEY CON.
.
rnAPTER 2 CBJOCTS AND OPERA'lORS This chapter describes the 432 environment as it appears to the I/O controller software. It :r;x:>ints out what the I/O controller can, and cannot, do in the 432 system. The first section broadly compares the facilities provided by the Interface Processor to those available on the General Data Processor.
iAPX 432 Interface Processor Architecture Reference Manual To permit the I/O controller to function in the 432 system as well as in the Peripheral Subsystem, the IP provides an environment, and operators that it executes within this environment.
CI3JECrS AND OPERATORS Table 2-1 IP/GOP System Object Comparison Object Processor Object Process Obj ect Context Object Operand Stack Instruction Segment Object Table IkInain Port Carrier Storage Reso.
iAPX 432 Interface Processor Architecture Refer.ence Manual Through its windows, an IP provides the basic ability to read and wr i te the contents of objects composed of data segments. However, using its function request facility an IP can manipulate an access descriptor which references an object.
CBJECrS AND OPERATORS Table 2-2 IP/GDP Operator Comparison (Part 1 of 2) Qe.erator WINIXJW DEFINITIOO OPERATOR Alter Map and Select Data Segment AOCESS DESCRIP'IOR M:NEMENl' OPERATORS Copy A.
2-6 iAPX 432 Interface Processor Architecture Reference Manual Table 2-2 continued IP/GOP Operator Canparison (Part 2 of 2) ProcESS Cl:H1UNICATICN OPERA'IORS Send Receive Conditional Send Conditi.
CBJECl'S AND OPERATORS 2- 2. CBJECl' ADDRESSING AND GLCBAL SIDRAGE MANAGEMENT Object addressing on the IP follows the same three level sequence as on a GOP.
iAPX 432 Interface Processor Architecture Reference Manual 2-4. FACILITIES FUR ASYNCHRCNOUS CDMJNlCATICN The IP offers the same set of operators for asynchronous interprocess communication as does a GOP, with the excey;>tion that the DEIAY operator ls not implemented.
0BJECrS AND OPERATORS Contained in each obj ect ' s storage descr iptor is an I/O lock which is applied by the IP when a window is opened on the object. This lock serves 'bNo purposes: first it guarantees that only one IP window can be opened on a particular 432 object at a time; second it prevents IIDvement of the object (e.
iAPX 432 Interface Processor Architecture Reference Manual Direct vs. Indirect Accessibility If a copy of an access descriptor for an object is in one of t.
CEJECrS AND OPERATORS Table 2-3 Direct/lndirect Accessibility Viewpoint of IP/GDP in 432 System . Directly Accessible 432 Infor.mation o access descriptors All access descriptors in the four Entry Access Segments. o data All objects of type data segment referenced b¥ access descriptors in the four Entry Access Segments.
iAPx 432 Interface Processor Architecture Reference Manual Object Selectors An object selector identifies an object by specifying an access descriptor contained in one of the four entry access segments. The object selector oonsists of a double byte quantity composed of two fields: 1.
The Interface Processor windCM mechanism provides the Per ipheral Subsystem with protected access to the contents of objects located in the 432 system. There are five windows, labeled 0-4. Each windCM can be used to access one (single segment) object.
iAPX 432 Interface Processor Architecture Reference Manual 3-1. WINJX)W ATl'RIBUl'ES Each window has a set of attributes which define its state at a given rnanent; these are sumnarized in table 3-1. The IP sets the attributes of all five windows when it performs processor qualification.
Table 3-1 Window Attribute Summary Attribute Description Window Status Window is open/closed/faulted Subr ange Base Address Start of windowed subr ange in the PS Subrange Size Length of windowed subra.
iAPX 432 Interface Processor. Architecture Reference Manual SUBRANGE BASE AIDRESS AND SUBRANGE SIZE A windCM's subrange is defined by a subrange base address and a subrange size, in bytes. The subra~ is the contiguous set of Peripheral SUbsystem memory addresses that are mapped by the windCM.
WINOOWS <l3JECI' REFERENCE An open window's object reference begins as an object selector and is converted by the IP into an access descriptor for the windowed 432 object.
iAPX 432 Interface Processor Architecture Reference Manual DIRECl'ICN The direction attribute specifies whether the windowed object may be read, written, both read and written, or neither read nor written. When the window is opened the IP checks the requested direction attribute with the access rights granted by the object reference.
00 meaning for windows 2-4, which suWOrt random transfers to 432 system memory only; the random transfer mode is described in section 3-2. Attempting to set the transfer mode of windows 2-4 will cause a fault.
3-8 iAPX 432 Interface Processor Architecture Reference Manual -64K-:!::: I~~! ,::" -36K- )}js';ilirange of windo,:" opened iiiiii!i!! wl.
WINOOWS 3- 2. W1NIXM OPERATI(lJ This section descr ibes the IP' s response to an address reference that falls into the windowed subrange of an open windGl.
%P 64K Byt Rang e e Access iAPX 432 Interface Processor Architecture Reference Manual PS ADDRESS SPACE 432 ADDRESS SPACE -r- --.-.----- , ~ SOBRANGE LENGTH .
MAPPED IP WINDOW 432 OBJECT 0 ----0 ----- LJ /// 0 ----· ------- O ----c/// ---- //// LJ ", ----0 ........ -- WINDOW - OBJECT WINDOW -: OBJECT WINDOW a REFINEMENT OBJECT oc: WINDOW WINOOW> RE.
LAPX 432 Interface Processor Architecture Reference Manual 3- 3. RANOOM mOE DATA TRANSFER Given that an IP address reference has passed the consistency checks, the IP finishes the Peripheral Subsystem bus cycle just as a menory oomponent would, accepting data from the bus in a wr i te operation, and placing data on the bus in a read operation.
41 03 ... .... 4096 Windot'-1ed Subrange Legend -.., ...... 3 1 2 - - - - Reference Sequence: - - - - - - Byte disP1acement~ I - - - Windowed Object G) (7) (6) (5) (4 ) ( 3) (2) (1) (0) <Y G) Subrange Address Referenced: 4'97 4102 Reference Operation: 4'99 Read Byte 3 Write Byte Read Double-byte Object Byte Accessed (disp.
iAPX 432 Interface Processor Architecture Reference Manual 3-4. BIOCK MJDE MTA TRANSFER Window 0 can be opened in random m::Xie or in block mode. Block mode allows the Peripheral Subsystem to take advantage of software instructions (e.g. iAPx 86 str:i.
WINOOWS BLOCK MODE CCNSIS'lENCY CHEr!K Since the byte count and base displacement effectively predefine the transfer from the perspective of the 432 object, the IP can perform most of the required consistency checks when the window is opened. The only checks made during a transfer are direction and byte count.
iAPX 432 Interface Processor Architecture Reference Manual Canpleting a block node write transfer which is shorter than the byte count is a two-step process. First, the AP must issue an ALTER MAP AND SELECl' DATA SEGmNI' function with the entry state operand to "force termination" on window o.
WINOOWS BLOCK MODE ADDRESS ING As mentioned earlier, in a block mode transfer the IP determines the displacement of a transf€r inbo the windowed object b¥ means of its on-chip displacement counter. Unlike random mode, then, the object displacement is independent of the subrange displacement.
iAPx 432 Interface Processor Architecture Reference Manual ----------- 41 03 Byte diSPlacement~ (7) (6) 3-18 4 096 Windowed Subrange 3 2 1 - - - - - - Windowed Object (5) (4) (3) (2) T 3 (1) ! (0) - (Base Displacement) Legend <D G) G) Reference Sequence: Subrange Address Referenced: Reference Operation: Object Byte Accessed (disp.
4096 Legend ..... ----,," Windowed Subrange Reference Sequence: " " ,,'- , , Sub range Address Referenced: Reference Operation: Object Byte Accessed (disp.
iAPx 432 Interface Processor Architecture Reference Manual 3-5. INTE~ TRANSFERS Window 1 may be opened onto either the 432 memory space or the 432 processor-memory interconnect space.
OiAPTER 4 FONcrIOOS This chapter describes the common facility that supports the execution of all Interface Processor functions. The first section shows hCM windCM 4 is used to provide access to the facility. The next section explains how a function is requested by writing operands and an o~""Ode through the windCM.
4-2 iAPX 432 Interface Processor Architecture Reference Manual Operands (reserved) Opcode Function State Process Selection Index Processor Data Segment Figure 4-1 Function Request Area 9 8 7 6.
IP WINDOWS 432 SYSTEM 0--- --_~ IP __ ......... PROCESSOR DATA SEGMENT 0 ------0 ---- ---- 0 ------0 -_ .... ---- 0 ------0 ...--- ---- 0 --- ---0 fI ___ ____ B D DATA SEGMENTS FUNCTICNS IP WINDOWS 43.
iAPX 432 Interface Processor Architecture Reference Manual 4- 2. FUNCrICN REC.UFSTS The performance of a function may be considered fram the AP point of view as a sequence of three phases, as shown in figure 4-3. The IP controller, running on the AP, performs the first phase, requesting the execution of a function.
• • • Read function state Write operands Write opcode I " Perform other processing,' ---------. I I _____ __ ~ Interrupt • from IP ~ - - ,.
iAPX 432 Interface Processor Architecture Reference Manual FUNCl'IOO OPERANDS An Interface Processor function may require fran zero to seven <DubIe-byte operands. The IP controller specifies a function's operands by writing values into locations of the operands field in the function request area.
FONcrICNS I I 15 , Short Ordinal ~~ ________ ~y _______ -J' l~-------------(16-bit unsigned integer) 15 , I : : : i : : : : : : : : ! : :] , v,------I Bit Field 15 l .
~ 432 Interface Processor Architecture Reference Manual 15 , p0000000000001Il~ Object Selector Operand d ° fO Entere Access Segment Identl. l.er - - - --- - - - - - - - - - -, Access Descriptor.
FUNcrIONS 4- 3. FUNcrICN EXOCUTICN The IP per forms the actual execution of a function independent of the IP controller. Therefore the IP controller (an Attached Processor with associated IP control software) is free do other work after it has requested execution of a function (except that it must refrain from requesting a second function).
4-10 iAPX 432 Interface Processor Architecture Reference Manual Qualify Selected Process Decode Opcode Perform operation Update destinations Update Return-value Update function completion state Gener~.
FUNCl'IONS Successful execution of a function typically causes the alteration of a destination operand (that is, an actual operand~ the operands field of the function request area is never changed by function execution). In addition, or alternatively, same functions produce a return-value.
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• 'it' n CHAPTER 5 PHYSICAL REEKRENCE MJOE The preceding chapters of this manual have Dmplicitly described the Interface Processor's logical reference node, its mrmal nnde of oper ation.
iAPX 432 Interface Processor Architecture Reference Manual 5-2. PHYSICAL REFERENCE mDE ADDRESSING In physical reference mode the object reference attribute of a window is replaced b¥ a 24-bit segment base address. Upon recognition of a subrange address reference the IP determines the transfer displacement as in logical reference node.
CHAPTER 6 FAULTS . This chapter describes IP faults, exceptional corrlitions which can occur as the IP performs functions. In general, the IP fault philosophy follows that of the GOP: the processor detects and contains faults so they do not affect other processes or processors in the 432 system.
iAPx 432 Interface Processor Architecture Reference Manual The IP records fault information in various areas of IP process and processor objects (refer to Appendix A for detailed description of these fault information areas).
FAULTS· Context-Level Faults Context-level faults are the least severe of the IP logical node faults. A context-level fault arises fran exceptions which can be confined to the context in which the IP is operating. The IP may fault when attempting to execute a function or during the movement of data through one of the windows.
iAPX 432 Interface Processor Architecture Reference Manual The fault port is serviced by a 432 fault handling process where one of four actions may be taken: o Correct the reason for the fault and OOmplete any partially perfonmed function by completing the unfinished steps.
processor ipsor.psor process i prcs. prcs . context iprcs.ctxt. LEGEND: FAUL TED STATE ~ ~ 4~ .. ~~ FAULTS "FATAL" . , ,~ ~~ FLT FLT FLT FLT processor processor processor ipsor .psor ipsor.psor ipsor.psor .4~ ~. ~~ FLT FLT FLT PRO FAU process ; prcs .
iAPX 432 Interface Processor Architecture Reference Manual 6-2. FAULT HANDLING When an IP process encounters a process-level fault, it is autanatically sent to a 432 fault port to await service. A fault handling 432 process is designated to service the faulted processes waiting at the fault port.
APPENDIX A SYSTEM OBJECT STRUCTURES The object structures of Interface Processors are described belOil. The only objects structures described are for those whose form or interpretation differ fran GOP object structures.
iAPX 432 Interface Processor Architecture Reference Manual A context object is represented by a context access segment and an associated context data segment. Context Access Segments Diagranmatically, a context access segment is structured as shown belCM.
SYSTEM OBJECI'S STRUCIURES A- 2. PROCESS <l3JEC'IS Logically, a process is the execution by a processor of an instruction stream within a specific environment.
iAPX 432 Interface Processor Architecture Reference Manual process access entry = = 1----------------1 = refined context access segment = 12 1 1----------------1 11 1 carrier AD -1---> surrogate ca.
SYSTEM 0BJECrS STRUCTURES Process Data Segments The basic structure of a process data segment is shown below. = = double byte 1 displacement 1----------------1 = refined context data segment = 1 1 90 .
iAPX 432 Interface Processor Architecture Reference Manual The organization of the process status field is shown below. !x!x! 9 bits !x1x!x1x1xl II! 1 1 1- bound 1 1---- waiting for message 1------ pr.
SYSTEM. 0BJECl'S STRUClURES A- 3. PROCF.5SOR CBJECTS An 432 Interface Processor consists of two cxx:>perating processing elements: a mapping facility and a function request facility. The mapping facility translates Peripheral Subsystem addresses into 432 system addresses.
A-a iAPX 432 Interface Processor Architecture Reference Manual processor access entry 21 20 segment --> 0 = = 1----------------1 1 1 process = selection = list 1----------------1 1- -1 1 1- mapped .
SYSTEM 0BJECrS STRUCTURES The base rights field of a processor access segment access descriptor is interpreted in the same manner as for all objects of base type access segment.
iAPX 432 Interface Processor Architecture Reference Manual double byte = = displacement 1----------------1 = control window area = 1 4 1----------------1 reserved 1----------------1 ! cur.
SYSTEM 0BJECl'S STRUCl'URFS The stowed bit is interpreted as follows: o - running I - stopped The broadcast acceptance mode bit is interpreted as follows: o - broadcast interprocessor messag.
A-l2 LAPX 432 Interface Processor Architecture Reference Manual control window area double byte = = displacement 1----------------1 80 = reserved = 77 1----------------1 ! ! processor = fault = information 64 !----------------1 1 selected state ! 63 1----------------1 1 selected idx.
SYSTEM 0BJECrS STRUCl'URES Peripheral Subsystem State Field - The organization of the Peripheral Subsystem state field is shown belCM. 1 12 bits lxlxxlxl 1 1 1 1-- write sample delay ! 1--- xack .
• iAPX 432 Interface Processor Architecture Reference Manual Alarm, Dispatching, and Reconfiguration State Fields - The alarm, dispatching ("select process"), and reconfiguration state fields are used to indicate that the processor has responded to that type of signal and signalled the associated Peripheral Subsystem via interrupt.
SYSTEM 0BJECl'S STRt.CIURES Function State Field - The function state field is used to describe the current state of the function request facility.
iAPX 432 Interface Processor Architecture Reference Manual current status information. When operands are read from this subr ange or wr i tten into this subr ange, the processor data segment is accessed. Data written into the part of the subrange representing the function request facility is captured when no function is in progress.
SYSTEM OBJECTS STRUCTURES Above the block transfer information, a copy of the information contained in each of the processor-resident map entr ies (0 through 4) is represented by a data structure with the following organization. = = double byte 1----------------1 displacement 1 base disp.
iAPX 432 Interface Processor Architecture Reference Manual The 2-bit transfer direction subfield indicates the types of read/write requests from the associated Peripheral Subsystem which are valid with respect to this map entry.
SYSTEM OBJECl'S STRUCTURFS The base displacement field contains the byte displacement into the 432 segment used to construct a refinement of a data segment. See Figure 3-2 for an illustration of the role of a window's base displacement in forming a refinement.
iAPX 432 Interface Processor Architecture Reference Manual The I-bit segment bound subfield indicates whether or not the associated fault was caused by a segment bounds violation. A value of zero indicates that the fault was not caused by a segment bounds violation.
SYSTEM 0BJECrS srRUCTURES Selected Index and Selected State Fields - The selected index and selected state fields are filled in by the processor fram information found in the process carrier data segment at process selection time, i. e when a "select process" IPC is received.
iAPX 432 Interface Processor Architecture Reference Manual 4 - Clear broadcast acceptance mode 5 - Flush object table 6 - Suspend and fully requalify processor 7 - Suspend and requalify processor 8 - .
APPENDIX B FUNcrIOO SUMMARY Ap;>endix B sumnarizes the Interface Processor functions. Three lists are provided to assist in locating the page which contains a particular functioo description. One list, Table B-1, organizes the function set by alphabetical order.
iAPx 432 Interface Processor Architecture Reference Manual TABLE B-1 ALPHABEl'ICAL INDEX TO IP FUNcrICNS HEX DECIMAL FUNCTICN OPERATOR FUNcrICN NAME CODE ID PAGE (Logical Mode Functions) ALTER MAP AND SEI.
FUNCTIOO SUMMARY 'mBLE B-2 IP FUNcrICN SUMMARY BY FUNcrICN CODE HEX DECIMAL FUNCTICN OPERATOR CDDE FUNCrICN NAME ID PAGE (Logical Mode Functions) 00 ALTER MAP AND SELECr DATA SEGiENI' 3 B-6 .
iAPX 432 Interface Processor Architecture Reference Manual TABLE B-3 IP FUNCl'ICN SUMMARY BY OPERATOR ID DEX::IMAL HEX OPERATOR FUNCl'ICN ID FUNcrIOO NAME (DDE PAGE (logical Mode Functions) .
FUNCl'IOO StM1ARy FUNCl'ICN 'IEMPIA'IE Operator ID: ID Contents Function Request Facility 1------------------------1 results 0 through 9 1 reserved 1 1------------------------1 operand 6 1 reserved 1------------------------1 oper and 5 1 reserved .
iAPX 432 Interface Processor Architecture Reference Manual ALTER MAP AND SELECr DATA SEGmNI' Operator ID: 3 Contents Function Request Facility 1------------------------1 results 0 through 9 1 res.
FUNCrlOO SUMMARY ArlIER MAP AND SELECI' PHYSICAL SEG1ENI' Operator ID: 3 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 0 through 9 1 reserved 20H-33H .
iAPX 432 Interface Processor Architecture Reference Manual AMPLIFY RIGHTS Operator 10: 11 Contents Function Request Facility 1------------------------1 results 0 through 9 1 reserved 1----------------.
FUNCl'ICN Sl:M-1ARY BroAOCAST TO POCCESSORS Operator ID: 27 Contents Function Request Facility 1------------------------1 results I through 9 1 reserved 1 1------------------------1 result 0 1 BO.
iAPX 432 Interface Processor Architecture Reference Manual <DNDITIOOAL ROCEIVE Operator ID: 24 Contents Function Request Facility 1------------------------1 results I through 9 1 reserved 1 1------------------------1 .
FUNCrIOO Sm.f.1ARY CCNDITlOOAL SEND Operator ID: 22 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 1 through 9 1 reserved 1 22H-33H 1------------------------ res.
iAPX 432 Interface Processor Architecture Reference Manual COpy ACCESS DESCRIPTOR Operator 10: 7 Contents Function Request Facility 1------------------------1 results 0 through 9 ! reserved ! 1-------.
EN'lER ACCESS SEG1ENI' Operator ID: 10 Contents Function~est Facility Hex Byte Offset 1------------------------ results 0 through 9 ! reserved 20H-33H 1------------------------ operand 6 ! r.
iAPX 432 Interface Processor Architecture Reference Manual ENrER GLOBAL AOCESS SEG1Em' Operator ID: 9 Contents Function Request Facility 1------------------------1 results 0 through 9 1 reserved 1 1------------------------1 oper am. 6 1 reserved 1 1------------------------1 oper am.
FUNCTICN SUI+1ARY INDIVISIBLE ADD SHORI' ORDINAL Operator ID: 28 Contents Function Request Facility Hex Byte Offset 1------------------------1 results I through 9 ! reserved 1 22H-33H 1----------.
iAPx 432 Interface Processor Architecture Reference Manual INDIVISmLE INSERr SHORT ORDINAL Operator ID: 29 Contents Function Request Facility 1------------------------1 results I through 9 1 reserved .
FUNcrICN St.M1ARy INSPECr ACCESS Operator ID: 18 Contents Function Request Facility 1------------------------1 results 2 through 9 1 OBJECT DESCRIPTOR IMAGE! 1------------------------1 results 0 throu.
iAPX 432 Interface Processor Architecture Reference Manual INSPECr AOCESS DESCRIPTOR Operator ID: 17 Contents Function Request Facility 1------------------------1 results 2 through 9 1 reserved 1-----.
FUNcrION SUMMARY ~K 0BJECl' Operator ID: 19 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 1 through 9 1 reserved 1 22H-33H 1------------------------1 resul.
iAPX 432 Interface Processor Architecture Reference Manual NULL AOCESS DESCRIPTOR Operator ID: 8 . Contents Function Request Facility 1------------------------1 results 0 through 9 1 reserved 1 1-----.
READ P~OR STATUS AND cra:K (IDgical and Physical Mode) Operator ID: 6 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 2 through 9 1 reserved 1------------------------1 result I 1 SYSTEM cra:K 1 24H-33H 22H 1-- ____ -------------- ____ 1 .
iAPX 432 Interface Processor Architecture Reference Manual ~IVE Operator ID: 23 Contents Function Request Facility 1------------------------1 results 0 through 9 1 reserved 1------------------------1 .
FUNcrION S~ RESl'RIcr RIGHTS Operator ID: 12 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 0 through 9 1 reserved 20H-33H 1------------------------ oper an.
iAPX 432 Interface Processor Architecture Reference Manual REl'RIEVE PUBLIC TYPE REPRFSENI'ATICN Operator ID: 14 Contents Function Request Facility 1------------------------1 results 0 throu.
FUNcrIOO St.Mo1ARY REl'RIEVE TYPE REPRESENTATICN Operator ID: 13 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 0 through 9 1 reserved 1 20H-33H 1----------.
iAPX 432 Interface Processor Architecture Reference Manual REI'RI1WE REFINED CBJEcr Operator ID: 16 Contents Function Request Facility 1------------------------1 results a through 9 ! reserved ! .
RErRIEVE TYPE DEFINITICN Operator ID: 15 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 0 through 9 1 reserved 1 20H-33H 1------------------------ oper am 6 1 re.
iAPX 432 Interface Processor Architecture Reference Manual SEND Operator ID: 21 Contents Function Request Facility 1------------------------1 results 0 through 9 1 reserved 1------------------------1 .
FONcrION Sl.Mo1ARY SEND TO PROCESSOR (IDgical Mode) Operator ID: 4 Contents Function Request Facility Hex Byte Offset 1------------------------1 results I through 9 1 reserved 1 22H-33H 1-------------.
iAPX 432 Interface Processor Architecture Reference Manual SEND TO PRX:ESSOR (Physical· Mode) Operator ID: 4 Contents Function Request Facility 1------------------------1 results 1 through 9 1 reserv.
FUNcrIOO SUl+1ARY SEI' PERIPHERAL SUBSYSTEM MODE (logical and Physical Mode) Operator ID: 5 Contents Function Request Facility Hex Byte Offset 1------------------------1 results 0 through 9 1 res.
iAPx 432 Interface Processor Architecture Reference Manual StJRROGATE ROCEIVE Operator ID: 26 Contents Function Request Facility 1------------------------1 results 0 through 9 1 reserved 1------------.
FUNcrICN S~ SURroGA'lE SEND Operator 10: 25 Contents Function Request Facility Hex Byte Offset 1------------------------ results 0 through 9 1 reserved 20H-33H 1------------------------ oper and 6 . 1 reserved lEH 1------------------------ oper and 5 1 reserved ICH 1------------------------ oper and 4 1 reserved l.
iAPX 432 Interface Processor Architecture Reference Manual UNLOCK 0BJECr Operator 10: 20 Contents Function Request Facility 1------------------------ resul ts 0 through 9 ! reserved 1-----------------.
C-l. FAULT REPORTING APPENDIX C FAULT SUMMARY Both logical ana physical mode faults are reported in fault information areas as descr ibed belON. The faul t information area for oontext, process, and processor level faults has the same organization.
iAPX 432 Interface Processor Architecture Reference Manual fault information area = = double byte 1 displacement 1----------------1 1 execution statel n+12 1----------------1 1 operator id 1 1--------.
FAULT SUMMARY The Peripheral Subsystem status, context/process status, processor status, and system timer fields contain the values of the the corresponding on-chip registers at the time of the fault. The o:perator id, which differs fran the opcode field in an instruction, specifies the operator that causes the fault.
iAPX 432 Interface Processor Architecture Reference Manual The W field specifies whether the fault was on a read or write access. A value of zero indicates a read access.
FAULT SUMMARY The TT and EEEE fields specifY the fault level and the fault type. The TT bits are interpreted as follows: TT Description 00 Context Level Faults 01 Process Level Faults (group 1) 10 Process Level Faults (group 2) 11 Processor Level Faults There are 16 fault types within each of the 4 groups.
iAPX 432 Interface Processor Architecture Reference Manual Sub-operations Faults FAULT GroUPS Sbore Access Descriptor Faults => Level Fault Destination Delete Rights Fault Object Qualification Faul.
Operator Faults OPERATOR Alter Map and Select Data Segment Interconnect Descriptor Fault I/O Lock Fault Transfer Direction Fault Length Validity Fault Window Subrange Overlap Fault lnoamplete Block Tr.
iAPX 432 Interface Processor Architecture Reference Manual Retrieve Refined Object Refinement Control Object System Rights Fault => Object Qualification Faults (Refinement Ctl Obj) Source Object Va.
Broadcast be Processors Processor System Rights Fault => Object Qualification Faults (Processor AS) => Object Qualification Faults (CAXmDO Segment) Communication Segment Lock Fault Read Processor Status and Clock no explicit fault cases FAULT S'f.
iAPX 432 Interface Processor Architecture Reference Manual C-4. tOCN- INSTIUCTICN INTERFACE FAULTS OPERATOR Initialization => => Object Qualification Faults (processor AS) => Object Qualifica.
APPENDIX D INTERRUPT HANDLING ] Whenever the Interface Processor detects an event that may require attention from the IP controller, it records the nature of the event in the current IP processor data segment and e.mi ts a pulse on 1. ts interrupt line.
0-2 iAPX 432 Interface Processor Architecture Reference Manual yes Mask IP interrupt Reset latch Save interrupted environment Enable higher- priority .
INTERRlJPI' HANDLING The central logic of this approach assumes that there is a "list" of poosible interrupt sources to be scanned, and that passing through this list may uncover one (the usual case), multiple, or zero events that require responses.
iAPX 432 Interface Processor Architecture Reference Manual Processor Data Segment Subfield Function state field Table 0-1 Interrupt Sources Value Event Function completion state subfield OOOOs Functio.
APPENDIX E SYSTEM INITIALIZATICN System initialization may be considered as a sequence of activities that brings a 432-based system from an arbitrary state to a known state where execution can begin. Although the initialization sequence will vary widely among applications, this appendix outlines the basic procedure.
iAPX 432 Interface Processor Architecture Reference Manual An Interface Processor responds to an INIT pulse by aborting any current operation, entering physical reference mode, configuring its windows as shown in table E-l, clear ing broadcast acceptance node, and then issuing an interrupt request to its Attached Processor.
SYSTEM INITIALIZATION L ~ Processor .... ,... .... ..., Object (n) Storage Descriptor (Processor Number n) Processor ~ ~ :: ~ Object (Processor Number 1) (1) Storage Descriptor ([I) Object Table Header .
iAPX 432 Interface Processor Architecture Reference Manual Note that the term "processor obj ect" above is meant to include ccmnunication segments, am a processor carrier, in addition to processor access and data segments. Likewise, "process object" includes a domain, instruction segments, context objects, etc.
SYSTEM INITIALIZATION Before any function request is made by the IP, enough 432 memory must be initialized to allCM Ip· execution. This is necessary because the IP will attempt to update the segment maWed by windCM 4 in response to the function request.
iAPX 432 Interface Processor Architecture Reference Manual Having established its identity, the processor proceeds to locate its processor object. It does this by assuming that the initial object table directory is located at physical mennry address 8 (see figure E-I).
SYSTEM INITIALIZATION Table E-l Window Configuration Following !NIT Attt"ibute WindCM 0 Window 1 WindCM 4 Window Status Open Open Open Transfer Mode Block Interconnect Random Subrange Base Addres.
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APPENDIX F INTERPROCESS CCMruNICATICN AND DISPA'lCHIt.;x; EXAMPLE In Chapter 1, a printer example was used to demonstrate the flow of data between 432 processes and AP tasks.
F-2 iAPX 432 Interface Processor Architecture Reference Manual IP PROCESSOR OBJECT IP DISPATCHING PORT PRINT OBJECT CONTEXT PRINT REQUEST PORT 432 OBJECTS 432 PROCESS Figure F-l Print Example Objects .
INTERPIO::FSS mHlNlCATICN AND DISPA'lCHING EXAMPLE Procedures in the utilities section demonstrate how a programmer can construct facilities to invoke IP functions.
iAPX 432 Interface Processor Architecture Reference Manual Printer task: Procedure: /*****~******************************************/ /* */ /* Data Structures and Constants * / /* */ /***************.
INTERPR:nSS C(l.MJNICATICN AND DISPATCHING EXAMPLE /**************************************************************************************/ /* Seven object selectors are required.
iAPX 432 Interface Processor Architecture Reference Manual Dispatch: Procedure~ /**********************************************************************************/ /* This procedure hangs the IP's processor carrier on the IP's dispatching */ /* port.
INTERPRXESS exM-UNICATICN AND DISPA'ICHING EXAMPLE Get-print_message: Procedure: /**********************************************************************************/ /* Attempt to Receive a message fran the Print Request Port, Figure F-2 */ /**********************************************************************************/ W~ndow_4.
iAPX 432 Interface Processor Architecture Reference Manual Clooe wirrlow: ProCedure~ /**********************************************************************************/ /* Close windCM, note only ~ operarrls are Ie<;uired. * / /**********************************************************************************/ Window_4.
INTERP:rocESS CGMJNICATICN AND DISPATCHING EXAMPLE Return-print_message: Procedure; /**********************************************************************************/ /* Sem message to Print Reply Port. See Figure F-6 */ /**********************************************************************************/ W~ndow_4.
iAPX 432 Interface Processor Architecture Reference Manual /************************************************/ P ~ /* Initialization */ /* */ /*****************************************k******/ Call Dis.
IP DISPATCHI G PORT INTERPROCESS a::MruNICATIGl AND DISPAroIING EXAMPLE IP OCESSOR PR o BJECT ~ IPI PR~ESS ~ iF c1r" PRINT REQUEST PORT (f4 CARRI~4 432 PROCESS ~.
iAPX 432 Interface Processor Architecture Reference Manual IP DISPATCHING PORT IP AP C~ .:- / -.tIo "c, / CARRIER - IP ~/ IP ~~/ 4 PROCESSOR PROCESS ~ /~<v OBJECT ~'v«;/': ~Cj/ / 1 / / / / ( I PRINT I PRINT REQUEST f REPLY PORT I PORT I , .
INTERP~S ~ICATIrn AND DISPATCHING EXAMPLE INTERRUPT ,----, ;' ... 1/ '- IP AP IP -- A.~ SELECTED (- DISPATCHING v -v PORT STATE SELECTED INDEX £ARRIEB J IP IP -- PROCESSOR J PROCESS OBJECT .
F-l4 iAPX 432 Interface Processor Architecture Reference Manual PRINT REQUEST PORT IP PROCESS - PRINT REPLY PORT ,fA CARRIE' (~ 432 PROCESS IP r ~ WINDOW III' ~ PRINT OBJECT ~ EJ "ALTER.
PRINT REQUEST PORT INTERPRXESS <XMvIDNICATIOO AND DISPATCHING EXAMPLE .-.--_/ IP .J PROCES, I f - - 432 PROCESS ,,- / PRINT REPLY PORT r I ,~ PRINT OBJECT IP ·SEND" function Figure F-6 Print .
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