Manuel d'utilisation / d'entretien du produit LAN9420i du fabricant SMSC
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SMSC LAN9420/LAN9420i DA T ASHEET Revision 1.22 ( 09-25-08) Datasheet PRODUCT FEA TURES LAN9420/LAN9420i Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Highlight s Opt.
ORDER NUMBERS: LAN9420-NU FOR 128-PIN VTQFP , LEAD-F REE ROHS COMPLIANT PACKAGE (0 TO 70 o C) LAN9420i-NU FOR 128-PIN VTQFP , LE AD-FREE ROHS COMPLIANT PAC KAGE (-40 o TO 85 o C) Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 3 Revision 1.22 (09-25-08) DA T ASHEET T able of Content s Chapter 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 4 SMSC LAN9420/LAN9420i DA T ASHEET 3.4.2 Data Descriptors and Buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 5 Revision 1.22 (09-25-08) DA T ASHEET 3.6.6 Parallel Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 6 SMSC LAN9420/LAN9420i DA T ASHEET 4.3.2 Transmit Poll Demand Regi ster (TX_POLL_DEMAND) . . . . . . . . . . . . . . . . . . . . . . . . 105 4.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 7 Revision 1.22 (09-25-08) DA T ASHEET 5.7 PCI I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 8 SMSC LAN9420/LAN9420i DA T ASHEET List of Figures Figure 1.1 System Level Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 9 Revision 1.22 (09-25-08) DA T ASHEET List of T ables Table 2.1 PCI Bus Interface Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 10 SMSC LAN9420/LAN9420i DA T ASHEET Table 5.13 L AN9420/LAN9420i Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 1 1 Revision 1.22 (09-25-08) DA T ASHEET Chapter 1 Introduction 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 12 SMSC LAN9420/LAN9420i DA T ASHEET 1.2 General Description LAN9420/LAN9420i is a full-featu r ed, Fast Ethernet controller whic h allows for the easy and cost- effective integration of Fast Ethernet into a PCI-based system.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 13 Revision 1.22 (09-25-08) DA T ASHEET 1.3 PCI Bridge LAN9420/LAN9420i implements a PCI Local Bus S pec ification Revision 3.0 compliant interface, supporting the PCI Bus Power Manageme nt Interface S pecification Revision 1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 14 SMSC LAN9420/LAN9420i DA T ASHEET 1.7.2 PLL and Power Management LAN9420/LAN9420i interfaces with a 25MHz crystal osci llator from which all internal clocks, with the exception of PCI clock, are generated .
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 15 Revision 1.22 (09-25-08) DA T ASHEET Chapter 2 Pin Description and Configuration Figure 2.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 16 SMSC LAN9420/LAN9420i DA T ASHEET 2.1 Pin List T able 2.1 PCI Bus Interface Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 PCI Clock In PCICLK IS PCI Clock In: 0 to 33MHz PCI Clock Input.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 17 Revision 1.22 (09-25-08) DA T ASHEET Note 2.1 This pin is used fo r factory testing and is l atched on power up. Thi s pin is pulled high through an internal resistor and must not be pulled low externa lly .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 18 SMSC LAN9420/LAN9420i DA T ASHEET T able 2.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 19 Revision 1.22 (09-25-08) DA T ASHEET T able 2.5 PLL and Ethernet PHY Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 1 Crystal Input XI ICLK Crystal Input: External 25MHz crystal input.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 20 SMSC LAN9420/LAN9420i DA T ASHEET T able 2.6 Power and Ground Pins NUM PINS NAME SYMBOL BUFFER TYPE DESCRIPTION 2 +3.3V Analog Power Supply VDD33A P +3.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 21 Revision 1.22 (09-25-08) DA T ASHEET T ab le 2.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 22 SMSC LAN9420/LAN9420i DA T ASHEET 2.2 Buffer T ypes BUFFER TYPE DESCRIPTION IS Schmitt.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 23 Revision 1.22 (09-25-08) DA T ASHEET Chapter 3 Functional Description 3.1 Functional Overview The LAN9420/LAN9420 i Ethernet Controller consists of five majo r functional blocks.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 24 SMSC LAN9420/LAN9420i DA T ASHEET 3.2.
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 25 Revision 1.22 (09-25-08) DA T ASHEET 3.2.2 PCI Interface Environments The PCIB supports only Device op eration. It fu nctions as a simple bridge, pe rmitting LAN9420/LAN9420i to act as a master/target PCI device on the PCI bus.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 26 SMSC LAN9420/LAN9420i DA T ASHEET 3.2.4 PCI T arget Interface The PCI target interface implements the address spaces listed in T able 3.1 .
Single-Chip Ethernet Controller with HP Auto- MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 27 Revision 1.22 (09-25-08) DA T ASHEET . 3.2.4.2.2 I/O MAPPING OF CSR The I/O BAR (BAR4) is doub le mapped over the CS R space with the n on-prefetchable area.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 28 SMSC LAN9420/LAN9420i DA T ASHEET Bit 3 of the PCI Device St atus Register . The PCI Device S tatus Register and PCI Device Command Register are standard registers in PCI Configur ation S p ace.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 29 Revision 1.22 (09-25-08) DA T ASHEET General-purpose ti mer interrupt (GPT_INT) G.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 30 SMSC LAN9420/LAN9420i DA T ASHEET write of '1' to the corresponding status bit in th e INT _STS register . The remaining interrupts are cleared from the source CSR.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 31 Revision 1.22 (09-25-08) DA T ASHEET Once enabled, the GPT counts down either until it reaches 0000h, or un til a new pre-load value is written to the GPT_LOAD field.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 32 SMSC LAN9420/LAN9420i DA T ASHEET Note: EEPROM byte addresses past 0Ah can be used to sto re data for any purpose. The signature value o f 0xA5 is stored at address 0.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 33 Revision 1.22 (09-25-08) DA T ASHEET Note: The EEPROM device powers-up in the erase/write disabled st ate. T o modify the contents of the EEPROM, the Host must fi rst issue the EWEN command.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 34 SMSC LAN9420/LAN9420i DA T ASHEET ERAL (Erase All): If erase/write o perations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 35 Revision 1.22 (09-25-08) DA T ASHEET EWDS (Erase/Write Disable): After issued, the EEPROM will ignore erase and write commands. T o re-enable erase/write operatio ns issue the EWEN comma nd.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 36 SMSC LAN9420/LAN9420i DA T ASHEET READ (Read Location): This command will cause a re ad of the EEPROM location pointed to by EPC Address (EPC_ADDR).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 37 Revision 1.22 (09-25-08) DA T ASHEET WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command wi ll cause the contents of the E2P_DA T A register to be written to every EEPR OM memory location.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 38 SMSC LAN9420/LAN9420i DA T ASHEET 3.3.6 System Control and St atus Registers (SCSR) Please refer to Section 4.2, "System Control and St atus Registers (SCSR)," on p age 86 for a complete description of the SCSR.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 39 Revision 1.22 (09-25-08) DA T ASHEET Descriptor lists and dat a buffe rs, described in this chapter . The DMAC trans fers RX data fr ames to the RX buf fers in Host memory and transmi ts dat a from TX buffers in the Host memory .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 40 SMSC LAN9420/LAN9420i DA T ASHEET Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 41 Revision 1.22 (09-25-08) DA T ASHEET 3.4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 42 SMSC LAN9420/LAN9420i DA T ASHEET 29:16 FL - Frame Length Indicates the le ngth in bytes, including the CRC, of the recei ved frame that was transferred to Host memory .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 43 Revision 1.22 (09-25-08) DA T ASHEET 7 TL - Frame T oo Long When set, indicates the frame length exceeds maximum Ethernet-spe cified size of 15 18 bytes (or 1522 bytes when VLAN tagging is enabled).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 44 SMSC LAN9420/LAN9420i DA T ASHEET Receive Descriptor 1 (RDES1) Receive Descriptor 2 (RDES2) T ab le 3 .6 RDES1 Bit Fi elds BITS DESCRIPTION 31:26 RESERVED Host Actions: Cleared on writes and ign ored on reads.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 45 Revision 1.22 (09-25-08) DA T ASHEET Receive Descriptor 3 (RDES3) 3.4.2.2 T ransmit descriptors The descriptors must be 4-DWORD (16-byte) aligned, while there are no al ignment restrictions on transmit buffer addresses.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 46 SMSC LAN9420/LAN9420i DA T ASHEET T ransmit Descriptor 0 (TDES0) TDES0 contains the transmitted frame status and th e descriptor ownership information.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 47 Revision 1.22 (09-25-08) DA T ASHEET T ransmit Descriptor 1 (TDES1) 8 EC - Excessive Collision When set, indicates tha t the transmission was aborted after 16 successive col lisions while attempting to transmit the current frame.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 48 SMSC LAN9420/LAN9420i DA T ASHEET 28 RESERVED Host Actions: Cleared on wri tes and ignored on read s. DMAC Actions: Ignored on reads. DMAC does not write to TDES1.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 49 Revision 1.22 (09-25-08) DA T ASHEET T ransmit Descriptor 2 (TDES2) T ransmit Descriptor 3 (TDES3) 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 50 SMSC LAN9420/LAN9420i DA T ASHEET Note: The TX and RX processes an d paths are inde pendent of each other and can be started or stopped independentl y of one another .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 51 Revision 1.22 (09-25-08) DA T ASHEET When the memory buffer ends before the frame end.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 52 SMSC LAN9420/LAN9420i DA T ASHEET 3.4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 53 Revision 1.22 (09-25-08) DA T ASHEET 3.5 10/100 Ethernet MAC The Ethernet Media Access Controller (MAC ) provides the foll owing features: Compliant with the IEEE 8 02.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 54 SMSC LAN9420/LAN9420i DA T ASHEET retransmission and detection of collision frames, as well as an L3 che cksum offload engine for tran smit and receive operations.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 55 Revision 1.22 (09-25-08) DA T ASHEET . 3.5.3 Address Filtering Functional Description The Ethernet address fields of an Et herne t packet, consists of two 6-byte fields: one for the destination address and one for the source address.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 56 SMSC LAN9420/LAN9420i DA T ASHEET 3.5.3.1 Perfect Filtering This filtering mode passes only in coming frames wh ose destination addre ss field exactly ma tches the value programmed into the MAC address high register (refer to Section 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 57 Revision 1.22 (09-25-08) DA T ASHEET 3.5.4 W akeup F rame Detection Setting the Wakeup Frame Enable bit (W AKE_EN) in the “WUCSR—W akeup Control a nd S tatus Register”, places th e MAC in the w akeup frame dete ction mode.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 58 SMSC LAN9420/LAN9420i DA T ASHEET The Filter i Byte Mask defines which incoming fram e bytes F ilter i will examine to determine whether or not this is a wakeup fra me.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 59 Revision 1.22 (09-25-08) DA T ASHEET T abl e 3.19 indicates the cases that prod uce a wake when the W akeup Frame Enable (W AKE_EN) bit of the W akeup Control and St atus Register (WUCSR) is set.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 60 SMSC LAN9420/LAN9420i DA T ASHEET Then the MAC inspects the frame for 16 repetit ions of the MAC address without any breaks or interruptions.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 61 Revision 1.22 (09-25-08) DA T ASHEET Example frame configurations: Figure 3.20 T ype II Ethe rnet Frame Figure 3.21 Ethernet Frame with VLAN T ag Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 62 SMSC LAN9420/LAN9420i DA T ASHEET The RXCOE supports a maximum of two VLAN tags. If there are more tha n two VLAN tags, the VLAN protocol identifier for the third tag is treated as an Ethernet type field.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 63 Revision 1.22 (09-25-08) DA T ASHEET 3.5.5.1 RX Checksum Calculation The checksum is calculated 16 bits at a time. In t he case of an odd si zed fram e, an extra byte of zero is used to pad up to 16 bits.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 64 SMSC LAN9420/LAN9420i DA T ASHEET 3.5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 65 Revision 1.22 (09-25-08) DA T ASHEET Figure 3.25 100BASE-TX Dat a Path 3.6.1 100BASE-TX T ransmit The data p ath of the 100BASE-TX is shown in Figure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 66 SMSC LAN9420/LAN9420i DA T ASHEET 3.6.1.2 Scrambling Repeated data patterns (especially the IDLE code-grou p) can have power spectral den sities with large narrow-band peaks.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 67 Revision 1.22 (09-25-08) DA T ASHEET 3.6.1.3 NRZI and ML T3 Encoding The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it become s a serial 125MHz NRZI data stream.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 68 SMSC LAN9420/LAN9420i DA T ASHEET and CA T- 5 cable. The equalizer ca n restore the sig nal for any good-qua lity CA T-5 cable between 1m and 150m.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 69 Revision 1.22 (09-25-08) DA T ASHEET 3.6.3 10BASE-T T ransmit Data to be transmitted comes from the MAC. T he 10BASE-T transmitter rece ives 4-bit nibbles from the internal MII at a rate of 2.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 70 SMSC LAN9420/LAN9420i DA T ASHEET is indicated by the flag “XPOL“, bit 4 in register 27. The 10M PLL is locked onto the received Manchester signal and from this, generates the received 20MHz clock.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 71 Revision 1.22 (09-25-08) DA T ASHEET The data transmitted by an FLP burst i s known as a “Link Code Word.” These are defined fully in IEEE 802.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 72 SMSC LAN9420/LAN9420i DA T ASHEET 3.6.6.3 Half vs. Full-Duplex Half-duplex o peration relies on the CSMA/CD (Carrier Sense Multiple Access / Coll ision Detect) protocol to handle network traffic and collisions.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 73 Revision 1.22 (09-25-08) DA T ASHEET Note: For maximum power savings, a uto-negotiation should b e disabled before enabling th e General Power-Down mode.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 74 SMSC LAN9420/LAN9420i DA T ASHEET the nPME signal upon detection of variou s power management events, such as an Ethernet “Wake On LAN”, or upon detection of an Ethern et link status change.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 75 Revision 1.22 (09-25-08) DA T ASHEET 3.7.3 Device Clocking LAN9420/LAN9420i requires a fixed-frequency 25MHz cl ock source. This is typically provided b y attaching a 25MHz crystal to the XI and XO p ins.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 76 SMSC LAN9420/LAN9420i DA T ASHEET 3.7.4.1.2 EXITING THE G3 STATE When the system leaves the G3 state, the device will behave as follows. S tate transitions are illustrated in Fig ure 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 77 Revision 1.22 (09-25-08) DA T ASHEET detection. Refer to section Section 3.7.6, "Detecting Powe r Management Events," on page 80 for more information.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 78 SMSC LAN9420/LAN9420i DA T ASHEET D3 HOT to D0 U (T8): This transition occurs when PCInRST is asserted while in the D3 HOT state (PCInRST=1 to 0, PM_ST A T E=1 1 b, V AUXDET=X, PWRGOOD=1).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 79 Revision 1.22 (09-25-08) DA T ASHEET 3.7.5 Reset s The LAN9420/LAN 9420i device employs the followin g resets: Power-On Reset (POR): This reset is asserted on initial application of device power .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 80 SMSC LAN9420/LAN9420i DA T ASHEET Note 3.10 PHY register bits designated as N ASR are not initialized by setting the PHY Soft Reset bit in the PHY’s Basic Control Register .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 81 Revision 1.22 (09-25-08) DA T ASHEET T wo control bits are implemented in the PM T_CTRL SCSR: W ake-on-LAN enable (WOL_EN) and Energy Detect enable (ED_EN ).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 82 SMSC LAN9420/LAN9420i DA T ASHEET b. The software application must wait for all pen ding DMA transactions to complete . Upon completion, no further transactions are permitted.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 83 Revision 1.22 (09-25-08) DA T ASHEET Chapter 4 Register Descriptions The registers are partitioned into five groups. The first group is the Sy stem Control and St atus Registers (SCSR).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 84 SMSC LAN9420/LAN9420i DA T ASHEET Figure 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 85 Revision 1.22 (09-25-08) DA T ASHEET 4.1 Register Nomenclature T abl e 4.1 describes the register bit attri butes u sed throughout this section.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 86 SMSC LAN9420/LAN9420i DA T ASHEET 4.2 System Control and St atus Registers (SCSR) T abl e 4 .2, "System Control and S tatus Register Addresses" lists the registers contained i n this section.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 87 Revision 1.22 (09-25-08) DA T ASHEET 4.2.1 ID and Revision (ID_REV) This register contains the device ID and block revision. Note 4.1 Default value is depe ndent on device revi sion.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 88 SMSC LAN9420/LAN9420i DA T ASHEET 4.2.2 Interrupt Control Register (INT_CTL) Interrupts are enabled/disab led through this register . Refer to Section 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 89 Revision 1.22 (09-25-08) DA T ASHEET 4.2.3 Interrupt St atus Register (INT_STS) This register contains the curren t status of the gen erat ed interrupts.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 90 SMSC LAN9420/LAN9420i DA T ASHEET 1 W ake Event Interru pt (W AK E_INT) Indicates a valid MAC wakeup event (W akeup Frame or Magic Packet) or PHY interrupt (Energy-Detect) has been received.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 91 Revision 1.22 (09-25-08) DA T ASHEET 4.2.4 Interrupt Configurat ion Register (INT_CFG) This register configures and moni tors the interrupt (IRQ) signal .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 92 SMSC LAN9420/LAN9420i DA T ASHEET 4.2.5 General Purpose Input/Output Configuration Regi ster (GPIO_CFG) This register configures th e GPIO and LED functions.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 93 Revision 1.22 (09-25-08) DA T ASHEET Note 4.2 Default value is depe ndent on the state of the GPIO pin. 10:8 GPIO Direction 0-2 (GPDIRn) When set, enables the correspond ing GPIO as an output.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 94 SMSC LAN9420/LAN9420i DA T ASHEET 4.2.6 General Purpose Timer Conf iguration Register (GPT_CFG) This register configures the general purpose time r (GPT).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 95 Revision 1.22 (09-25-08) DA T ASHEET 4.2.7 General Purpose Timer Curre nt Count Register (GPT_CNT) This register reflects the current valu e of the general purpose ti mer .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 96 SMSC LAN9420/LAN9420i DA T ASHEET 4.2.8 Bus Master Bridge Conf iguration Register (BUS_CFG) This register determines the bus arbitration c haracteristics for the RX and T X DMA engines.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 97 Revision 1.22 (09-25-08) DA T ASHEET 4.2.9 Power Management C ontrol Register (PMT_CTRL) This register controls the wake even t detectio n featu res.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 98 SMSC LAN9420/LAN9420i DA T ASHEET 4.2.10 Free Run Counter (FREE_RUN) This register reflects the value of the free-run ning (6. 25Mhz) counter (FRC).
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 99 Revision 1.22 (09-25-08) DA T ASHEET 4.2.1 1 EEPROM Command Register (E2P_CMD) This register is used to control the read and write operations with the serial EEPROM.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 100 SMSC LAN9420/LAN9420i DA T ASHEET 30-28 EPC Command (EPC_CMD) This field is used to issue command s to the EEPROM co ntroller . The EPC will execute commands when the EPC Busy bit is set.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 101 Revision 1.22 (09-25-08) DA T ASHEET 8 EEPROM Loaded When set, this bit indica tes that a valid EEPROM was found, and that the MAC address and SSVID/SSID programming have completed normally .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 102 SMSC LAN9420/LAN9420i DA T ASHEET 4.2.12 EEPROM Dat a Register (E2P_DA T A) This register is used i n conjunction with the E2P_CMD register to perform read and write operations with the serial EEPROM.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 103 Revision 1.22 (09-25-08) DA T ASHEET 4.3 DMAC Control and S t atus Registers (DCSR) T abl e 4.4 lists the register s contained in this section.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 104 SMSC LAN9420/LAN9420i DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 105 Revision 1.22 (09-25-08) DA T ASHEET 4.3.2 T ransmit Poll Demand Register (TX_POL L_DEMAND) This register enables the TX DMA engine to check for new descriptors.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 106 SMSC LAN9420/LAN9420i DA T ASHEET 4.3.3 Receive Poll Demand Re gister (RX_POLL_DEMAND) This register enables the RX DMAC to check for new descriptors.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 107 Revision 1.22 (09-25-08) DA T ASHEET 4.3.4 Receive List Base Address Register (RX_BASE_ADDR) This register specifies the start address of th e receive buffer list.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 108 SMSC LAN9420/LAN9420i DA T ASHEET 4.3.5 T ransmit List Base A ddress Register (TX_ BASE_ADDR) This register specifies the start address of the tr ansmit buf fer list.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 109 Revision 1.22 (09-25-08) DA T ASHEET 4.3.6 DMA Controller St atus Register (DMAC_ST A TUS) This register contains all of the st atus bit s that the DMAC reports to the Host system.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 1 10 SMSC LAN9420/LAN9420i DA T ASHEET 14:10 RESERVED RO - 9 Receive Watchdog T i meout (RWT) A Receive Watchdog T imeout occurs when the leng th of the receiving frame is greater than 2048 bytes through 2560 bytes.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 1 1 1 Revision 1.22 (09-25-08) DA T ASHEET 4.3.7 DMA Controller Control (Opera tion Mode) Register (DMAC_CONTROL) This register est ablishes the RX an d TX operating modes and co mmands.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 1 12 SMSC LAN9420/LAN9420i DA T ASHEET 1 St art/Stop Re ceive (SR) When set, the Receive Process is p laced in the Running state. The DMA Controller attempts to acquire the de scriptor from the receive list and process incoming frames.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 1 13 Revision 1.22 (09-25-08) DA T ASHEET 4.3.8 DMA Controller Interrupt Enable Register (DMAC_INTR_ENA) This register enables the DMAC interru pts reported in the DMAC_ST A TUS reg ister .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 1 14 SMSC LAN9420/LAN9420i DA T ASHEET 1 T ransmit Process Stopped (TPS_EN) The Transmit Process S toppe d Interrupt is enabled only when this bit and the Abnormal Interru pt Summary Enable bit (bit [15]) are set.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 1 15 Revision 1.22 (09-25-08) DA T ASHEET 4.3.9 Missed Frame and Buffer Overfl ow Counter Reg (MISS_FRAME_CNTR) The DMAC maintains two counters to track the num ber of missed frames dur ing a receive operation.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 1 16 SMSC LAN9420/LAN9420i DA T ASHEET 4.3.10 Current T ransmit Buffer Address Register (TX_BUFF_ADDR) This register points to the current tran smit buffer address being read by the DMAC.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 1 17 Revision 1.22 (09-25-08) DA T ASHEET 4.3.1 1 Current Receive Bu ffer Ad dress Register (RX_BUFF_ADDR) This register points to the current rece ive buffer address being read by the D MAC.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 1 18 SMSC LAN9420/LAN9420i DA T ASHEET 4.4 MAC Control and St atus Registers (MCSR) T abl e 4.5 lists the register s contained in this section.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 1 19 Revision 1.22 (09-25-08) DA T ASHEET 4.4.1 MAC Control Register (MAC_CR) This register establishes the RX and T X operating modes and inclu des controls for address filtering and packet filtering.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 120 SMSC LAN9420/LAN9420i DA T ASHEET 15 Hash Only Filtering mode (HO) When set, the addr.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 121 Revision 1.22 (09-25-08) DA T ASHEET 7-6 BackOff Limit (BOLMT) The BOLMT bits allow the user to set its back-off limit in a relaxed or aggressive mode.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 122 SMSC LAN9420/LAN9420i DA T ASHEET 2 Receiver Enable (RXEN) When set (1), the MAC’s receiver is enabled and will receive frames from the internal PHY .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 123 Revision 1.22 (09-25-08) DA T ASHEET 4.4.2 MAC Address High Register (ADDRH) This register contains the upper 16 bits of the physical address of the MAC, where ADDRH[15:8] is the 6 th octet of the RX frame.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 124 SMSC LAN9420/LAN9420i DA T ASHEET 4.4.3 MAC Address Low Register (ADDRL) This register contains the lower 32 bits of the ph ysical address of the MAC, where ADDRL[7:0] is the first octet of the Ethernet frame.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 125 Revision 1.22 (09-25-08) DA T ASHEET 4.4.4 Multicast Hash T able High Register (HASHH) The 64-bit Multicast table is used for group address fi lter ing.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 126 SMSC LAN9420/LAN9420i DA T ASHEET 4.4.5 Multicast Hash T able Low Register (HASHL) This register d efines the lower 32 -bits of the Multicast Hash T able.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 127 Revision 1.22 (09-25-08) DA T ASHEET 4.4.6 MII Access Regi ster (MII_ACCESS) This register is used to control the management cycles to the interna l PHY .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 128 SMSC LAN9420/LAN9420i DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 129 Revision 1.22 (09-25-08) DA T ASHEET 4.4.8 Flow Control Register (FLOW) This register is us ed to control the genera tion and re ception of the Control frames by the MAC’s flow control block.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 130 SMSC LAN9420/LAN9420i DA T ASHEET 4.4.9 VLAN1 T ag Re gister (VLAN1) This register contains the VLAN tag fi eld to iden tify VLAN1 frames.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 131 Revision 1.22 (09-25-08) DA T ASHEET 4.4.10 VLAN2 T ag Re gister (VLAN2) This register contains the VLAN tag fi eld to iden tify VLAN2 frames.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 132 SMSC LAN9420/LAN9420i DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 133 Revision 1.22 (09-25-08) DA T ASHEET 4.4.12 W akeup Contro l and St atus Register (WUCSR) This register contains data pertaining to th e MAC’s remote wakeup status and capabilities.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 134 SMSC LAN9420/LAN9420i DA T ASHEET 4.4.13Checksum Offload Engine Control Register (COE_CR) This register co ntrols the RX and TX checksum of fload engines .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 135 Revision 1.22 (09-25-08) DA T ASHEET 4.5 PHY Registers The PHY registers are not memory mappe d. These registers are acce ssed indirectly through the MAC via the MII_ACCESS and MII_DA T A registers.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 136 SMSC LAN9420/LAN9420i DA T ASHEET 4.5.1 Basic Control Register Index (In Decimal): 0 Size: 16 bits BITS DESCRIPTION T YPE DEFAULT 15 PHY Sof t Reset 1 = PHY software reset.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 137 Revision 1.22 (09-25-08) DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 138 SMSC LAN9420/LAN9420i DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 139 Revision 1.22 (09-25-08) DA T ASHEET 4.5.4 PHY Identifier 2 Index (In Decimal): 3 Size: 16 bits BITS DESCRIPTION T YPE DEFAULT 15:10 PHY ID Number b Assigned to the 19 th through 24th b its of the OUI.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 140 SMSC LAN9420/LAN9420i DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 141 Revision 1.22 (09-25-08) DA T ASHEET 4.5.6 Auto Negotiation Link Partner Ability Index (In Decimal): 5 Size: 16 bits BITS DESCRIPTION T YPE DEFAULT 15 Next Page 1 = next page capable, 0 = no next page ability .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 142 SMSC LAN9420/LAN9420i DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 143 Revision 1.22 (09-25-08) DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 144 SMSC LAN9420/LAN9420i DA T ASHEET 4.5.9 Special Modes Index (In Decimal): 18 Size: 16 bits BITS DESCRIPTION T YPE DEFAULT 15:8 RESER VED RO - 7-5 MODE PHY Mode of operation.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 145 Revision 1.22 (09-25-08) DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 146 SMSC LAN9420/LAN9420i DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 147 Revision 1.22 (09-25-08) DA T ASHEET 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 148 SMSC LAN9420/LAN9420i DA T ASHEET 4.5.13 PHY S pecial Control/St a tus Note 4.6 Bit 6 of this reg ister must be set to ‘1’ for write operations.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 149 Revision 1.22 (09-25-08) DA T ASHEET 4.6 PCI Configuration S p ace CSR (CONFIG CSR) Configuration and read back o f t he CONFIG CSR is accomplished by the Host processor via the PCI bus.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 150 SMSC LAN9420/LAN9420i DA T ASHEET T abl e 4.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 151 Revision 1.22 (09-25-08) DA T ASHEET 4.6.1 PCI Power Management Ca pabilities Register (PCI_PMC) This register implements the standard capability structure used to define powe r management features in a PCI device.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 152 SMSC LAN9420/LAN9420i DA T ASHEET Note 4.10 The default state of this field is dependant on the setting of the V AUXDET signal as n oted in the description.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 153 Revision 1.22 (09-25-08) DA T ASHEET 4.6.2 PCI Power Management Control and St atus Register (PCI_PMCSR) This register controls the d evice’s power state.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 154 SMSC LAN9420/LAN9420i DA T ASHEET Note 4.1 1 The default state of this field is dependant on the setting of the V AUXDET signal as noted in the description.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 155 Revision 1.22 (09-25-08) DA T ASHEET Chapter 5 Operational Characteristics 5.1 Absolute Maximum Ratings* Supply V oltage (VDD33A, VDD33BIAS, VDD33 IO) ( Note 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 156 SMSC LAN9420/LAN9420i DA T ASHEET 5.3 Power Consumption This section details the power consumption of LAN9 420/ LAN9420i as measured d uring various modes of operation.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 157 Revision 1.22 (09-25-08) DA T ASHEET 5.3.2 D3 - Enabled for W ake Up Packet Detection 5.3.3 D3 - Enabled for Link St atus Change Detection (Energy Detect) T able 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 158 SMSC LAN9420/LAN9420i DA T ASHEET 5.3.4 D3 - PHY in General Power Down Mode 5.3.5 Maximum Power Consumption Note 5.5 Over the conditions specified in Section 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 159 Revision 1.22 (09-25-08) DA T ASHEET 5.4 DC S pecifications Note 5.6 This specification applies to all IS type inputs and tri-stated bi-direc tional non-PCI pins.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 160 SMSC LAN9420/LAN9420i DA T ASHEET Note 5.10 Measured at line side of transforme r , line replaced by 100 Ω (+/- 1%) resistor . Note 5.1 1 Offset from 16nS pulse width at 50% of pulse peak.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 161 Revision 1.22 (09-25-08) DA T ASHEET 5.5 AC S pecifications This section contains timing informa tion for non-PCI signals. Note: LAN9420/LAN9420i ad heres to the PCI Local Bus S pecification re vision 3.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 162 SMSC LAN9420/LAN9420i DA T ASHEET 5.6 PCI Clock T iming The following specifies th e PCI clock requirements for LAN9420/LAN9420i: Note 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 163 Revision 1.22 (09-25-08) DA T ASHEET 5.7 PCI I/O T iming The following specifies th e PCI I/O requirements for LAN9420/LAN9420i: Note: Input test is done with 0.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 164 SMSC LAN9420/LAN9420i DA T ASHEET Note: PCI signal timing is specified with loads de tailed in Section 4.2.3.2 of the PCI Local Bus S pecifica tion, Rev .
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 165 Revision 1.22 (09-25-08) DA T ASHEET 5.8 EEPROM T iming The following specifies th e EEPROM timing requirements for LAN9420/LAN942 0i: Figure 5.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 166 SMSC LAN9420/LAN9420i DA T ASHEET 5.9 Clock Circuit LAN9420/LAN9420i can accept either a 25MHz cryst al (preferred) or a 25MHz singl e-ended clock oscillator (+/- 50ppm) input.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 167 Revision 1.22 (09-25-08) DA T ASHEET Chapter 6 Package Outline 6.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet Revision 1.22 (09-25-08) 168 SMSC LAN9420/LAN9420i DA T ASHEET Notes: 1. All dimensions are in mill imeters unless otherwise noted. 2. Dimensions b & c apply to the flat section of the lead foot between 0.
Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface Datasheet SMSC LAN9420/LAN9420i 169 Revision 1.22 (09-25-08) DA T ASHEET Chapter 7 Revision History T able 7.1 C ustomer Revision Histo ry REVISION LEVEL & DATE SECTI ON/FIGURE/ENTRY CORRECTION Rev .
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté SMSC LAN9420i c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du SMSC LAN9420i - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation SMSC LAN9420i, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le SMSC LAN9420i va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le SMSC LAN9420i, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du SMSC LAN9420i.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le SMSC LAN9420i. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei SMSC LAN9420i ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
