Manuel d'utilisation / d'entretien du produit PD78P214 du fabricant NEC
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USER'S MANUAL µ PD78214 SUB-SERIES 8-BIT SINGLE-CHIP MICROCOMPUTER HARDW ARE µ PD78212 µ PD78213 µ PD78214 µ PD78P214 µ PD78212 (A) µ PD78213 (A) µ PD78214 (A) µ PD78P214 (A) Document No.
1 2 3 4 5 6 7 8 GENERAL PIN FUNCTIONS CPU FUNCTION CLOCK GENERATOR PORT FUNCTIONS REAL-TIME OUTPUT FUNCTION TIMER/COUNTER UNITS A/D CONVERTER 9 ASYNCHRONOUS SERIAL INTERFACE CLOCK SYNCHRONOUS SERIAL I.
Cautions on CMOS Devices 1 Countermeasures against static electricity for all MOSs Caution When handling MOS devices, take care so that they are not electrostatically charged.
The information in this document is subject to change without notice. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.
Main Revisions in This Edition Page Description P.55 V SS and "Caution" have been added in (a) of Fig. 4-2 . P.329 "Caution" has been added in (2) of Section 12.4.6 . P.383 "Caution" has been added in (b) of Section 14.4.
PREFACE Users: This manual is aimed at engineers who need to be familiar with the capabilities of the µ PD78214 sub-series for application program development purposes. Purpose: The purpose of this manual is to help users understand the hardware capabilities of the µ PD78214 sub-series.
PD78P214 PD78P214(A) µ µ PD78214 PD78214(A) µ µ PD78213 PD78213(A) µ µ PD78212 PD78212(A) µ µ PROM 16K RAM 512 ROM 16K RAM 512 ROM-less RAM 512 ROM 8K RAM 384 To check the details of a register when you know the name of the register: See Appendix D .
Never use the code combinations indicated "Not to be set" in the register descriptions. Characters likely to be confused: 0 (zero) and O (uppercase "O") 1 (one), l (lowercase "L"), and I (uppercase "I") Related documents: The following reference documents are also available.
• Documents related to development tools IE-78210-R In-Circuit Emulator System Software Operator's Manual CC78K Series C Compiler User's Manual Document No.
• Other documents Document No. IEI-1213 IEI-1207 IEI-1209 IEI-1203 MEI-1202 Document name Package Manual SMD Surface Mount Technology Manual Quality Grades on NEC Semiconductor Devices NEC Semicondu.
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- i - Contents CONTENTS CHAPTER 1 GENERAL ........................................................................................................................................ 1 1.1 FEATURES .........................................................
- ii - Contents 3.3 NOTES ................................................................................................................................... 53 CHAPTER 4 CLOCK GENERATOR ................................................................
- iii - Contents Preface 5.8.4 Built-In Pull-Up Resistor .......................................................................................... 93 5.8.5 Notes ........................................................................................
- iv - Contents 7.4.6 Sample Applications .................................................................................................. 211 7.5 NOTES ................................................................................................
- v - Contents 10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE .................................................. 26 5 10.4.1 Basic Operation Timing .......................................................................................... 2 65 10.4.
- vi - Contents 12.3.4 Multiplexed-Interrupt Handling .............................................................................. 3 13 12.3.5 Interrupt Request and Macro Service Pending .................................................... 316 12.3.
- vii - Contents CHAPTER 16 APPLICATION EXAMPLES ............................................................................................................ 395 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS ................................................
- viii - Contents LIST OF FIGURES Fig. No. Title, Page 2-1 I/O Circuits Provided for Pins ....................................................................................................... 3 4 3-1 Memory Map of µ PD78212 (EA Pin Driven High) ...
- ix - Contents Fig. No. Title, Page 5-25 Connection of Pull-Up Resistors (Port 4) ................................................................................... 79 5-26 Example of Driving an LED Directly .........................................
- x - Contents Fig. No. Title, Page 7-16 Example of Rewriting Compare Register CR00 ......................................................................... 1 24 7-17 Example of PWM Output Signal with a 100% Duty Factor ..............................
- xi - Contents 7-62 Timing of Pulse Width Measurement ......................................................................................... 156 7-63 Setting of Control Registers for Pulse Width Measurement ........................................
- xii - Contents 7-106 Interrupt Request Handling for Pulse Width Calculation ......................................................... 1 97 7-107 Example of PWM Signal Output by 8-Bit Timer/Counter 2 ..................................................
- xiii - Contents 8-9 Software-Started Scan-Mode A/D Conversion .......................................................................... 2 35 8-10 Example of Malfunction in a Hardware-Started A/D Conversion ..........................................
- xiv - Contents 11-1 Format of External Interrupt Mode Register 0 (INTM0) ........................................................... 294 11-2 Format of External Interrupt Mode Register 1 (INTM1) ......................................................
- xv - Contents 13-1 Format of the Memory Expansion Mode Register (MM) ......................................................... 3 46 13-2 Format of Programmable Wait Control Register (PW) ............................................................. 3 47 13-3 Read Timing .
- xvi - Contents 17-1 Timing Chart for PROM Write and Verify .................................................................................. 40 0 17-2 Write Operation Flowchart .......................................................................
- xvii - Contents LIST OF TABLES Table No. Title, Page 2-1 Port 2 Functions ............................................................................................................................. 2 7 2-2 Port 3 Operating Mode ...................
- xviii - Contents 8-1 Modes Generating the INTAD ...................................................................................................... 225 8-2 A/D Conversion Time ......................................................................
1 1 CHAPTER 1 GENERAL The µ PD78214 sub-series is part of the 78K/II series of eight-bit single-chip microcomputers capable of accessing an expanded memory space of 1 megabyte.
2 µ PD78214 Sub-Series 78K/II Products The following are contained: A / D converter D/A converter The PWM output function is added. The macro service and timer/ counter are enhanced. The comparator is deleted. PD78234 sub-series µ The D/A converter is contained.
3 Chapter 1 General 1 1.1 FEATURES ° 78K/II series ° Multiplexed internal bus (faster execution of instructions) Minimum instruction cycle (operating at 12 MHz): 333 ns ( µ PD78212, µ PD78214, and.
4 µ PD78214 Sub-Series 1.2 ORDERING INFORMATION AND QUALITY GRADE 1.2.1 Ordering Information Ordering code Package Internal ROM µ PD78212CW- ××× 64-pin plastic shrink DIP (750 mil) Masked ROM µ .
5 Chapter 1 General 1 1.2.2 Quality Grade Ordering code Package Quality grade µ PD78212CW- ××× 64-pin plastic shrink DIP (750 mil) Standard µ PD78212GC- ××× -AB8 64-pin plastic QFP (14 × 14 m.
6 µ PD78214 Sub-Series 1.3 PIN CONFIGURATION (TOP VIEW) 1.3.1 Normal Operating Mode (1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window 1 2 3 4 5 6 7 8 9 10 11 1.
7 Chapter 1 General 1 (2) 68-pin plastic QFJ Remark The NC pin is not connected inside the chip. 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 P70/AN0 P34/TO0 P35/TO1 P36/TO2 P37/TO3 P00 P01 P02 .
8 µ PD78214 Sub-Series (3) 64-pin plastic QFP (14 × 14 mm) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 P64/RD P63/A19 P62/A18 P61/A17 P60/A16 RESET X2 X1 V SS P57/A15 P56/A14 P55/A13 P54/A12 P53/A11 P52/.
9 Chapter 1 General 1 (4) 74-pin plastic QFP (20 × 20 mm) Remark The NC pins are not connected inside the chip. P65/WR P66/W AIT/AN6 P67/REFRQ/AN7 P07 NC P06 P05 P04 P03 NC P02 P01 P00 P37/T O3 P36/T.
10 µ PD78214 Sub-Series P00-P07 : Port 0 P20-P27 : Port 2 P30-P37 : Port 3 P40-P47 : Port 4 P50-P57 : Port 5 P60-P67 : Port 6 P70-P75 : Port 7 TO0-TO3 : Timer output CI : Clock input RxD : Receive da.
11 Chapter 1 General 1 1.3.2 PROM Programming Mode (P20/NMI = 12.5 V, RESET = L) (1) 64-pin plastic shrink DIP, 64-pin plastic QUIP, 64-pin ceramic shrink DIP with window Caution The symbols enclosed .
12 µ PD78214 Sub-Series (2) 68-pin plastic QFJ Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be ha ndled as follows: L : Connect the corresponding pin independently to V SS , through a 10-k Ω resistor.
13 Chapter 1 General 1 (3) 64-pin plastic QFP (14 × 14 mm) Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be ha ndled as follows: L : Connect the corresponding pin independently to V SS , through a 10-k Ω resistor.
14 µ PD78214 Sub-Series (4) 74-pin plastic QFP (20 × 20 mm) Caution The symbols enclosed in parentheses indicate that the corresponding pins, not used in PROM programming mode, shall be ha ndled as follows: L : Connect the corresponding pin independently to V SS , through a 10-k Ω resistor.
15 Chapter 1 General 1 V PP : Programming power supply RESET : Reset D0-D7 : Data bus A0-A14 : Address bus V SS : Ground OE : Output enable V DD : Power supply CE : Chip enable P20/NMI : Port 2/non-ma.
16 µ PD78214 Sub-Series 1.4 EXAMPLE APPLICATION SYSTEM (PRINTER) M P00-P03 M P04-P07 TO SCK SO T X D R X D Ports AV REF AV SS AN0 AN1 AN2-AN7 Temperature sensor Motor supply voltage SW input for each.
17 Chapter 1 General 1 1.5 BLOCK DIAGRAM Notes 1. None for µ PD78213 and µ PD78213(A), 8KB for µ PD78212 and µ PD78212(A), 16KB for µ PD78214, µ PD78P214, µ PD78214(A) 2.
18 µ PD78214 Sub-Series 1.6 FUNCTIONS Item Input pins Output pins I/O pins Total Connected to a pull-up resistor Driving a LED directly Driving a transistor directly 65 µ PD78213 µ PD78212 µ PD782.
19 Chapter 1 General 1 Item A/D converter Interrupt Instruction set Package µ PD78213 µ PD78212 µ PD78214 µ PD78P214 Eight channels, each having a resolution of eight bits • 19 interrupts (seven.
20 µ PD78214 Sub-Series Product Item RAM capacity I/O pins Timer/counter Serial interface Interrupt A/D converter Package Others µ PD78213 512 bytes • Software programmable pull-up resistors: Supp.
21 Chapter 1 General 1 Series name µ PD78214 Sub-Series µ PD78218A Sub-Series µ PD78214 µ PD78214(A) µ PD78218A Product µ PD78212 µ PD78212(A) µ PD78213 µ PD78213(A) µ PD78P214 µ PD78P214(A.
22 µ PD78214 Sub-Series Product Item Quality grade Package Standard • 64-pin plastoc shrink DIP • 64-pin plastic QFP • 74-pin plastic QFP µ PD78212 µ PD78212(A) Special • 64-pin plastoc shr.
23 Chapter 1 General 1 Product name Parameter Internal ROM Internal RAM Port 4 Port 5 Port 6 Others 8KB masked ROM at 00000H to 01FFFH 384 bytes at 0FD80H to 0FEFFH Used as both general-purpose I/O po.
24.
25 2 CHAPTER 2 PIN FUNCTIONS 2.1 PIN FUNCTION LIST 2.1.1 Normal Operating mode (1) Ports P20 P21 P22 P23 P24 P25 P26 P27 P30 P31 P32 P33 P34-P37 P60-P63 P64 Note 2 P65 Note 2 P66 P67 P70-P75 Port 0 (P0): Can be used as two four-bit, real-time output ports.
26 µ PD78214 Sub-Series (2) Pins other than those which function as ports TO0-TO3 CI RxD TxD ASCK SB0 SI SO SCK NMI INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 AD0-AD7 A8-A15 A16-A19 RD WR WAIT ASTB REFRQ RE.
27 Chapter 2 Pin Functions 2 2.1.2 PROM Programming Mode (only for the µ PD78P214, P20/NMI = 12.5 V, RESET = L) Pin P20/NMI RESET A0-A14 D0-D7 CE OE V PP V DD V SS NC Function Address bus Data bus PR.
28 µ PD78214 Sub-Series (a) When functioning as a port Signals applied to these pins can be read and these pins can be tested, regardless of whether these pins are acting as secondary function pins.
29 Chapter 2 Pin Functions 2 Table 2-2 Port 3 Operating Mode (n = 0 to 7) P30 P31 P32 P33 P34 P35 P36 P37 RxD input TxD output SCK input/output SO output/SB0 input/output TO0 output TO1 output TO2 out.
30 µ PD78214 Sub-Series (6) P60 to P67 (port 6): Output (P60 to P63) and tristate inputs/outputs (P64 to P67) Port 6 is an eight-bit I/O port with output latches. Pins P64 to P67 are provided with software-programmable pull-up resistors. The pins of port 6 also function as control signal input pins, as listed in Table 2-3.
31 Chapter 2 Pin Functions 2 (8) ASTB (address strobe): Output Timing signal output used for latching addresses externally to enable access to external memory. (9) EA (external access): Input Control signal input used for switching the program memory from the internal ROM to the external memory.
32 µ PD78214 Sub-Series (9) V SS Ground. (10) NC (non-connection) Not connected inside the chip..
33 Chapter 2 Pin Functions 2 2.3 I/O CIRCUITS AND UNUSED-PIN HANDLING Table 2-4 lists the types of I/O circuits provided for each pin and describes how pins are handled when not used.
34 µ PD78214 Sub-Series Fig. 2-1 I/O Circuits Provided for Pins Type 1 IN V DD P N Type 2 IN Schmitt trigger input with hysteresis characteristics Type 4 Data V DD P N OUT Output disable Push-pull output which can output high impedance (both the positive and negative channels are off.
35 Chapter 2 Pin Functions 2 2.4 NOTES (1) While the RESET signal is being applied, pins P60 to P63 are high impedance. When the RESET signal is released, the output of these pins is low level. Design the peripheral circuit so that it operates satisfactorily when pins P60 to P63 initially output the low level.
36.
37 3 CHAPTER 3 CPU FUNCTION 3.1 MEMORY SPACE The µ PD78214 can access a memory space of up to 1M byte. Figs. 3-1 to 3-4 show the corresponding memory maps. The mapping of program memory depends on the status of the EA pin. The EA pin of the µ PD78213 must be tied low.
38 µ PD78214 Sub-Series Fig. 3-1 Memory Map of µ PD78212 (EA Pin Driven High) Notes 1. Accessed in 1M-byte expansion mode. 2. External SFR area Remark The shaded areas indicate internal memory.
39 Chapter 3 CPU Function 3 Fig. 3-2 Memory Map of µ PD78212 (EA Pin Driven Low) Notes 1. Accessed in 1M-byte expansion mode. 2. External SFR area Remark The shaded areas indicate internal memory.
40 µ PD78214 Sub-Series Fig. 3-3 Memory Map of µ PD78213, µ PD78214, or µ PD78P214 (EA Pin Driven Low) Notes 1. Accessed in 1M-byte expansion mode.
41 Chapter 3 CPU Function 3 Fig. 3-4 Memory Map of µ PD78214, µ PD78P214 (EA Pin Driven High) Notes 1. Accessed in 1M-byte expansion mode. 2. Accessed in external memory expansion mode 3. External SFR area Remark The shaded areas indicate internal memory.
42 µ PD78214 Sub-Series 3.1.1 Internal Program Memory Area In the area from 00000H to 03FFFH (00000H to 01FFFH for the µ PD78212), a 16K × 8 bit ROM (8K × 8 bit ROM for the µ PD78212) is incorporated. Programs and table data are stored in this area.
43 Chapter 3 CPU Function 3 3.1.2 Internal RAM Area A 512-byte (384-byte for the µ PD78212) general-purpose static RAM is incorporated into the area from 0FD00H to 0FEFFH.
44 µ PD78214 Sub-Series To access the space, specify the bank to be used (high-order four bits of address, A16 to A19) in the bank register (P60 to P63 of register P6, or PM60 to PM63 of register PM6). Then, execute an instruction which allows extended addressing.
45 Chapter 3 CPU Function 3 3.2 REGISTERS 3.2.1 Program Counter (PC) This 16-bit binary counter holds the address of the program to be executed next (see Fig. 3-6 ). Usually, the address is automatically incremented according to the number of bytes of the instruction to be fetched.
46 µ PD78214 Sub-Series (3) Register bank selection flags (RBS0, RBS1) These two flags are used to select one of four register banks (see Table 3-2 ). The flags hold two-bit information indicating the register bank selected by the SEL RBn instruction.
47 Chapter 3 CPU Function 3 Fig. 3-9 Data Saved to the Stack Area Fig. 3-10 Data Restored from the Stack Area PUSH rp instruction Stack Register pair, low Register pair, high SP – 2 SP – 1 SP ⇒ .
48 µ PD78214 Sub-Series Fig. 3-11 Configuration of General-Purpose Registers A E1H B E3H D E5H H E7H A E9H B EBH D EDH H EFH A F1H B F3H D F5H H F7H A F9H B FBH D FDH H FFH X E0H C E2H E E4H L E6H X .
49 Chapter 3 CPU Function 3 (2) Function General-purpose registers can be operated in units of eight bits. They can also be operated in units of 16 bits, that is, a pair of eight-bit registers can be operated as a single unit (AX, BC, DE, HL).
50 µ PD78214 Sub-Series 3.2.5 Special Function Registers (SFR) A mode register, control register, and other registers with special functions, which are built-in hardware peripherals, are mapped into the 256-byte space from 0FF00H to 0FFFFH. Caution Never access an address to which no SFR is mapped in this area.
51 Chapter 3 CPU Function 3 0FF00H 0FF02H 0FF03H 0FF04H 0FF05H 0FF06H 0FF07H 0FF0AH 0FF0BH 0FF0CH 0FF10H 0FF11H 0FF12H 0FF13H 0FF14H 0FF15H 0FF16H 0FF17H 0FF18H 0FF19H 0FF1AH 0FF1CH 0FF20H 0FF23H 0FF2.
52 µ PD78214 Sub-Series 0FF50H 0FF51H 0FF52H 0FF54H 0FF56H 0FF5CH 0FF5DH 0FF5EH 0FF5FH 0FF68H 0FF6AH 0FF80H 0FF82H 0FF86H 0FF88H 0FF8AH 0FF8CH 0FF8EH 0FF90H 0FFC0H 0FFC4H 0FFC5H 0FFC6H 0FFD0H 0FFDFH .
53 Chapter 3 CPU Function 3 3.3 NOTES (1) A program fetch from the internal RAM area is prohibited. (2) Operation of the stack pointer In stack addressing, the entire 64K bytes can be accessed. No stack area can be mapped into the SFR area or internal ROM area.
54.
55 4 CHAPTER 4 CLOCK GENERATOR 4.1 CONFIGURATION AND FUNCTION A clock generator generates and controls the internal system clock (CLK) sent to the CPU.
56 µ PD78214 Sub-Series Remark Different uses of the crystal and ceramic resonator Generally, a crystal’s oscillation frequency is quite stable. Crystals are ideal for high-precision time management (for example, clock or frequency measurement).
57 Chapter 4 Clock Generator 4 Fig. 4-4 Notes on Connection of the Oscillator X2 PD78214 µ X1 V SS Cautions 1. Place the oscillator as close as possible to pins X1 and X2. 2. Do not let other signal lines cross the circuit enclosed in a dashed line. Fig.
58 µ PD78214 Sub-Series ( c) A varying high current flows too close to the signal line. (d) A current flows through the ground line of the oscillator. (The potentials vary at points A, B, and C.) (e) A signal is being drawn from the oscillator. (2) At power-on or return from STOP mode, some time is required for the oscillation to settle.
59 5 CHAPTER 5 PORT FUNCTIONS 5.1 DIGITAL I/O PORTS The µ PD78214 has the ports shown in Fig. 5-1. These ports can be used for various types of control. Table 5-1 lists the function of each port. For ports 2 through 6, software can specify whether to use a built-in pull-up resistor for inputs.
60 µ PD78214 Sub-Series Table 5-1 Port Functions Port 0 Port 2 Port 3 Port 4 Note Port 5 Note Port 6 Note Port 7 Software-specified pull-up resistor Name Pin name P00-P07 P20-P27 P30-P37 P40-P47 P50-P57 P60-P63 P64-P67 P70-P75 Function Can be specified for either output in 8-bit units or high impedance.
61 Chapter 5 Port Functions 5 5.2.1 Hardware Configuration Fig. 5-2 shows the hardware configuration of port 0. Fig. 5-2 Configuration of Port 0 5.2.2 Setting the Input/Output Mode and Control Mode The port 0 mode register (PM0) sets the I/O mode of port 0, as shown in Fig.
62 µ PD78214 Sub-Series 5.2.3 Operation Port 0 is an output-only port. Once port 0 is put in the output mode, the output latch becomes operable, enabling data transfer between the output latch and accumulator according to a transfer instruction. The output latch can be loaded with any data by a logical operation instruction.
63 Chapter 5 Port Functions 5 5.3 PORT 2 Port 2 is an 8-bit input-only port. P22 through P27 have a software-programmable built-in pull-up resistor. In addition to functioning as an input port, port 2 functions as a control signal input pin such as for external interrupts (see Table 5-3 ).
64 µ PD78214 Sub-Series 5.3.1 Hardware Configuration Fig. 5-6 shows the configuration of port 2 Fig. 5-6 Block Diagram of Port 2 Note P20 or P21 does not have a circuit enclosed in a dotted box. 5.3.2 Setting the Input Mode and Control Mode Port 2 is an input-only port.
65 Chapter 5 Port Functions 5 Fig. 5-7 Port Specified as an Input Port Caution For the in-circuit emulator, the level of each port 2 pin from which noise has not been removed can be read and tested. 5.3.4 Built-In Pull-Up Resistor P22 through P27 have built-in pull-up resistors.
66 µ PD78214 Sub-Series Fig. 5-9 Connection of Pull-Up Resistors (Port 2) Caution P22 through P26 are not pulled up immediately after a reset. In this case, INTP1 through INTP5 (one of the multiple fun ctions assigned to P22 to P26) may set interrupt request flags.
67 Chapter 5 Port Functions 5 Table 5-4 Port 3 Operating Modes (n = 0 through 7) Condition P30 P31 P32 P33 P34 P35 P36 P37 Mode Control signal I/O mode PMC3n = 1 RxD input TxD output SCK I/O SO output.
68 µ PD78214 Sub-Series 5.4.1 Hardware Configuration Fig. 5-10 through 5-13 show the configuration of port 3. Fig. 5-10 Block Diagram of P30 (Port 3) P30 Internal bus WR PM30 Port 3 mode register PM3.
69 Chapter 5 Port Functions 5 Fig. 5-11 Block Diagram of P31, and P34 through P37 (Port 3) Internal bus RD PUO WR PUO WR PM3n Port 3 mode register PM3n WR PMC3n PMC3n WR P3n P3n RD PMC3n RD P3n Pull-u.
70 µ PD78214 Sub-Series Fig. 5-12 Block Diagram of P32 (Port 3) ★ Internal bus RD P32 P32 RD PUO WR PUO Pull-up resistor option register PUO3 WR PM32 Port 3 mode register PM32 WR PMC32 PMC32 RD PMC.
71 Chapter 5 Port Functions 5 Fig. 5-13 Block Diagram of P33 (Port 3) ★ 5.4.2 Setting the I/O Mode and Control Mode The port 3 mode register (PM3) can put each pin of port 3 in either the input or output mode independently of the other pins, as shown in Fig.
72 µ PD78214 Sub-Series Fig. 5-14 Port 3 Mode Register Format Fig. 5-15 Port 3 Mode Control Register (PMC3) Format PM37 7 PM36 6 PM35 5 PM34 4 PM33 3 PM32 2 PM31 1 PM30 0 PM3 PM3n Input mode (output .
73 Chapter 5 Port Functions 5 5.4.3 Operation Port 3 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 3 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can be transferred between the output latch and the accumulator using a transfer instruction.
74 µ PD78214 Sub-Series (3) Control signal input or output Regardless of setting of the port mode 3 register (PM3), each bit of port 3 can be used to input or output a control signal, independently of the other bits, by setting the corresponding bit of the port mode control register (PMC3) to 1.
75 Chapter 5 Port Functions 5 Fig. 5-20 Connection of Pull-Up Resistors (Port 3) 5.5 PORT 4 Port 4 is an 8-bit I/O port with an output latch. The memory expansion mode register (MM) can put all 8 bits of this port in either the input or output mode at one time.
76 µ PD78214 Sub-Series 5.5.1 Hardware Configuration Fig. 5-21 shows the hardware configuration of port 4. Fig. 5-21 Block Diagram of Port 4 5.5.2 Setting the I/O Mode and Control Mode The memory expansion mode register (MM, see Fig 13-1 ) specifies the operating mode of port 4, as listed in Table 5-5.
77 Chapter 5 Port Functions 5 5.5.3 Operation Port 4 is an I/O port. It functions also as an address/data bus (AD0 through AD7). (1) Output port When port 4 is in the output mode, its output latch is operable. Once the output latch becomes operable, data can be transferred between the output latch and the accumulator using a transfer instruction.
78 µ PD78214 Sub-Series (3) Address/data bus (AD0 through AD7) Port 4 is used as the address/data automatically for external access. Do not execute I/O instructions for port 4. 5.5.4 Built-In Pull-Up Resistor Port 4 has built-in pull-up resistors. When port 4 must be pulled up, the built-in pull-up resistors should be used.
79 Chapter 5 Port Functions 5 Fig. 5-25 Connection of Pull-Up Resistors (Port 4) 5.5.5 Driving LEDs Directly For port 4, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directly on an active-low signal.
80 µ PD78214 Sub-Series 5.6 PORT 5 Port 5 is an 8-bit I/O port with an output latch. The port 5 mode register (PM5) can put each bit of this port in either the input or output mode, independently of the other bits. Each pin has a software-programmable built-in pull- up resistor, and can drive an LED directly.
81 Chapter 5 Port Functions 5 Fig. 5-28 Port 5 Mode Register Format Table 5-6 Port 5 Operating Modes 1 1 0 0 1 × MM2 0 1 × MM1 × 1 × MM0 EA pin MM register bit Operation mode I/O port Address/data bus (A8-A15) For the µ PD78213, port 4 functions only as the address/data bus (AD8 through AD15).
82 µ PD78214 Sub-Series Fig. 5-30 Port Specified as an Input Port Caution Although its ultimate purpose is to manipulate only 1 bit, a bit manipulation instruction accesses a port in 8-bit units.
83 Chapter 5 Port Functions 5 Fig. 5-32 Connection of Pull-Up Resistors (Port 5) 5.6.5 Driving LEDs Directly For port 5, the low level side of the output buffer has an enhanced driving capacity so that it can drive an LED directly on an active-low signal.
84 µ PD78214 Sub-Series 5.7 PORT 6 Port 6 is an 8-bit I/O port with an output latch. P64 through P67 have a software-programmable built-in pull-up resistor. In addition to the port functions, port 5 works as I/O pins for various control signals as listed in Table 5-7.
85 Chapter 5 Port Functions 5 (vi) AN6 and AN7 (analog input) These pins receive analog signals for the A/D converter. 5.7.1 Hardware Configuration Fig.
86 µ PD78214 Sub-Series Fig. 5-35 Block Diagram of P64 and P65 (Port 6) Internal bus P64 (P65) V DD RD IN Selector RD PUO WR PUO Pull-up resistor option register PUO6 Port 6 mode register P64 (P65) W.
87 Chapter 5 Port Functions 5 Fig. 5-36 Block Diagram of P66 (Port 6) Internal bus P66 V DD RD IN RD PUO WR PUO Pull-up resistor option register PUO6 Port 6 mode register PM66 WR PM66 Output latch WR .
88 µ PD78214 Sub-Series Fig. 5-37 Block Diagram of P67 (Port 6) 5.7.2 Setting the I/O Mode and Control Mode The port 6 mode register (PM6) can put port 6 in either the input or output mode as shown in Fig. 5-38. Table 5- 8 lists the operations needed to make port 6 function as control pins.
89 Chapter 5 Port Functions 5 Cautions 1. To use P60 through P63 as an output port, it is necessary to reset the PM60 through PM63 bits to 0. If they are not 0, the in- circuit emulator may not work. 2. To use the P66/WAIT pin as the WAIT pin, it is necessary to put P66 in the input mode using the PM6 register.
90 µ PD78214 Sub-Series 5.7.3 Operation Port 6 is an I/O port. Its pins also function as control signal pins. (1) Output port When port 6 is in the output mode, the contents of its output latch are output, and data can be transferred between the output latch and the accumulator using a transfer instruction.
91 Chapter 5 Port Functions 5 (3) Control pins When port 6 function as control pins, they cannot be manipulated or tested by software. (4) Analog inputs (P66 and P67 only) When port 6 is used as analog input pins (AN6 and AN7), the level of each pin can be read and tested.
92 µ PD78214 Sub-Series 5.7.5 Note When P66 and P67 are used as analog input pins AN6 and AN7 respectively or when A/D conversion is not performed, do not apply a voltage out of the range AV SS through AV REF to these pins, if AN6 and AN7 are selected for ANI0 through ANI2 of the A/D converter mode register (ADM).
93 Chapter 5 Port Functions 5 5.8.3 Operation Port 7 is an input-only port, and the level of its pins can be read and tested. Fig. 5-44 Port Specified as an Input Port Internal bus RD IN P7n n = 0 to 5 5.8.4 Built-In Pull-Up Resistor Port 0 has no built-in pull-up resistor.
94 µ PD78214 Sub-Series (4) P22 through P26 are not pulled up immediately after a reset, and the interrupt request flag may be set depending on the function of a dual-function pin (INTP1 through INTP5). Therefore, specify connection of a pull-up resistor in the initialization routine, before clearing the interrupt request flag.
95 6 CHAPTER 6 REAL-TIME OUTPUT FUNCTION 6.1 CONFIGURATION AND FUNCTION The real-time output function is implemented by the hardware centering around port 0 and the buffer register (P0H and P0L) as shown in Fig.
96 µ PD78214 Sub-Series Fig. 6-1 Block Diagram of the Real-Time Output Port 4 4 4 P00 P01 P02 P03 P04 P05 P06 P07 INTP0 P0ML INTC10 Selector Selector P0MH P0ML EXTR P0MH BYTE INTC11 4 P0L P0H Buffer .
97 Chapter 6 Real-Time Output Function 6 6.2 REAL-TIME OUTPUT CONTROL REGISTER (RTPC) The real-time output control register (RTPC) is an 8-bit register to specify the functions of port 0. An 8-bit manipulation instruction and a bit manipulation instruction can be used to read data from and write data to the RTPC register.
98 µ PD78214 Sub-Series Table 6-1 Port 0 Operating Modes and Operations Needed for the Port 0 Buffer Registers 8-bit port mode 8-bit real-time output port mode 4-bit separate real-time output port mo.
99 Chapter 6 Real-Time Output Function 6 6.4 OPERATION When port 0 is in the real-time output port mode, the contents of the buffer registers (P0H and P0L) are sent to the output latches for output to the pins of port 0 in synchronization with the occurrence of a trigger condition listed in Table 6-2.
100 µ PD78214 Sub-Series Fig. 6-4 Real-Time Output Port Operation Timing D02 D03 D02 D01 D00 D01 D03 D04 0H CR11 CR11 CR11 CR11 FFH Timer starts INTC11 interrupt request CPU operation Buffer register.
101 Chapter 6 Real-Time Output Function 6 Fig. 6-5 Real-Time Output Port Operation Timing (Controlling 2 Channels Independently of Each Other) 8-bit timer/ counter 1 Timer starts 0H INTC11 interrupt r.
102 µ PD78214 Sub-Series 6.5 APPLICATION EXAMPLE This section describes an example of application in which P00 through P03 are used as a 4-bit real-time output port. Each time TM1 for 8-bit timer/counter 1 coincides with the contents of CR10, the contents of the P0L are output to P00 through P03.
103 Chapter 6 Real-Time Output Function 6 Fig. 6-7 Contents of the Control Register for the Real-Time Output Function 76 54 321 0 00 000 0 01 RTPC Uses pins P00 to P03 as real-time output ports Disabl.
104 µ PD78214 Sub-Series Fig. 6-9 Interrupt Request Handling When the Real-Time Output Function Is Used 6.6 NOTES (1) When the P0ML or P0MH is set to 1, the output buffer for the corresponding output port is turned on to output the contents of the port 0 output latch, regardless of the contents of the port 0 mode register (PM0).
105 Chapter 6 Real-Time Output Function 6 (4) With an in-circuit emulator, digital noise cannot be eliminated normally from the INTP0 pin. When it is specified that data transfer from the buffer register to the output latch be performed according to a signal from the INTP0 pin, data transfer may occur according to an erroneously detected edge.
106.
107 7 CHAPTER 7 TIMER/COUNTER UNITS The µ PD78214 contains one 16-bit timer/counter unit (channel) and three 8-bit timer/counter units (channels). Table 7-1 Timer/Counter Types and Functions Unit Typ.
108 µ PD78214 Sub-Series Fig. 7-1 Block Diagrams of Timer/Counter Units 16-bit timer/counter unit f CLK /8 Timer register TM0 Compare register CR00 OVF Compare register CR01 Capture register CR02 Coi.
109 Chapter 7 Timer/Counter Units 7 7.1 16-BIT TIMER/COUNTER 7.1.1 Functions The 16-bit timer/counter can function as an interval timer and can also be used for programmable square wave output and pulse width measurement.
110 µ PD78214 Sub-Series Fig. 7-2 Block Diagram of 16-Bit Timer/Counter 8 CLR01 Compare register (CR01) 8 ENTO1 16 ALV0 ENTO0 ALV1 Internal bus Timer output control register (TOC) P34/TO0 P35/TO1 INT.
111 Chapter 7 Timer/Counter Units 7 (1) 16-bit timer 0 (TM0) TM0 is a count-up timer using a count clock of f CLK /8. The count operation of TM0 can be enabled or disabled by timer control register 0 (TMC0). TM0 allows only read operation using a 16-bit manipulation instruction.
112 µ PD78214 Sub-Series Fig. 7-3 Format of Timer Control Register 0 (TMC0) 765 4 3 2 1 0 CE3 0 0 0 CE0 OVF0 0 0 TMC0 OVF0 0 1 1 0 CE0 TM0 overflow flag Overflow does not occur Overflow occurs (count.
113 Chapter 7 Timer/Counter Units 7 (3) Timer output control register (TOC) The TOC register is an 8-bit register for specifying the active level of timer output and for enabling/disabling timer output. The lower 4 bits control the timer output operation (on the TO0 and TO1 pins) of the 16-bit timer/counter.
114 µ PD78214 Sub-Series 7.1.4 Operation of 16-Bit Timer 0 (TM0) (1) Basic operation The 16-bit timer/counter performs count operation by counting up with a count clock of f CLK /8. When the RESET signal is applied, TM0 is cleared to 0000H, and count operation stops.
115 Chapter 7 Timer/Counter Units 7 (c) When the value of TM0 is FFFFH Count clock f CLK /8 TM0 Cleared by software OVF0 FFFEH FFFFH 0H 1H OVF0 ← 0 (2) Clear operation After a coincidence with the CR01 compare register, 16-bit timer 0 (TM0) can be automatically cleared.
116 µ PD78214 Sub-Series Fig. 7-8 Clear Operation When the CE0 Bit Is Reset to 0 (a) Basic operation TM0 CE0 n-1 n 0 Count clock (b) Restart after 0 is set in TM0 cleared Count clock TM0 CE0 n-1 n 0 0 1 When the CE0 bit is set to 1 after this count clock, counting starts from 0 on the count clock input after the CE0 bit has been set.
117 Chapter 7 Timer/Counter Units 7 7.1.5 Compare Register and Capture Register Operations (1) Compare operation The 16-bit timer/counter performs an operation to compare the values set in the compare registers with timer count values.
118 µ PD78214 Sub-Series Fig. 7-10 TM0 Cleared After a Coincidence Is Detected Remark CLR01 = 1 (2) Capture operation The 16-bit timer/counter performs a capture operation to load the count value of the timer into the capture register in synchronism with an external trigger.
119 Chapter 7 Timer/Counter Units 7 Fig. 7-11 Capture Operation Remark Dn: TM0 count value (n = 0, 1, 2, ...) CLR01 = 0 Caution With an in-circuit emulator, digital noise on the INTP3 pin cannot be removed correctly. When the capture function is u sed, the operation described below is performed if an edge is detected erroneously.
120 µ PD78214 Sub-Series Table 7-5 Timer Output (TO0, TO1) Operation TOC 0 0 1 1 0 1 1 0 1 1 0 1 1 ENTO1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 AL V1 0 1 0 1 1 0 1 1 0 1 1 0 1 ENTO0 0/1 .
121 Chapter 7 Timer/Counter Units 7 (1) Basic operation By setting ENTOn (n = 0, 1) of the timer output control register (TOC) to 1, the timer outputs (TO1, TO0) can be changed with the timing determined by MOD0, MOD1, and CLR01 of capture/compare control register 0 (CRC0).
122 µ PD78214 Sub-Series 7.1.7 PWM Output The PWM output function outputs a PWM signal whose period coincides with the full-count period of 16-bit timer 0 (TM0). The pulse width of TO0 is determined by the value of CR00, and the pulse width of TO1 is determined by the value of CR01.
123 Chapter 7 Timer/Counter Units 7 Fig. 7-14 Example of PWM Output Using TM0 Remark ALV0 = 0, ALV1 = 0 Fig. 7-15 PWM Output When CR00 = FFFFH Remark ALV0 = 0 FFFFH INTO00 FFFFH FFFFH FFFFH FFFFH TO0 TM0 count value Count clock period T OVF flag Duty factor = × 100 = 99.
124 µ PD78214 Sub-Series Even if the value of a compare register (CR00, CR01) coincides with the value of 16-bit timer 0 (TM0) more than once during one period of PWM output, the output levels on the timer outputs (TO0, TO1) do not change.
125 Chapter 7 Timer/Counter Units 7 2. If timer output is disabled (ENTOn = 0: n = 0, 1), the output level on the TOn (n = 0, 1) pin is the inverted value of the value set in ALVn (n = 0, 1). Accordingly, note that if timer output is disabled when the PWM output function is selected, the active level is output.
126 µ PD78214 Sub-Series Fig. 7-19 PPG Output When CR00 = CR01 Fig. 7-20 PPG Output When CR00 = 0000H Remark ALV0 = 0 1 2 nn n INTC00 INTC01 TO0 TM0 count value n-1 0 n-1 2 1 0 0 Count period T Pulse.
127 Chapter 7 Timer/Counter Units 7 Even if the value of the CR00 compare register coincides with the value of 16-bit timer 0 (TM0) more than once during one period of PPG output, the output levels on the timer outputs (TO0, TO1) are not inverted. Fig.
128 µ PD78214 Sub-Series 2. If the current value of the CR01 compare register is decreased below the value of 16-bit timer 0 (TM0), the PPG period becomes as long as the full-count time of TM0.
129 Chapter 7 Timer/Counter Units 7 7.1.9 Sample Applications (1) Interval timer operation (1) By free running 16-bit timer 0 (TM0), and adding a value to a compare register (CR00, CR01) in an interrupt handling routine, the 16-bit timer/counter can be used as an interval timer whose period is as long as the added value.
130 µ PD78214 Sub-Series Fig. 7-25 Setting of Control Registers for Interval Timer Operation (1) (a) Timer control register 0 (TMC0) (b) Capture/compare control register 0 (CRC0) 76 54 321 0 00 0 0 00 0 1 CRC0 Disables clearing TM0 Both TO0 and TO1 are used for toggle output Fig.
131 Chapter 7 Timer/Counter Units 7 Fig. 7-27 Interrupt Request Handling for Interval Timer Operation (1) (2) Interval timer operation (2) The 16-bit timer/counter can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand.
132 µ PD78214 Sub-Series Fig. 7-29 Setting of Control Registers for Interval Timer Operation (2) (a) Timer control register 0 (TMC0) 76 54 3 2 1 0 00 0 0 10 0 1 CRC0 Clears TM0 when CR01 coincides with TM0 Both TO0 and TO1 are used for toggle output (b) Capture/compare control register 0 (CRC0) Fig.
133 Chapter 7 Timer/Counter Units 7 Fig. 7-31 Timing of Pulse Width Measurement Remark D n : TM0 count value (n = 0, 1, 2, ...) Fig. 7-32 Setting of Control Registers for Pulse Width Measurement (a) T.
134 µ PD78214 Sub-Series (c) External interrupt mode register 1 (INTM1) Fig. 7-33 Setting Procedure for Pulse Width Measurement Fig. 7-34 Interrupt Request Handling for Pulse Width Calculation Pulse .
135 Chapter 7 Timer/Counter Units 7 (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare register is output. (See Fig. 7-35 .) The duty factor of a PWM output signal can be changed in steps of 1/65536 from 1/65536 to 65535/65536.
136 µ PD78214 Sub-Series Fig. 7-37 Setting Procedure for PWM Output Fig. 7-38 Changing Duty Factor of PWM Output CIF00 ← 0 Preprocessing for changing duty factor Clear INTC00 interrupt request flag.
137 Chapter 7 Timer/Counter Units 7 (5) PPG output operation In PPG output operation, a pulse signal with a period and duty factor determined by the values set in the compare registers is output. (See Fig. 7-39 .) Fig. 7-40 shows the setting of control registers.
138 µ PD78214 Sub-Series Fig. 7-41 Setting Procedure for PPG Output PPG output Set CRC0 register Set TOC register Set P34 pin in control mode Set period in compare register CR01 ; Sets bit 3 of TMC0 CRC0 ← D8H PMC3.4 ← 1 Set duty factor in compare register CR00 Start counting CE0 ← 1 Fig.
139 Chapter 7 Timer/Counter Units 7 7.2 8-BIT TIMER/COUNTER 1 7.2.1 Functions Eight-bit timer/counter 1 can function as an interval timer and can also be used for pulse width measurement. In addition to these basic functions, 8-bit timer/counter 1 can be used as a timer for generating an output trigger on a real-time output port.
140 µ PD78214 Sub-Series 7.2.2 Configuration Eight-bit timer/counter 1 consists of one 8-bit timer 1 (TM1), one 8-bit compare register (CR10), and one 8-bit capture/compare register (CR11).
141 Chapter 7 Timer/Counter Units 7 Fig. 7-43 Block Diagram of 8-Bit Timer/Counter 1 Internal bus 8 8 PRS12 ES01 Timer control register 0 (TMC1) Clear PRS11 PRS10 RESET 8 8 8 8 8 8 8 CE1 OVF1 8 Intern.
142 µ PD78214 Sub-Series (1) 8-bit timer 1 (TM1) TM1 is a timer for counting up with the count clock specified by the lower 4 bits of prescaler mode register 1 (PRM1). The count operation of TM1 can be enabled or disabled by timer control register 1 (TMC1).
143 Chapter 7 Timer/Counter Units 7 7.2.3 8-Bit Timer/Counter 1 Control Registers (1) Timer control register 1 (TMC1) The TMC1 register is an 8-bit register for controlling the count operations of 8-bit timer 1 (TM1) and 8-bit timer 2 (TM2). The lower 4 bits control the count operation of TM1 of 8-bit timer/counter 1.
144 µ PD78214 Sub-Series Fig. 7-45 Format of Prescaler Mode Register 1 (PRM1) 7 6 54 3 2 10 PRM1 PRS23 0 PRS12 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 PRS10 PRS11 Specification of count clock [Hz] f CLK /16 f CLK /32 f CLK /64 f CLK /128 f CLK /256 f CLK /512 85.
145 Chapter 7 Timer/Counter Units 7 7.2.4 Operation of 8-Bit Timer 1 (TM1) (1) Basic operation Eight-bit timer/counter 1 performs count operation by counting up with the count clock specified by the lower 4 bits of prescaler mode register 1 (PRM1). When the RESET signal is applied, TM1 is cleared to 00H, and count operation stops.
146 µ PD78214 Sub-Series (c) When the value of TM1 is FFH Count clock TM1 Cleared by software OVF1 OVF1 ← 0 FEH FFH 0H 1H (2) Clear operation After a coincidence with a compare register (CR1m: m = 0, 1) or capture operation, 8-bit timer 1 (TM1) can be automatically cleared.
147 Chapter 7 Timer/Counter Units 7 Fig. 7-49 TM1 Cleared after Capture Operation TM1 Count clock n-1 n 0 1 2 INTP0 TM1 is captured to CR11 here Cleared here TM1 can also be cleared by software when the CE1 bit of the timer control register (TMC1) is reset to 0.
148 µ PD78214 Sub-Series (b) Restart after 0 is set in TM1 cleared Count clock TM1 CE1 n-1 n 0 0 1 When the CE1 bit is set to 1 aftr this count clock, counting starts from 0 on the count clock input after the CE1 bit has been set.
149 Chapter 7 Timer/Counter Units 7 Fig. 7-51 Compare Operation Remark CLR10 = 0, CLR11 = 0, CM = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.
150 µ PD78214 Sub-Series Fig. 7-53 Capture Operation Remark D n : TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1 Count starts TM1 count value D0 D1 D2 D2 D1 FFH 0H INTP0 pin input IN.
151 Chapter 7 Timer/Counter Units 7 Fig. 7-54 TM1 Cleared after Capture Operations Remark D n : TM1 count value (n = 0, 1, 2, ...) CLR10 = 0, CLR11 = 0, CM = 1 7.
152 µ PD78214 Sub-Series Fig. 7-55 Timing of Interval Timer Operation (1) n n 0H TM1 count value MOD(2n) MOD(3n) FFH MOD(2n) MOD(3n) MOD(4n) Timer starts Compare register (CR10) INTC10 interrupt requ.
153 Chapter 7 Timer/Counter Units 7 Fig. 7-57 Setting Procedure for Interval Timer Operation (1) Fig. 7-58 Interrupt Request Handling for Interval Timer Operation (1) (2) Interval timer operation (2) Eight-bit timer/counter 1 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand.
154 µ PD78214 Sub-Series Fig. 7-59 Timing of Interval Timer Operation (2) (When CR11 Is Used As a Compare Register) Remark Interval = (n + 1) × x/f CLK , 0 ≤ n ≤ FFH x = 16, 32, 64, 128, 256, 512 Fig.
155 Chapter 7 Timer/Counter Units 7 Fig. 7-61 Setting Procedure for Interval Timer Operation (2) (3) Pulse width measurement operation In pulse width measurement, the width of the high level or low level of an external pulse signal applied to the external interrupt request (INTP0) input pin is measured.
156 µ PD78214 Sub-Series Fig. 7-62 Timing of Pulse Width Measurement (When CR11 Is Used As a Capture Register) Remark D n : TM1 count value (n = 0, 1, 2, .
157 Chapter 7 Timer/Counter Units 7 Fig. 7-63 Setting of Control Registers for Pulse Width Measurement (a) Timer control register 1 (TMC1) (b) Prescaler mode register 1 (PRM1) (c) Capture/compare cont.
158 µ PD78214 Sub-Series Fig. 7-64 Setting Procedure for Pulse Width Measurement Fig. 7-65 Interrupt Request Handling for Pulse Width Calculation Set CRC1 register Set INTM0 register and MK0L registe.
159 Chapter 7 Timer/Counter Units 7 7.3 8-BIT TIMER/COUNTER 2 7.3.1 Functions Eight-bit timer/counter 2 has two functions not available with the other three timers/counters: • External event counter.
160 µ PD78214 Sub-Series (2) Programmable square wave output Eight-bit timer/counter 2 outputs a square wave separately on the TO2 and TO3 timer output pins. Table 7-12 Programmable Square Wave Output Setting Range of 8-Bit Timer/Counter 2 Maximum pulse width 2 8 × 16/f CLK (683 µ s) 2 8 × 32/f CLK (1.
161 Chapter 7 Timer/Counter Units 7 (4) External event counter Eight-bit timer/counter 2 counts clock pulses (CI pin input pulses) applied to the external interrupt input pin (INTP2). Table 7-14 indicates the clock signals that can be applied to 8-bit timer/counter 2.
162 µ PD78214 Sub-Series Fig. 7-66 Block Diagram of 8-Bit Timer/Counter 2 External interrupt mode register INTC21 RESET 8 8 8 8 8 8 8 1/8 ES21 ES20 ES11 ES10 (INTM0) INTP1 INTP1 INTP2/CI INTP2 MPX Ed.
163 Chapter 7 Timer/Counter Units 7 (5) Output control circuit When the value of CR20 or CR21 coincides with the value of TM2, timer output can be inverted. By setting the higher 4 bits of the timer output control register (TOC), a square wave can be output on a timer output pin (TO2, TO3).
164 µ PD78214 Sub-Series (2) Prescaler mode register 1 (PRM1) The PRM1 register is an 8-bit register used to specify a count clock for 8-bit timer 1 (TM1) and 8-bit timer 2 (TM2). The higher 4 bits are used to specify a count clock for TM2 of 8-bit timer/counter 2.
165 Chapter 7 Timer/Counter Units 7 (3) Capture/compare control register 2 (CRC2) The CRC2 register is used to specify the condition for enabling the clear operation of 8-bit timer 2 (TM2) with the CR21 compare register or CR22 capture register, and also specify a timer output (TO2, TO3) mode.
166 µ PD78214 Sub-Series (4) Timer output control register (TOC) The TOC register is an 8-bit register for controlling the active level of timer output and for enabling/disabling timer output. The higher 4 bits control the timer output operation (on the TO2 and TO3 pins) of 8-bit timer/counter 2.
167 Chapter 7 Timer/Counter Units 7 7.3.4 Operation of 8-Bit Timer 2 (TM2) (1) Basic operation Eight-bit timer/counter 2 performs count operation by counting up with the count clock specified by the higher 4 bits of prescaler mode register 1 (PRM1). Bit 7 (CE2) of timer control register 1 (TMC1) is used to enable/disable count operation.
168 µ PD78214 Sub-Series (c) When the value of TM2 is FFH (2) Clear operation After a coincidence with the CR21 compare register or capture operation, 8-bit timer 2 (TM2) can be automatically cleared. If a TM2 clear cause occurs, TM2 is cleared to 00H by the next count clock pulse.
169 Chapter 7 Timer/Counter Units 7 TM2 can also be cleared by software when the CE2 bit of the timer control register (TMC1) is reset to 0. Similarly, clear operation is performed by the count clock pulse following the resetting of CE2 bit to 0.
170 µ PD78214 Sub-Series (c) Restart before 0 is set in TM2 cleared Count clock TM2 CE2 n-1 When the CE2 bit is set to 1 before this count clock, Clearing TM2 by CE2 ← 0 and counting by CE2 ← 1 are performed simultaneously.
171 Chapter 7 Timer/Counter Units 7 Fig. 7-75 External Event Count Timing of 8-Bit Timer/Counter 2 (1) When occurrences of one edge are counted (maximum frequency = f CLK /24) Remark ICI: CI input sig.
172 µ PD78214 Sub-Series The count operation of TM2 is controlled by the CE2 bit of the TMC1 register as in the case of basic operation. When the CE2 bit is set to 1 by software, TM2 is cleared to 00H by the first count clock pulse, then count-up operation starts.
173 Chapter 7 Timer/Counter Units 7 Fig. 7-77 Example Where Input of No Valid Edge Cannot Be Distinguished from Input of Only One Valid Edge with External Event Counter Cannot be distinguished TM2 1 0 2 CI 0 Count starts Fig.
174 µ PD78214 Sub-Series (b) Count value read processing 3. With an in-circuit emulator, digital noise on the CI/INTP2 pin cannot be removed correctly. When the event counter function is used, the operation described below is performed if an edge is detected erroneously.
175 Chapter 7 Timer/Counter Units 7 7.3.6 One-Shot Timer Function Eight-bit timer/counter 2 has an operation mode in which the full-count (FFH) is reached as the result of count operation.
176 µ PD78214 Sub-Series 7.3.7 Compare Register and Capture Register Operations (1) Compare operation Eight-bit timer/counter 2 performs an operation to compare the values set in the compare registers with timer count values.
177 Chapter 7 Timer/Counter Units 7 Fig. 7-81 TM2 Cleared After a Coincidence Is Detected Remark CLR22 = 0 Caution When using an in-circuit emulator, see the notes described in Section 7.
178 µ PD78214 Sub-Series Fig. 7-82 Capture Operation Remark D n : TM2 count value (n = 0, 1, 2, ...) CLR21 = 0, CLR22 = 0 D0 D1 D2 D0 D1 D2 (undefined) (undefined) Reads CR22 Reads CR22 FFH TM2 count.
179 Chapter 7 Timer/Counter Units 7 Fig. 7-83 TM2 Cleared after Capture Operation Remark CLR21 = 0, CLR22 = 1 7.3.8 Basic Operation of Output Control Circuit The output control circuit controls the levels of the timer outputs (TO2, TO3) according to the coincidence signal from the compare registers.
180 µ PD78214 Sub-Series Table 7-15 Timer Output (TO2, TO3) Operation TOC 0 0 1 1 0 1 1 0 1 1 0 1 1 ENTO3 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 0/1 AL V3 0 1 0 1 1 0 1 1 0 1 1 0 1 ENTO2 0/1.
181 Chapter 7 Timer/Counter Units 7 (1) Basic operation By setting ENTOn (n = 2, 3) of the timer output control register (TOC) to 1, the timer outputs (TO2, TO3) can be changed with the timing determined by MOD0, MOD1, and CLR21 of capture/compare control register 2 (CRC2).
182 µ PD78214 Sub-Series Table 7-16 TO2 and TO3 Toggle Output (f CLK = 6 MHz) Count clock f CLK /16 f CLK /32 f CLK /64 f CLK /128 f CLK /256 f CLK /512 Maximum pulse width 2 8 × 16/f CLK (683 µ s) 2 8 × 32/f CLK (1.37 ms) 2 8 × 64/f CLK (2.73 ms) 2 8 × 128/f CLK (5.
183 Chapter 7 Timer/Counter Units 7 Table 7-17 PWM Output on TO2 and TO3 (f CLK = 6 MHz) Count clock f CLK /16 f CLK /32 f CLK /64 f CLK /128 f CLK /256 f CLK /512 Minimum pulse width 2.7 5.3 10.7 21.3 42.7 85.3 PWM period (ms) 0.7 1.4 2.7 5.5 10.9 21.
184 µ PD78214 Sub-Series Fig. 7-87 PWM Output When CR20 = FFH Remark ALV2 = 0 Even if the value of a compare register (CR20, CR21) coincides with the value of 8-bit timer 2 (TM2) more than once during one period of PWM output, the output levels on the timer outputs (TO2, TO3) are not inverted.
185 Chapter 7 Timer/Counter Units 7 Cautions 1. If a value less than the value of 8-bit timer 2 (TM2) is set in a compare register (CR20, CR21), a PWM signal with a 100% duty factor is output. Rewrite the CR20 or CR21 compare register, if required, by using an interrupt generated by a coincidence between TM2 and the compare register.
186 µ PD78214 Sub-Series Fig. 7-90 shows an example of PPG output using 8-bit timer 2 (TM2). Fig. 7-91 shows an example of PPG output when CR20 = CR21.
187 Chapter 7 Timer/Counter Units 7 Fig. 7-91 PPG Output When CR20 = CR21 Remark ALV2 = 0 Fig. 7-92 PPG Output When CR20 = 00H Remark ALV2 = 0 1 2 nn n INTC20 INTC21 TO2 TM2 count value n-1 0 n-1 2 1 .
188 µ PD78214 Sub-Series Even if the value of the CR20 compare register coincides with the value of 8-bit timer 2 (TM2) more than once during one period of PPG output, the output level on the timer output (TO2) is not inverted.
189 Chapter 7 Timer/Counter Units 7 2. If the current value of the CR21 compare register is decreased below the value of 8-bit timer 2 (TM2), the PPG period becomes as long as the full-count time of TM2.
190 µ PD78214 Sub-Series 7.3.11 Sample Applications (1) Interval timer operation (1) By free running 8-bit timer 2 (TM2), and adding a value to a compare register (CR20, CR21) in an interrupt handling routine, 8-bit timer/counter 2 can be used as an interval timer whose period is as long as the added value.
191 Chapter 7 Timer/Counter Units 7 Fig. 7-97 Setting of Control Registers for Interval Timer Operation (1) (a) Prescaler mode register 1 (PRM1) (b) Capture /compare control register 0 (CRC0) 76 54 321 0 00 0 0 0 1 CRC0 0 0 Disables clearing TM2 Both TO2 and TO3 are used for toggle output (c) Timer control register 1 (TMC1) Fig.
192 µ PD78214 Sub-Series Fig. 7-99 Interrupt Request Handling for Interval Timer Operation (1) (2) Interval timer operation (2) Eight-bit timer/counter 2 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand.
193 Chapter 7 Timer/Counter Units 7 Fig. 7-101 Setting of Control Registers for Interval Timer Operation (2) (a) Prescaler mode register 1 (PRM1) (b) Capture/compare control register 2 (CRC2) (c) Time.
194 µ PD78214 Sub-Series Fig. 7-102 Setting Procedure for Interval Timer Operation (2) (3) Pulse width measurement operation In pulse width measurement, the width of the high level or low level of an external pulse signal applied to the INTP1 pin is measured.
195 Chapter 7 Timer/Counter Units 7 Fig. 7-103 Timing of Pulse Width Measurement Remark D n : TM2 count value (n = 0, 1, 2, ...) Fig. 7-104 Setting of Control Registers for Pulse Width Measurement (a).
196 µ PD78214 Sub-Series (c) Timer control register 1 (TMC1) (d) External interrupt mode register 0 (INTM0) Fig. 7-105 Setting Procedure for Pulse Width Measurement Set CRC1 register Set INTM0 regist.
197 Chapter 7 Timer/Counter Units 7 Fig. 7-106 Interrupt Request Handling for Pulse Width Calculation (4) PWM output operation In PWM output operation, a pulse signal with a duty factor determined by the value set in a compare register is output. (See Fig.
198 µ PD78214 Sub-Series Fig. 7-108 Setting of Control Registers for PWM Output Operation (a) Timer control register 1 (TMC1) (b) Prescaler mode register 1 (PRM1) (c) Capture/compare control register.
199 Chapter 7 Timer/Counter Units 7 Fig. 7-109 Setting Procedure for PWM Output Fig. 7-110 Changing Duty Factor of PWM Output (5) PPG output operation In PPG output operation, a pulse signal with a period and duty factor determined by the values set in the compare registers is output.
200 µ PD78214 Sub-Series Fig. 7-112 Setting of Control Registers for PPG Output Operation (a) Timer control register 1 (TMC1) (b) Prescaler mode register 1 (PRM1) (c) Capture/compare control register.
201 Chapter 7 Timer/Counter Units 7 Fig. 7-113 Setting Procedure for PPG Output Fig. 7-114 Changing Duty Factor of PPG Output (6) External event counter operation When functioning as an external event counter, 8-bit timer/counter 2 counts clock pulses externally applied to the CI pin.
202 µ PD78214 Sub-Series Fig. 7-116 Setting of Control Registers for External Event Counter Operation (a) Prescaler mode register 1 (PRM1) (b) External interrupt mode register 0 (INTM0) (c) Timer control register 1 (TMC1) Fig.
203 Chapter 7 Timer/Counter Units 7 (7) One-shot timer operation When functioning as a one-shot timer, 8-bit timer/counter 2 generates only one interrupt when a specified count time has elapsed after the start of 8-bit timer 2 (TM2). (See Fig. 7-118 .
204 µ PD78214 Sub-Series Fig. 7-120 Setting Procedure for One-Shot Timer Operation Fig. 7-121 Procedure for Starting an Additional One-Shot Timer Operation One-shot timer Set one-shot timer mode ; Se.
205 Chapter 7 Timer/Counter Units 7 7.4 8-BIT TIMER/COUNTER 3 7.4.1 Functions Eight-bit timer/counter 3 can be used as an interval timer, and also as a counter for generating a clock signal used with the baud rate generator. When operating as an interval timer, 8-bit timer/counter 3 generates an internal interrupt at specified intervals.
206 µ PD78214 Sub-Series Fig. 7-122 Block Diagram of 8-Bit Timer/Counter 3 INTP4/ASCK ES41,ES40 8 8 1/8 ES41 ES40 INTP4 INTC30 f CLK /512 f CLK /256 f CLK /128 f CLK /64 f CLK /32 f CLK /16 f CLK /8 .
207 Chapter 7 Timer/Counter Units 7 7.4.3 8-Bit Timer/Counter 3 Control Registers (1) Timer control register 0 (TMC0) The TMC0 register is an 8-bit register for controlling the count operation of 8-bit timer 3 (TM3). The higher 4 bits control the count operation of TM3 of 8-bit timer/counter 3.
208 µ PD78214 Sub-Series 7.4.4 Operation of 8-Bit Timer 3 (TM3) (1) Basic operation Eight-bit timer/counter 3 performs count operation by counting up with the count clock specified by the higher 4 bits of prescaler mode register 0 (PRM0). When the RESET signal is applied, TM3 is cleared to 00H, and count operation stops.
209 Chapter 7 Timer/Counter Units 7 (2) Clear operation After a coincidence with the CR30 compare register, 8-bit timer 3 (TM3) can be automatically cleared.
210 µ PD78214 Sub-Series (b) Restart after 0 is set in TM3 cleared Count clock TM3 CE3 n-1 n 0 0 1 When the CE3 bit is set to 1 after this count clock, counting starts from 0 on the count clock input after the CE3 bit has been set.
211 Chapter 7 Timer/Counter Units 7 Fig. 7-128 Compare Operation 7.4.6 Sample Applications (1) Interval timer operation Eight-bit timer/counter 3 can be used as an interval timer that generates an interrupt at intervals of a count time specified beforehand.
212 µ PD78214 Sub-Series Fig. 7-130 Setting of Control Registers for Interval Timer Operation (a) Timer control register 0 (TMC0) (b) Prescaler mode register 0 (PRM0) 765 4 3 21 0 PRS3 0 00 0 PRM0 PRS2 PRS1 PRS0 Specifies count clock (x/f CLK ; where x = 16, 32, 64, 128, 256, or 512) Fig.
213 Chapter 7 Timer/Counter Units 7 (2) The OVFm flag for holding an overflow from a timer/counter is contained in register TMCn used to control the operation of the timer/counter. When a read/modify/write instruction (such as AND TMCn,#7FH) is executed, for example, the OVFm flag may be cleared.
214 µ PD78214 Sub-Series Fig. 7-132 Count Start Operation (5) Even when an instruction is executed to stop a timer (CEn ← 0), the value of TMn is not cleared to 0 immediately. Instead, the value of TMn is cleared to 0 by the count clock pulse occurring after an instruction is executed (CEn ← 0) to stop the timer.
215 Chapter 7 Timer/Counter Units 7 (6) When a register associated with a timer/counter is accessed, wait states as many as the maximum number of clock pulses Note indicated below are automatically inserted.
216 µ PD78214 Sub-Series (9) When PWM is used, a PWM signal with a 100% duty factor is output if a value less than the value of TMn (n = 0, 2) is set in compare register CRnm (n = 0, 2, m = 0, 1). CRnm rewrite operation must be performed using an interrupt generated by a coincidence between TMn and CRnm to be rewritten.
217 Chapter 7 Timer/Counter Units 7 (10)Notes on compare register rewrite operation when PPG output is used (a) If a value less than the value of TMn is written into compare register CRn0 (n = 0, 2) before the value of the CRn0 register coincides with the value of TMn (n = 0, 2), a PPG signal with a 100% duty factor is output in that period.
218 µ PD78214 Sub-Series Fig. 7-137 Example of PPG Output Period Made Longer n3 n1 n2 n4 n2 0H CRn0 CRn1 TOp (p = 0,2) n1 n3 n1 n4 n2 n1 Full count value n3 n5 TMn The PPG period is extended when a value, n2 less than TMn value, n5 is written to CRn1 here.
219 Chapter 7 Timer/Counter Units 7 (14) With an in-circuit emulator, digital noise cannot be removed correctly. When a timer/counter is used together with edge detection function, note the point below. (a) When IE-78210-R is used Operations are performed on an erroneously detected edge.
220 µ PD78214 Sub-Series Fig. 7-138 Interrupt Request Generation Using External Event Counter Countable timing of TM2 TM2 n n-1 n+1 ICI CI 8 to 12 clocks 16 clocks (Max.) Count clock of TM2 Coincidence between INTP2 and ICI TM2 counts up here or is compared with compare register.
221 Chapter 7 Timer/Counter Units 7 Fig. 7-140 How to Distinguish Input of No Valid Edge from Input of Only One Valid Edge with External Event Counter (a) Count start processing (b) Count value read processing Count starts Clear INTP2 interrupt request flag ; Clears PIF2 (0) Start counting ; Sets CE2 (1) End TMC1.
222 µ PD78214 Sub-Series (3) With an in-circuit emulator, digital noise cannot be removed correctly. When the timer/counter is used together with edge detection function, note the point below. • When IE-78210-R is used All functions are performed on an erroneously detected edge.
223 Chapter 7 Timer/Counter Units 7 Fig. 7-141 Interrupt Generation Timing Change by an Erroneously Detected Edge TMn count value (n = 1,2) For PD78214 Emulator other than IE-78210-R For PD78214 Emula.
224 µ PD78214 Sub-Series (c) Event counter function (with only 8-bit timer/counter 2) An erroneously detected edge causes no change in the value of the timer/counter.
225 8 CHAPTER 8 A/D CONVERTER The µ PD78214 contains an analog-to-digital (A/D) converter with eight multiplexed analog input pins (AN0 through AN7). This A/D converter uses successive approximation The conversion result is stored in an 8-bit A/D conversion result register (ADCR).
226 µ PD78214 Sub-Series Fig. 8-1 A/D Converter Configuration Successive approximation register (SAR) Sample and hold circuit Series resistor string Input selector Tap selector R/2 R/2 A/D converter .
227 Chapter 8 A/D Converter 8 Cautions 1. To prevent malfunction due to noise, insert a capacitor between each analog input pins (AN0 through AN7) and the AV SS pin and between the reference voltage input pin (AV REF ) and the AV SS pin. Fig. 8-2 Example of Capacitors Connected to the A/D Converter Pins 2.
228 µ PD78214 Sub-Series (7) Edge detector The edge detector detects the valid edge of an input at the interrupt request input pin (INTP5) and generates an external interrupt request signal (INTP5) and an external trigger for A/D conversion.
229 Chapter 8 A/D Converter 8 Fig. 8-3 A/D Converter Mode Register (ADM) Format Note F CLK : System clock frequency 7 6 54 3 210 TRG 0 FR CS ADM ANI2 ANI1 ANI0 MS FR ANI2 ANI1 ANI0 MS 0 0 0 0 1 1 1 1 .
230 µ PD78214 Sub-Series 8.3 OPERATION 8.3.1 Basic A/D Converter Operation (1) A/D conversion sequence The A/D converter operates as follows: (a) The input selector selects one of the analog input pins (AN0 through AN7) according to the mode of operation specified in the A/D converter mode register (ADM).
231 Chapter 8 A/D Converter 8 A/D conversion continues until the CS bit is reset by software. If data is written to the ADM register during conversion, conversion is initialized. If the CS bit is 1, conversion is started from the beginning. When the RESET signal is input, the ADCR register contents become undefined.
232 µ PD78214 Sub-Series (3) A/D conversion time The time required for A/D conversion is determined by the system clock frequency (f CLK ) and the FR bit of the ADM register. To maintain A/D conversion accuracy above a certain level, it is necessary to set the FR bit as listed in Table 8-2 according to the system clock frequency.
233 Chapter 8 A/D Converter 8 8.3.3 Scan Mode In the scan mode, signals input from the analog input pins, specified by bits 1 through 3 (ANI0 through ANI2) of the A/D converter mode register (ADM), are selected successively for conversion.
234 µ PD78214 Sub-Series 2. If the ADM register is set after registers related to interrupts have been set during the scan mode, an unwanted interrupt may occur, thus causing the storage location of the conversion result to appear to have shifted. To prevent this, take the actions listed below in the stated order.
235 Chapter 8 A/D Converter 8 (2) Scan-mode A/D conversion When triggered, conversion begins with the signal input to the AN0 pin. When the conversion sequence for the AN0 pin is completed, the signal at the next analog input pin is converted. Each time a conversion sequence is completed, an interrupt request (INTAD) is generated.
236 µ PD78214 Sub-Series Fig. 8-10 Example of Malfunction in a Hardware-Started A/D Conversion Notes 1. When the operation is normal, the result of conversion 2 is stored. If a malfunction occurs, however, value 7FH is stored. 2. Time from when an input to the INT5 pin changes to when its edge is asserted.
237 Chapter 8 A/D Converter 8 Fig. 8-11 Select-Mode A/D Conversion Started by Hardware ANn ANn ANn ANn ANn ANm ANm ANm ANn ANn ANn INTP5 pin input (rising edge valid) A/D conversion Standby state ADM writing CS ← 1, TRG ← 1 ADM writing CS ← 1, TRG ← 1 ADCR INTAD INTAD accepted Standby state Remark n = 0, 1, .
238 µ PD78214 Sub-Series Fig. 8-12 Scan-Mode A/D Conversion Started by Hardware AN0 AN2 AN1 AN0 AN0 AN1 AN2 AN1 AN0 AN1 AN0 AN0 AN0 AN2 AN1 AN0 ADCR AN0 ADM writing CS ← 1, TRG ← 1 A/D conversion.
239 Chapter 8 A/D Converter 8 8.4 INTERRUPT REQUEST FROM THE A/D CONVERTER The A/D converter generates an A/D conversion end interrupt request (INTAD), each time a conversion sequence is completed, except for the select mode. The interrupt control flags are shared by the INTAD interrupt and the INTP5 external interrupt.
240 µ PD78214 Sub-Series (2) About hardware-started A/D conversion (a) Eight to twelve system clocks are required from when a valid edge appears at the INTP5 pin until A/D conversion is actually started. Take this delay into consideration when designing your application.
241 Chapter 8 A/D Converter 8 Fig. 8-14 Example of Malfunction in a Hardware-Started A/D Conversion Notes 1. When the operation is normal, the result of conversion 2 is stored. If a malfunction occurs, however, value 7FH is stored. 2. Time from when an input to the INT5 pin changes to when its edge is asserted.
242.
243 9 CHAPTER 9 ASYNCHRONOUS SERIAL INTERFACE The µ PD78214 contains an asynchronous serial interface, UART (Universal Asynchronous Receiver Transmitter). This interface transmits 1-byte data following a start bit and is capable of full-duplex transmission.
244 µ PD78214 Sub-Series Fig. 9-1 Asynchronous Serial Interface Configuration INTST Internal bus Reception buffer RESET TXS 1/8 1/8 RXB PE FE OVE INTSR INTSER (ASIS) Transmission control parity gener.
245 Chapter 9 Asynchronous Serial Interface 9 (1) Reception buffer (RXB) The reception buffer holds the receive data. Each time the shift register receives 1 byte of data, it sends it to this reception buffer. If the data length is specified to be 7 bits, the receive data is sent to bits 0 through 6 of the RXB.
246 µ PD78214 Sub-Series Fig. 9-2 Format of the Asynchronous Serial Interface Mode Register (ASIM) Cautions 1. The asynchronous serial interface mode register (ASIM) must not be modified during transmission.
247 Chapter 9 Asynchronous Serial Interface 9 Fig. 9-3 Format of the Asynchronous Serial Interface Status Register (ASIS) Caution Be sure to read the reception buffer (RXB) contents, even if a reception error occurs. Otherwise, an overrun error will occur when the next data is received, and the error status will persist.
248 µ PD78214 Sub-Series • Odd parity In contrast to even parity, the parity bit for odd parity is controlled so that the number of 1 bits in the transmit data becomes odd. When data is received, the number of 1 bits in it is counted, and if the number of 1 bits is even, a parity error is detected.
249 Chapter 9 Asynchronous Serial Interface 9 9.3.4 Reception When the RXE bit of the asynchronous serial interface mode register (ASIM) is set to 1, reception is enabled, and the input to the RxD pin is sampled. Sampling at the RxD pin is performed using the serial clock specified in the ASIM register.
250 µ PD78214 Sub-Series Table 9-1 Causes of Reception Errors Parity error Framing error Overrun error The parity of the receive data does not match the type of parity specified at transmission. No stop bit is detected Note . Before the receive data is read out from the reception buffer, the next data is received.
251 Chapter 9 Asynchronous Serial Interface 9 9.4 BAUD RATE GENERATOR 9.4.1 Configuration of the Baud Rate Generator for UART Fig. 9-8 shows the configuration of the baud rate generator. Fig. 9-8 Baud Rate Generator Clock Configuration (1) 4-bit counter The 4-bit counter counts the internal system clock (f CLK ).
252 µ PD78214 Sub-Series Fig. 9-9 Baud Rate Generator Control Register (BRGC) Format 7 6543 2 1 0 BRGC CE TPS2 TPS1 TPS0 MDL3 MDL2 MDL1 MDL0 MDL3 MDL2 MDL1 MDL0 k Input clock of baud rate generator 0.
253 Chapter 9 Asynchronous Serial Interface 9 9.4.3 Operation of the Baud Rate Generator for UART The baud rate generator for UART starts operating, when the CE bit of the baud rate generator control register (BRGC) is set to 1.
254 µ PD78214 Sub-Series 9.5 BAUD RATE SETTING The baud rate can be set by three methods listed in Table 9-2. The table indicates the ranges of baud rates that can be generated by each method, the baud rate calculation formulas, and the selection methods.
255 Chapter 9 Asynchronous Serial Interface 9 Table 9-3 Example of Setting the BRGC Register When the Baud Rate Generator for UART Is Used — FCH F9H E9H D9H C9H B9H A9H 99H 89H 92H 84H — 2.
256 µ PD78214 Sub-Series 9.5.2 Example of Setting the Baud Rate When 8-bit Timer/Counter 3 Is Used Table 9-4 lists examples of setting the baud rate when 8-bit timer/counter 3 is used. When using 8-bit timer/ counter 3, reset the SCK bit of the asynchronous serial interface mode register (ASIM) to 0.
257 Chapter 9 Asynchronous Serial Interface 9 Table 9-4 Example of Setting the Baud Rate When 8-Bit Timer/Counter 3 Is Used (Asynchronous Serial Interface) f CLK /16 f CLK /8 f CLK /8 f CLK /8 f CLK /8 f CLK /8 f CLK /8 f CLK /8 — — 0.16 0.03 0.16 0.
258 µ PD78214 Sub-Series 9.5.3 Example of Setting the BRGC When the External Baud Rate Input (ASCK) Is Used Table 9-5 lists examples of setting the BRGC register when an external baud rate input (ASCK) is used. To use the ASCK input, set the SCK bit of the asynchronous serial interface mode register (ASIM) to 1.
259 10 CHAPTER 10 CLOCK SYNCHRONOUS SERIAL INTERFACE 10.1 FUNCTION The clock synchronous serial interface of the µ PD78214 is configured as shown in Fig.
260 µ PD78214 Sub-Series Fig. 10-1 Block Diagram of the Clock Synchronous Serial Interface Internal bus D CLS1 CLS0 f CLK /32 f CLK /8 8-bit timer/counter 3 output 1/2 Serial clock selector INTCSI In.
261 Chapter 10 Clock Synchronous Serial Interface 10 (1) Shift register (SIO) Converts 8-bit serial data into 8-bit parallel data and vice versa. The SIO is used for both transmission and reception. Data is shifted in (received) or shifted out (transmitted) from the MSB.
262 µ PD78214 Sub-Series 10.3 CONTROL REGISTERS 10.3.1 Clock Synchronous Serial Interface Mode Register (CSIM) This 8-bit register specifies a serial interface operation mode, serial clock and wake-up function. The 8-bit manipulation instruction and bit manipulation instruction can read and write the contents of the CSIM register.
263 Chapter 10 Clock Synchronous Serial Interface 10 10.3.2 Serial Bus Interface Control Register (SBIC) The SBIC register consists of bits that control the status of the serial bus, as well as bits that indicate the status of the data input from the serial bus.
264 µ PD78214 Sub-Series Fig. 10-3 Format of Serial Bus Interface Control Register (SBIC) ★ SBIC BSYE ACKD ACKE ACKT CMDD RELD CMDT RELT 76543210 RELT Trigger output control for bus release signal .
265 Chapter 10 Clock Synchronous Serial Interface 10 10.4 OPERATIONS IN THE THREE-WIRE SERIAL I/O MODE In three-wire serial I/O mode, the device can communicate with a device having a conventional clock synchronous serial interface.
266 µ PD78214 Sub-Series Fig. 10-5 Timing in Three-Wire Serial I/O Mode Notes Master CPU : Output Slave CPU : Input In three-wire serial I/O mode, the SO pin sends a CMOS push-pull output. Remark When connecting the device to a device having two-wire serial I/O, connect a buffer to the SO pin as shown in Fig.
267 Chapter 10 Clock Synchronous Serial Interface 10 10.4.2 Operation When Only Transmission Is Permitted Transmission is enabled when the CTXE bit of the clock synchronous serial interface mode register (CSIM) is set (1). If the CTXE bit is set, writing the contents of the shift register (SIO) invokes the start of transmission.
268 µ PD78214 Sub-Series (1) Selecting the internal clock as the serial clock When transmission and reception are started, the serial clock is output from the SCK pin. In synchronization with the falling edge of the serial clock, data is sequentially output from the SIO to the SO pin.
269 Chapter 10 Clock Synchronous Serial Interface 10 (2) Function to select a chip by its address The master sends an address to select a slave chip. (3) Wake-up function Using the wake-up function (which can be set or released by software), a slave device can easily detect whether it receives the address (chip select).
270 µ PD78214 Sub-Series 10.5.2 Configuration of the Serial Interface Fig. 10-9 is a block diagram of the µ PD78214. The serial clock pin (SCK) and serial data bus pin SB0 are configured as shown in Fig.
271 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-9 Block Diagram of Clock Synchronous Serial Interface Internal bus D CLS1 CLS0 f CLK /32 f CLK /8 INTCSI Interrupt signal generator circuit.
272 µ PD78214 Sub-Series 10.5.3 Detecting an Address Match SBI communication is started when a slave device is selected according to the address sent by the master device. The software detects whether the address of a slave device matches the sent address.
273 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-10 Format of Clock Synchronous Serial Interface Mode Register (CSIM) Caution Do not change CTXE from 0 to 1 or CRXE from 1 to 0, or vice versa, by means of a single instruction.
274 µ PD78214 Sub-Series (2) Serial bus interface control register (SBIC) This 8-bit register consists of bits controlling the serial bus statuses and flags indicating the statuses of data input from the serial bus. The 8-bit manipulation instruction and bit manipulation instruction can read and write the contents of the register.
275 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-11 Format of SBIC Register (2/2) Remarks (R) : Read-only (W) : Write-only (R/W): Read/write ★ Acknowledge trigger bit (W) Acknowledge enable bit (R/W) Acknowledge detection flag (R) Busy enable bit (R/W) 1 ACKT Do not set this bit to 1 before serial transfer is completed.
276 µ PD78214 Sub-Series (3) Shift register (SIO) This 8-bit shift register is used for parallel-serial conversion. The data written into the SIO is output to the serial data bus. The data on the serial data bus is read into the SIO. Fig. 10-12 shows the configuration of the shift register and related components.
277 Chapter 10 Clock Synchronous Serial Interface 10 10.6 SBI COMMUNICATION AND SIGNALS This section describes the format of the SBI serial data and signals to be used. Serial data transferred via SBI can be divided into three groups: address, command, and data.
278 µ PD78214 Sub-Series 10.6.2 Command Signal (CMD) The command signal is the SB0 line going from high to low while the SCK line is high (the serial clock is not output). The master device outputs this signal. Fig. 10-15 Command Signal SCK SB0 "H" The slave device contains the hardware to detect the command signal.
279 Chapter 10 Clock Synchronous Serial Interface 10 10.6.4 Command and Data The master device sends commands to, and sends or receives data to or from, the slave device selected according to the specified address. Fig. 10-18 Command SCK SB0 1 2345 678 Command C7 C6 C5 C4 C3 C2 C1 C0 Command signal Fig.
280 µ PD78214 Sub-Series 10.6.6 Busy Signal (BUSY) and Ready Signal (READY) The busy signal informs the master device that the slave device is preparing for data transmission or reception. The ready signal informs the master device that the slave device is ready for data transmission or reception.
281 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-23 ACKT Operation Caution Do not set ACKT before transfer has been completed. Fig. 10-24 ACKE Operations (a) When ACKE is set to 1 at the e.
282 µ PD78214 Sub-Series (d) When ACKE is set to 1 for a short period of time Fig. 10-25 ACKD Operations (a) When the ACK signal is output during the ninth cycle of the SCK clock SCK SB0 ACKE The ACK.
283 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-26 BSYE Operation SCK SB0 BSYE 9 BUSY 8 7 6 ACK When BSYE = 1 at this point When reset operation is executed during this period and BSYE = 0 at the falling edge of SCK.
284 µ PD78214 Sub-Series Table 10-2 Signals in SBI Mode (1/3) SCK SB0 “ H ” “ H ” SCK SB0 Rising edge of SB0 while SCK is set to 1 Falling edge of SB0 while SCK is set to 1 Bus release signal (REL) Command signal (CMD) Output device Definition • RELT is set.
285 Chapter 10 Clock Synchronous Serial Interface 10 Table 10-2 Signals in SBI Mode (2/3) Low signal output to SB0 within a single cycle of the SCK clock after serial reception has been completed Low .
286 µ PD78214 Sub-Series Table 10-2 Signals in SBI Mode (3/3) Notes 1. If WUP is set to 0, CSIIF is always set at the rising edge of the eighth pulse of the SCK clock. If WUP is set to 1, CSIIF is set at the rising edge of the eighth pulse of the SCK clock only when an address is received.
287 Chapter 10 Clock Synchronous Serial Interface 10 10.6.8 Communication In SBI communication, the master device outputs an address on the serial bus and, usually, one target slave device is selected out of two or more devices according to the address.
288 µ PD78214 Sub-Series Fig. 10-27 Sending an Address from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 12345678 SB0 pin A7 Hardware operation A6 A5.
289 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-28 Sending a Command from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 12345678 SB0 pin C.
290 µ PD78214 Sub-Series Fig. 10-29 Sending Data from Master Device to Slave Device Program processing Hardware operation Program processing SCK pin 12345678 SB0 pin D7 Hardware operation D6 D5 D4 D3.
291 Chapter 10 Clock Synchronous Serial Interface 10 Fig. 10-30 Sending Data from the Slave Device to the Master Device Program processing Hardware operation Program processing SCK pin 12345678 12 SB0.
292 µ PD78214 Sub-Series 10.7 NOTES (1) Do not change CTXE from 0 to 1 and CRXE from 1 to 0, or vice versa, by means of a single instruction. If this is attempted, the serial clock counter will malfunction and the first communication after the change will be terminated before the eighth bit is sent.
293 11 CHAPTER 11 EDGE DETECTION FUNCTION Pins P20 to P26 support an edge detection function to program a rising or falling edge. The detected edge is sent to the internal hardware. Table 11-1 shows the relationship between pins P20 to P26, and the use of the detected edge.
294 µ PD78214 Sub-Series Fig. 11-1 Format of External Interrupt Mode Register 0 (INTM0) ES21 7 ES20 6 ES11 5 ES10 4 ES01 3 ES00 2 0 1 ESNMI 0 INTM0 ES01 Falling edge Specifies edge to be detected on .
295 Chapter 11 Edge Detection Function 11 Fig. 11-2 Format of External Interrupt Mode Register 1 (INTM1) 0 7 0 6 ES51 5 ES50 4 ES41 3 ES40 2 ES31 1 ES30 0 INTM1 ES31 Falling edge Specifies edge to be .
296 µ PD78214 Sub-Series 11.2 EDGE DETECTION ON PIN P20 An edge on pin P20 is detected after noise elimination by means of analog delay. A pulse width of at least 10 µ s is required to detect the edge.
297 Chapter 11 Edge Detection Function 11 11.3 EDGE DETECTION ON PINS P21 TO P26 An edge on pins P21 to P26 is detected after digital noise elimination by means of clock sampling. The digital noise elimination is performed by means of sampling with the f CLK /4 clock.
298 µ PD78214 Sub-Series (b) Erroneously detected edge during input of a high signal INTPn input (n = 0 to 6) Erroneously detected edge f CLK /4 After noise rejection Falling edge detection Rising ed.
299 Chapter 11 Edge Detection Function 11 (5) If noise input to pins P21 to P26 is synchronized with the f CLK /4 clock of the µ PD78214, it may not be judged as being noise. If the input of such noise is possible, add a filter to the input pin so that the noise can be eliminated.
300 µ PD78214 Sub-Series • Compare operation of the timer/counter : If the mode for carrying out a clear operation after a capture operation is selected, or if timer/counter 2 is used as an external event counter, the erroneously detected edge causes the timing of match interrupt generation to be changed.
301 12 CHAPTER 12 INTERRUPT FUNCTIONS The µ PD78214 has the following two interrupt handling modes. Either mode can be selected by the program. Interrupt handling by a macro service is limited to the interrupt request sources provided with a macro service handling mode listed in Table 12-1.
302 µ PD78214 Sub-Series 12.1 INTERRUPT REQUEST SOURCES The µ PD78214 has 19 interrupt request sources shown in Table 12-2. Each of these sources is assigned an interrupt vector table.
303 Chapter 12 Interrupt Functions 12 12.1.2 Nonmaskable Interrupt Request A nonmaskable interrupt request is input to the NMI pin. When a valid edge, specified by bit 0 (ESNMI) of external interrupt mode register 0 (INTM0), is input to the NMI pin, an interrupt request is generated.
304 µ PD78214 Sub-Series (2) Selecting INTP5 or INTAD Interrupt INTP5 or INTAD is selected by the A/D converter mode register (ADM). (Either of these interrupts is selected automatically, according to the mode of operation specified for the A/D converter.
305 Chapter 12 Interrupt Functions 12 Table 12-3 Flags for Interrupt Request Sources INTP0 INTP1 INTP2 INTP3 INTC00 INTC01 INTC10 INTC11 INTC21 INTP4 INTC30 INTP5 INTAD INTC20 INTSER INTSR INTST INTCS.
306 µ PD78214 Sub-Series 12.2.2 Interrupt Mask Register (MK0) The MK0 register is a 16-bit register consisting of interrupt mask flags. Each interrupt mask flag enables or disables the corresponding interrupt request. When the RESET signal is input, the register is set to FFFFH, thus disabling all maskable interrupts.
307 Chapter 12 Interrupt Functions 12 When a low-priority vectored interrupt is being handled, vectored interrupt requests with lower and higher priorities are accepted for multiple-interrupt handling provided that interrupts are enabled.
308 µ PD78214 Sub-Series 12.2.6 Program Status Word (PSW) The PSW is a register that holds the result of instruction execution and the current status of interrupt requests. The register is mapped with the IE flag that specifies whether to enable maskable interrupts and the ISP flag to control multiple-interrupt handling.
309 Chapter 12 Interrupt Functions 12 Resetting the NMIS bit to 0 during execution of a nonmaskable interrupt service program enables multiple- interrupt handling for nonmaskable interrupt requests. If the NMIS bit is 0, a new nonmaskable interrupt request is accepted even when a nonmaskable interrupt service program is running.
310 µ PD78214 Sub-Series (c) If a new NMI request occurs during execution of an NMI service program (when the NMIS bit is reset to 0 by the current NMI service program after the NMI request occurs) (.
311 Chapter 12 Interrupt Functions 12 3. Nonmaskable interrupts are always accepted except during execution of the nonmaskable interrupt handling program (except when multiple-interrupt handling for n.
312 µ PD78214 Sub-Series Fig. 12-10 Interrupt Handling Algorithm Interrupts for ×× PR = 0 occur simultaneously? ×× IF = 1? ×× MK = 0? ×× PR = 0? Y es (interrupt request occurs) Ye s No (low p.
313 Chapter 12 Interrupt Functions 12 12.3.4 Multiple-Interrupt Handling The µ PD78214 performs multiple-interrupt handling in which another interrupt request is accepted during one interrupt is already being handled. Multiple-interrupt handling runs according to priority.
314 µ PD78214 Sub-Series Fig. 12-11 Example of Handling an Interrupt Request When an Interrupt Is Already Being Handled (1/2) Main routine Processing a Vectored interrupt request e (high priority) .
315 Chapter 12 Interrupt Functions 12 Fig. 12-11 Example of Handling an Interrupt Request When an Interrupt Is Already Being Handled (2/2) Main routine Processing i Vectored interrupt request k (low p.
316 µ PD78214 Sub-Series Fig. 12-12 Example of Handling Interrupts That Occur Simultaneously 12.3.5 Interrupt Request and Macro Service Pending When any of the following instructions is executed, all interrupts (including nonmaskable interrupts) and macro services are kept pending.
317 Chapter 12 Interrupt Functions 12 Example of correct coding (2) LOOP: BT IF0H.3, $NEXT BR $LOOP NEXT: ← 2. In addition, when you have to use a coding of the instructions listed above consecutive.
318 µ PD78214 Sub-Series 3. “ Peripheral RAM ” corresponds to the internal RAM at addresses 0FC80H through 0FDFFH (for the µ PD78212, 0FD80H through 0FDFFH).
319 Chapter 12 Interrupt Functions 12 12.4 MACRO SERVICE FUNCTION 12.4.1 Macro Service Outline Macro service is one of the interrupt handling methods. When a vectored interrupt is processed, the conte.
320 µ PD78214 Sub-Series 12.4.2 Macro Service Types The macro service can be used by the 17 types of interrupts listed in Table 12-7 (of which, 15 types can use macro services simultaneously). In addition, three modes of operation are available, and each should be selected according to the application.
321 Chapter 12 Interrupt Functions 12 (3) Type C Transfers 1-byte data from memory to the real-time output port and the compare register for 8-bit timer/ counter 1 upon each interrupt request. When a specified number of data transfers are performed, a vectored interrupt request is generated.
322 µ PD78214 Sub-Series 12.4.4 Macro Service Control Register (1) Macro service control word The macro service function of the µ PD78214 is controlled using the macro service mode registers and macro service channel pointers.
323 Chapter 12 Interrupt Functions 12 (2) Macro service mode register A macro service mode register is an 8-bit register that specifies the mode of macro service operation. It is mapped in internal RAM as part of macro service control word (see Fig 12-16 ).
324 µ PD78214 Sub-Series Table 12-8 Interrupt Requests That Can Specify Macro Service and Related SFRs (Type A) Interrupt request specifying the type A macro service Transfer source/destination SFR C.
325 Chapter 12 Interrupt Functions 12 Fig. 12-18 Flow of Data Transfer by Macro Service (Type A) Accepts macro service request Read contents of macro service mode register Identify channel type Read c.
326 µ PD78214 Sub-Series (2) Macro service channel configuration A channel pointer and a macro service counter (MSC) specify the addresses of transfer source and destination buffers in the internal RAM (at FE00H through FEFFH). (See Fig. 12-19 .) The SFR to be accessed is predetermined for each interrupt request.
327 Chapter 12 Interrupt Functions 12 (3) Example of using the type A macro service The following example shows how data received through an asynchronous serial interface is transferred to a buffer area in the internal RAM. Fig. 12-20 Asynchronous Serial Reception 12.
328 µ PD78214 Sub-Series Fig. 12-21 Flow of Data Transfer by Macro Service (Type B) Accepts macro service request Read contents of macro service mode register Identify channel type Read channel point.
329 Chapter 12 Interrupt Functions 12 (2) Macro service channel configuration The macro service pointer (MP) indicates a data buffer area in the 64K memory space as a transfer source or destination. The SFR pointer (SFRP) is set with the lower 8 bits of the address of an SFR used as a transfer source or destination.
330 µ PD78214 Sub-Series (3) Example of using the type B macro service The following example shows how parallel data is input from port 3 in synchronization with an external signal. The external signal is input to the external interrupt pin (INTP4). Fig.
331 Chapter 12 Interrupt Functions 12 12.4.7 Macro Service Type C (1) Operation The type C macro service controls 8-bit timer/counter 1 and the real-time output port simultaneously.
332 µ PD78214 Sub-Series Fig. 12-25 Flow of Data Transfer by Macro Service (Type C) Accepts macro service request Read contents of macro service mode register Identify channel type Read channel point.
333 Chapter 12 Interrupt Functions 12 Ring control? Decrement ring counter Ring counter = 0? Vectored interrupt request occurs No No Yes No Subtract modulo register contents from low-order 8-bits of m.
334 µ PD78214 Sub-Series (2) Macro service channel configuration There are two types of type C macro service channels, as shown in Fig. 12-26. The timer macro service pointer (MPT) indicates a data buffer area in the 64K memory space from which data is transferred to, or added to the contents of, the compare register for 8-bit timer/counter 1.
335 Chapter 12 Interrupt Functions 12 (b) With ring control Modulo register (MR) Ring counter (RC) Macro service counter (MSC) Data macro service pointer, low (MPDL) Data macro service pointer, high (.
336 µ PD78214 Sub-Series (3) Example of using the type C macro service The following example shows a pattern output to the real-time output port and how the output interval is controlled directly.
337 Chapter 12 Interrupt Functions 12 Fig. 12-28 Data Transfer Control Timing (4) Example of using automatic addition control and ring control (a) Automatic addition control The automatic addition con.
338 µ PD78214 Sub-Series Fig. 12-29 Four-Phase Stepping Motor with Phase 1 Excitation Fig. 12-30 Four-Phase Stepping Motor with Phases 1 and 2 Excitation 1234123 1 cycle (4 patterns) Phase A Phase B .
339 Chapter 12 Interrupt Functions 12 Fig. 12-31 Block Diagram 1 for Automatic Addition Control Plus Ring Control (Constant-Speed Rotation with Phases 1 and 2 Excitation) MSC FF – 1 Ring counter (RC.
340 µ PD78214 Sub-Series Fig. 12-32 Timing Chart 1 for Automatic Addition Control Plus Ring Control (Constant-Speed Rotation with Phases 1 and 2 Excitation) T0 T2 T1+ ∆ t T3 T2+ ∆ t T4 T3+ ∆ t .
341 Chapter 12 Interrupt Functions 12 Fig. 12-33 Block Diagram 2 for Automatic Addition Control Plus Ring Control (with the Output Timing Varied by Phase 2 Excitation) MSC FF – 1 Ring counter (RC) 0.
342 µ PD78214 Sub-Series Fig. 12-34 Timing Chart 2 for Automatic Addition Control Plus Ring Control (with the Output Timing Varied by Phase 2 Excitation) ∆ t9 T1 T0+ ∆ t1 T2 T1+ ∆ t2 T3 T2+ ∆.
343 Chapter 12 Interrupt Functions 12 12.5 NOTES (1) Do not use the RETI instruction to return from the software interrupt. (2) A macro service request is accepted and processed even when a nonmaskable interrupt service program is running.
344 µ PD78214 Sub-Series Example of correct coding (2) LOOP: BT IF0H.3, $NEXT BR $LOOP NEXT: ← (6) In addition, when you have to use a coding of the instructions listed in Section 12.
345 13 CHAPTER 13 LOCAL BUS INTERFACE FUNCTION The local bus interface function is provided to connect external memories (ROM and RAM) and I/Os. External memories (ROM and RAM) and I/Os are accessed by using the RD, WR, and ASTB signals, a multiplexed address/data bus consisting of lines AD0 to AD7, and an address bus consisting of lines A8 to A19.
346 µ PD78214 Sub-Series 13.1 CONTROL REGISTERS 13.1.1 Memory Expansion Mode Register (MM) The MM register is an 8-bit register for controlling externally expanded memory, specifying the number of wait states (address space: 00000H to 0FFFFH), and controlling the internal fetch cycle.
347 Chapter 13 Local Bus Interface Function 13 13.1.2 Programmable Wait Control Register (PW) The PW register is an 8-bit register for specifying the number of wait states for external expansion data memory space 10000H to FFFFFH. The PW register can be read and written with both 8-bit manipulation instructions and bit manipulation instructions.
348 µ PD78214 Sub-Series Fig. 13-3 Read Timing Higher address Lower address (output) Data (input) Hi-Z Hi-Z A8-A15 (output) AD0-AD7 ASTB (output) RD (output) Hi-Z Fig.
349 Chapter 13 Local Bus Interface Function 13 Fig. 13-5 Accessing Expansion Data Memory (a) Read cycle RD (output) A16-A19 (output) Contents of P6/PM6 register Higher address Higher address Lower add.
350 µ PD78214 Sub-Series 13.2.3 Memory Mapping with Expanded Memory Figs. 13-6 to 13-9 show the memory maps when the memory has been expanded. Even when the memory has been expanded, external devices.
351 Chapter 13 Local Bus Interface Function 13 Fig. 13-6 Data Memory Expansion for µ PD78212 (When EA = L) Internal RAM External SFR area SFR 0FD7FH 0FD80H 0FEFFH 0FF00H 0FFD0H 0FFFFH 0FFDFH 00000H M.
352 µ PD78214 Sub-Series Fig. 13-7 Data Memory Expansion for µ PD78212 (When EA = H) Internal RAM External SFR area SFR External memory Internal RAM External SFR area SFR 10000H MM2, MM1, MM0 = 1, 1.
353 Chapter 13 Local Bus Interface Function 13 Fig. 13-8 Data Memory Expansion for µ PD78213 and µ PD78214 (When EA = L) Internal RAM External SFR area SFR 0FCFFH 0FD00H 0FEFFH 0FF00H 0FFD0H 0FFFFH .
354 µ PD78214 Sub-Series Fig. 13-9 Data Memory Expansion for µ PD78214 and µ PD78P214 (When EA = H) Internal RAM External SFR area SFR External memory Internal RAM External SFR area SFR 10000H MM2,.
355 Chapter 13 Local Bus Interface Function 13 13.2.4 Example of Connecting Memories Fig. 13-10 shows an example of connecting memories to the µ PD78214.
356 µ PD78214 Sub-Series Fig. 13-10 Example of Connecting Memories to µ PD78214 PD23C4000A µ PD43256AC-12 µ PD27C512D-15 µ LE D0-D7 OE Q0-Q7 AD0-AD7 ASTB A8-A14 OE CE A17 A16 A15 A14 A-1-A13 CS W.
357 Chapter 13 Local Bus Interface Function 13 13.3 INTERNAL ROM HIGH-SPEED FETCH FUNCTION The µ PD78212, µ PD78214, and µ PD78P214 contain an internal ROM. The internal ROM can be accessed quickly without having to use the bus control circuit. Usually, internal ROM is fetched at the same speed as external ROM.
358 µ PD78214 Sub-Series Fig. 13-11 Wait Control Space of µ PD78212 (When EA = L) Internal RAM External SFR area SFR 0FD7FH Expansion data memory 00000H External memory 0FD80H 0FEFFH 0FF00H 0FFFFH 1.
359 Chapter 13 Local Bus Interface Function 13 Fig. 13-12 Wait Control Space of µ PD78212 (When EA = H) Internal RAM External SFR area SFR 0FD7FH Expansion data memory 00000H External memory 0FD80H 0.
360 µ PD78214 Sub-Series Fig. 13-13 Wait Control Space of µ PD78213 and µ PD78214 (When EA = L) Internal RAM External SFR area SFR 0FCFFH Expansion data memory 00000H External memory 0FD00H 0FEFFH .
361 Chapter 13 Local Bus Interface Function 13 Fig. 13-14 Wait Control Space of µ PD78214 and µ PD78P214 Internal RAM External SFR area SFR 0FCFFH Expansion data memory 00000H External memory 0FD00H.
362 µ PD78214 Sub-Series Fig. 13-15 Read Timing of Programmable Wait Function (1/2) (a) When zero wait states are set Higher address Lower address (output) Data (input) Hi-Z Hi-Z A8-A15 (output) AD0-.
363 Chapter 13 Local Bus Interface Function 13 Fig. 13-15 Read Timing of Programmable Wait Function (2/2) (c) When two wait states are set Higher address Lower address (output) Data (input) Hi-Z Hi-Z .
364 µ PD78214 Sub-Series Fig. 13-16 Write Timing of Programmable Wait Function (1/2) (a) When zero wait states are set Higher address Lower address Data Hi-Z Hi-Z A8-A15 (output) AD0-AD7 (output) AST.
365 Chapter 13 Local Bus Interface Function 13 Fig. 13-16 Write Timing of Programmable Wait Function (2/2) (c) When two wait states are set Higher address Lower address Data Hi-Z Hi-Z A8-A15 (output) .
366 µ PD78214 Sub-Series Fig. 13-17 Timing When External Wait Signal Is Used (a) Read timing Higher address Lower address (output) Data (input) Hi-Z Hi-Z A8-A15 (output) AD0-AD7 ASTB (output) RD (out.
367 Chapter 13 Local Bus Interface Function 13 13.5 PSEUDO STATIC RAM REFRESH FUNCTION 13.5.1 Function The µ PD78214 provides the pseudo static RAM refresh function to enable pseudo static RAM to be connected directly. The pseudo static RAM refresh function outputs refresh pulses at arbitrary intervals.
368 µ PD78214 Sub-Series 13.5.3 Operation (1) Pulse refresh operation To support the pulse refresh cycle of pseudo static RAM, the REFRQ pin outputs refresh pulses, synchronized with the bus cycle.
369 Chapter 13 Local Bus Interface Function 13 (b) Accessing External Memory The refresh bus cycle is generated at the intervals specified with the refresh mode register (RFM).
370 µ PD78214 Sub-Series (2) Self-refresh Self-refresh is performed to retain the contents of pseudo static RAM when in standby mode. (a) Setting self-refresh mode When bit 4 (RFEN) of the RFM register is set to 1, and bit 7 (RFLV) is set to 0, pin REFRQ outputs a low-level signal, requesting pseudo static RAM to enter self-refresh mode.
371 Chapter 13 Local Bus Interface Function 13 Caution If the RFEN bit of the refresh mode register (RFM) is already set to 1 (or is simultaneously set to 1) when the RFLV bit is changed from 0 to 1, pin REFRQ may output a glitch, having a peak level of approximately 2.
372 µ PD78214 Sub-Series 13.5.4 Example of Connecting Pseudo Static RAM Fig. 13-23 shows an example of connecting pseudo static RAM to the µ PD78214. In this example, pseudo static RAM is assigned to addresses 20000H to 3FFFFH. Fig. 13-23 Example of Connecting Pseudo Static RAM to µ PD78214 Remarks 1.
373 Chapter 13 Local Bus Interface Function 13 (3) When macro service Type A or Type C is used in external memory expansion mode (the µ PD78213 always uses external memory), an illegal write access may occur.
374 µ PD78214 Sub-Series Fig. 13-24 Return from Self-Refresh Clear RFEN bit to 0 Set RFLV bit to 1 Set RFEN bit to 1 Approximately 200 ns delay RFLV = 1 Yes No Self-refresh mode Pulse refresh mode (n.
375 Chapter 13 Local Bus Interface Function 13 Fig. 13-27 Preventing Problems That May Occur during Emulation A19 To target circuit A18 A17 A16 ASTB Q 4 Q 3 Q 2 Q 1 D 4 D 3 D 2 D 1 Target probe 74HC37.
376.
377 14 CHAPTER 14 STANDBY FUNCTION 14.1 FUNCTION OVERVIEW The µ PD78214 supports a standby function to reduce the system’s power consumption. With the standby function, two modes are available: • HALT mode: In this mode, only the CPU clock is stopped.
378 µ PD78214 Sub-Series Fig. 14-2 Standby Function Block System clock oscillator Frequency divider Oscillation settling time counter (16 bits) fxx or fx f CLK STP flip-flop 1 Q Q S R STP flip-flop 2.
379 Chapter 14 Standby Function 14 14.2 STANDBY CONTROL REGISTER (STBC) The standby control register (STBC) is an 8-bit register which controls standby mode.
380 µ PD78214 Sub-Series 14.3.2 Releasing HALT Mode HALT mode can be released by any of the following three sources: • Nonmaskable interrupt request (NMI) • Maskable interrupt request (vectored i.
381 Chapter 14 Standby Function 14 (2) Release by a maskable interrupt request Only maskable interrupts with 0 in the interrupt mask flag can be used to release HALT mode.
382 µ PD78214 Sub-Series 14.4 STOP MODE 14.4.1 Specifying STOP Mode and Operation States in STOP Mode The system enters STOP mode when the STP bit of the STBC register is set to 1. The STBC register can be written only with a specified 8-bit data write instruction.
383 Chapter 14 Standby Function 14 Fig. 14-4 Releasing STOP Mode with an NMI Signal Caution If another effective edge of the NMI signal is detected during the oscillation settling time, the oscillation settling time counter is cleared and restarts counting, resulting in a longer wait time than usual.
384 µ PD78214 Sub-Series 14.4.3 Notes on Using STOP Mode Check the following items to ensure that current consumption is appropriately reduced in STOP mode: (1) Is the output level of each output pin appropriate? The appropriate output level of each pin depends on the circuit of the next stage.
385 Chapter 14 Standby Function 14 Fig. 14-6 Example of Address Bus Arrangement Power supply backed up V DD V DD V SS V SS IN Diode with small V F An (n = 8 to 15) Power supply not backed up CMOS IC , etc. PD78214 µ The outputs of the address/data bus pins are high-impedance in STOP mode.
386 µ PD78214 Sub-Series Fig. 14-8 Example Arrangement for Analog Input Pin V DD V SS ANn (n = 0 to 7) Power supply backed up PD78214 µ AV REF Diode with small V F Power supply not backed up Signal source The voltage input to the AN0 to AN7 pins must be maintained at a level between V SS and V DD .
387 Chapter 14 Standby Function 14 Fig. 14-9 Example of Longer Oscillation Settling Time NMI (effective at falling edge) 2 16 /f CLK STOP mode Wait for oscillation to settle Normal operation Oscillation settling time is extended by this period.
388.
389 15 CHAPTER 15 RESET FUNCTION 15.1 RESET FUNCTION When the signal applied to the RESET input pin is low, the system is reset, and each hardware component is set to the state indicated in Table 15-2. All pins, except the power supply pin, assume the high-impedance state.
390 µ PD78214 Sub-Series Table 15-1 Pin States during Reset and After Reset State Is Released Pin name P00-P07 P20/NMI-27/SI P30/RxD-P37/TO3 P40/AD0-P47/AD7 P50/A8-P57/A15 P60/A16-P63/A19 P64/RD, P65.
391 Chapter 15 Reset Function 15 Table 15-2 Hardware States after Reset (1/2) State after reset Hardware Program counter (PC) Stack pointer (SP) Program status word (PSW) Data memory General registers.
392 µ PD78214 Sub-Series Table 15-2 Hardware States after Reset (2/2) State after reset Hardware Mode register (CSIM) Shift register (SIO) Asynchronous mode register (ASIM) Asynchronous status regist.
393 Chapter 15 Reset Function 15 Fig. 15-3 Timing Charts for Reset Operation (a) For µ PD78213 (b) For µ PD78214 15.2 NOTE When resetting the system at power-on, do not set the RESET signal high immediately after the supply voltage reaches the specified level.
394.
395 16 CHAPTER 16 APPLICATION EXAMPLES 16.1 OPEN-LOOP CONTROL OF STEPPER MOTORS This section provides an example of controlling stepper motors with the real-time output function, 8-bit timer/ counter 1, and the macro service function of the µ PD78214.
396 µ PD78214 Sub-Series Fig. 16-1 Example of Controlling Two Stepper Motors Internal bus Internal bus Compare register CR11 8-bit timer 1 TM1 Buffer register P0H Output latch Output latch Buffer reg.
397 Chapter 16 Application Examples 16 16.2 SERIAL COMMUNICATION WITH MULTIPLE DEVICES Fig. 16-2 shows an example of a system configured with a serial bus interface.
398 µ PD78214 Sub-Series Fig. 16-3 Example of Communication with SBI Address Command Command SB0 Address Command Data Command SB0 Address Command Data Data SB0 Address Data Data Data SB0 Address Data Data Command Data SB0 : Bus release : Command trigger Fig.
399 17 CHAPTER 17 PROGRAMMING FOR THE µ PD78P214 The µ PD78P214 employs an electrically writable PROM of 16384 × 8 bits for program memory. Use the NMI and RESET pins to set the µ PD78P214 to PROM programming mode when programming the PROM. The µ PD78P214 provides programming characteristics compatible with the µ PD27C256A Note .
400 µ PD78214 Sub-Series Fig. 17-1 Timing Chart for PROM Write and Verify Hi-Z Data input A0-A14 Data output Data input Hi-Z Hi-Z Hi-Z +12.5 V D0-D7 V DD V pp +6 V V DD V DD CE (input) 3X ms Write Ve.
401 Chapter 17 Programming for The µ PD78214 17 Fig. 17-2 Write Operation Flowchart 17.3 PROCEDURE FOR READING FROM PROM The contents of PROM can be read out to the external data bus (D0 to D7) by following the procedure below: (1) Fix the RESET pin to the low level.
402 µ PD78214 Sub-Series Fig. 17-3 PROM Read Timing Chart Address input A0-A14 Hi-Z Data output CE (input) OE (input) D0-D7 Hi-Z 17.4 NOTE When V PP is +12.
403 18 CHAPTER 18 INSTRUCTION OPERATIONS This chapter describes the operation of each instruction of the µ PD78214 sub-series. Refer to the 78K/II Series User’s Manual, Instructions (IEU-1311) for details of each operation, the corresponding machine language code (instruction code), and the number of clock states for each instruction.
404 µ PD78214 Sub-Series saddr, saddr’ : Memory address indicated in short direct addressing mode; FE20H-FF1FH immediate data or label saddrp : Memory address indicated in short direct addressing p.
405 Chapter 18 Instruction Operations 18 Z : Zero flag RBS1-RBS0 : Register bank selection flag IE : Interrupt request enable flag STBC : Standby control register jdisp8 : Signed 8-bit data (displacem.
406 µ PD78214 Sub-Series MOV XCH Operation Mnemonic Operand No. of bytes Flags ZA C C Y 18.2 LIST OF OPERATIONS (1) 8-bit data transfer instructions: MOV, XCH r, #byte 2 r ← byte saddr, #byte 3 (sa.
407 Chapter 18 Instruction Operations 18 MOVW Operation Mnemonic Operand No. of bytes Flags rp, #word 3 rp ← word saddrp, #word 4 (saddrp) ← word sfrp, #word 4 sfrp ← word rp, rp' 2 rp ← .
408 µ PD78214 Sub-Series SUB SUBC AND OR Operation Mnemonic Operand No. of bytes Flags A, #byte 2 A, CY ← A – byte × × × saddr, #byte 3 (saddr), CY ← (saddr) – byte × × × sfr, #byte 4 s.
409 Chapter 18 Instruction Operations 18 XOR CMP Operation Mnemonic Operand No. of bytes Flags A, #byte 2 A ← A ∨ byte × saddr, #byte 3 (saddr) ← (saddr) ∨ byte × sfr, #byte 4 sfr ← sfr .
410 µ PD78214 Sub-Series ROR ROL RORC ROLC SHR SHL SHRW SHLW ROR4 ROL4 Operation Mnemonic Operand No. of bytes Flags r, n 2 (CY, r 7 ← r 0 , r m-1 ← r m ) × n times n=0 to 7 × r, n 2 (CY, r 0 .
411 Chapter 18 Instruction Operations 18 ADJBA ADJBS Operation Mnemonic Operand No. of bytes Flags ZA C C Y 1 Use the decimal adjust accumulator after addition. ×× × 1 Use the decimal adjust accumulator after subtraction. ×× × MOV1 AND1 OR1 Operation Mnemonic Operand No.
412 µ PD78214 Sub-Series XOR1 SET1 CLR1 NOT1 Operation Mnemonic Operand No. of bytes Flags ZA C C Y CY, saddr.bit 3 CY ← CY ∨ (saddr.bit) × CY, sfr.bit 3 CY ← CY ∨ sfr.bit × CY, A.bit 2 CY ← CY ∨ A.bit × CY, X.bit 2 CY ← CY ∨ X.bit × CY, PSW.
413 Chapter 18 Instruction Operations 18 CALL CALLF CALLT BRK RET RETI RETB Operation Mnemonic Operand No. of bytes Flags ZA C C Y !addr16 3 (SP – 1) ← (PC + 3) H , (SP – 2) ← (PC + 3) L , PC .
414 µ PD78214 Sub-Series BC BL BNC BNL BZ BE BNZ BNE BT BF BTCLR DBNZ Operation Mnemonic Operand No. of bytes Flags $ addr16 2 PC ← PC + 2 + jdisp8 if CY = 1 addr16 2 PC ← PC + 2 + jdisp8 if CY = 0 $ addr16 2 PC ← PC + 2 + jdisp8 if Z = 1 $ addr16 2 PC ← PC + 2 + jdisp8 if Z = 0 saddr.
415 Chapter 18 Instruction Operations 18 MOV SEL NOP EI DI Operation Mnemonic Operand No. of bytes Flags STBC, #byte 4 STBC ← byte RBn 2 RBS1 – 0 ← n, n = 0 – 3 1 No operation 1 IE ← 1 (Enab.
416 µ PD78214 Sub-Series First operand Second operand # byte A sfr mem & mem !addr16 & !addr16 PSW n None Note 2 r r' saddr saddr' MOV XCH MOV XCH ADD Note 1 MOV MOV XCH ADD Note 1 .
417 Chapter 18 Instruction Operations 18 (2) 16-bit instructions MOVW, ADDW, SUBW, CMPW, INCW, DECW, SHRW, and SHLW Table 18-2 16-Bit Instructions for Each Addressing Type First operand Second operand.
418 µ PD78214 Sub-Series (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, and BTCLR Table 18-3 Bit Manipulation Instructions for Each Addressing Type First operand Second operand CY A. bit None Note MOV1 AND1 OR1 XOR1 CY /A.
419 Chapter 18 Instruction Operations 18 (4) Call instructions and branch instructions CALL, CALLF, CALLT, BR, BC, BT, BF, BTCLR, DBNZ, BL, BNC, BNL, BZ, BE, BNZ, and BNE Table 18-4 Call Instructions .
420.
421 A APPENDIX A 78K/II SERIES PRODUCT LIST The following pages list the 78K/II series products. For details, refer to each User’s Manual..
422 µ PD78214 Sub-Series Series name µ PD78214 Sub-Series µ PD78218A Sub-Series µ PD78224 Sub-Series µ PD78214 ( µ PD78P214) Number of basic instructions Minimum instruction execution time µ PD.
423 Appendix A 78K/II Series Product List A (1/3) µ PD78234 Sub-Series µ PD78244 Sub-Series µ PD78233 µ PD78243 µ PD78238 ( µ PD78P238) µ PD78237 500 ns 333 ns 333 ns 500 ns 333 ns 500 ns 65 (i.
424 µ PD78214 Sub-Series Series name µ PD78214 Sub-Series µ PD78218A Sub-Series µ PD78224 Sub-Series µ PD78214 ( µ PD78P214) PWM output Comparator µ PD78213 µ PD78212 µ PD78224 ( µ PD78P224).
425 Appendix A 78K/II Series Product List A (2/3) µ PD78234 Sub-Series µ PD78244 Sub-Series µ PD78233 µ PD78243 µ PD78238 ( µ PD78P238) µ PD78237 None 8 bits × 8 µ PD78234 µ PD78244 12 bits .
426 µ PD78214 Sub-Series Series name µ PD78214 Sub-Series µ PD78218A Sub-Series µ PD78224 Sub-Series µ PD78214 ( µ PD78P214) Interrupt µ PD78213 µ PD78212 µ PD78224 ( µ PD78P224) µ PD78220 .
427 Appendix A 78K/II Series Product List A (3/3) µ PD78234 Sub-Series µ PD78244 Sub-Series µ PD78233 µ PD78243 µ PD78238 ( µ PD78P238) µ PD78237 7 2 levels (programmable), vector/macro service 8/16 bits selectable (except type A) 15 Occurs when transferred data is D0H to DFH Depends on mode.
428.
429 B APPENDIX B DEVELOPMENT TOOLS The development tools described on the following pages are available for the development of systems using µ PD78214 sub-series.
430 µ PD78214 Sub-Series IE-78210-R Note 2 IE-78240-R IE-78240-R-A In-circuit emulator Emulation probe EP-78210CW Note 2 EP-78210GC Note 2 EP-78210GJ EP-78210GQ Note 2 EP-78210L Note 2 EP-78240CW-R E.
431 Appendix B Development Tools B IE-78240-R-A The IE-78240-R-A is an enhanced version of the IE-78210-R and IE-78240-R. This in-circuit emulator can be used for any model of the µ PD78214 sub-series. It operates with a PC-9800 series or IBM PC/AT host machine.
432 µ PD78214 Sub-Series HARDWARE (2/2) This socket is mounted on the board of the user system developed for the 74- pin QFP. It is used together with the EP-78210GJ or EP-78240GJ-R. This socket is mounted on the board of the user system developed for the 64- pin QFP.
433 Appendix B Development Tools B B.2 SOFTWARE B.2.1 Language Processing Software (1/3) 78K/II series relocatable assembler (RA78K/II) This relocatable assembler can be used for all the 78K/II series products. Its macro functions enhance efficiency in software development.
434 µ PD78214 Sub-Series OS µ S5A1RA78K2 µ S5A10RA78K2 µ S5A13RA78K2 µ S7B11RA78K2 µ S7B10RA78K2 µ S7B13RA78K2 µ S3H15RA78K2 µ S3K15RA78K2 µ S3M15RA78K2 Part number Distribution medium Host machine HP-UX TM (rel.7.05B) Sun OS TM (rel.4.1.1) EWS-UX/V TM (rel.
435 Appendix B Development Tools B OS µ S5A10CC78K2-L µ S5A13CC78K2-L µ S7B10CC78K2-L µ S7B13CC78K2-L µ S3H15CC78K2-L µ S3K15CC78K2-L µ S3M15CC78K2-L Part number 5.
436 µ PD78214 Sub-Series This program enables control of the in-circuit emulator for the 78K/II series from the host machine. It can automatically execute commands, thus enhancing efficiency in debugging.
437 Appendix B Development Tools B This program provides the serial and parallel interfaces between PG-1500 and the host machine, enabling the host machine to control the PG-1500. PG-1500 controller OS µ S5A10PG1500 µ S5A13PG1500 µ S7B11PG1500 µ S7B10PG1500 µ S5A13PG1500 Part number 5-inch 2HD 3.
438 µ PD78214 Sub-Series B.3 UPGRADING OTHER IN-CIRCUIT EMULATORS TO 78K/II SERIES LEVEL The 78K series and 75X series in-circuit emulators can be upgraded to the level of the 78K/II series by replacing their internal boards with an optional board. Note that the upgraded in-circuit emulator requires an appropriate new control program.
439 Appendix B Development Tools B IE-78112-R Note 1 IE-78210-R Note 1 IE-78220-R Note 1 IE-78130-R IE-78230-R Note 1 IE-78310-R Note 1 IE-78310A-R IE-75000-R IE-75001-R IE-78000-R IE-78320-R Note 1 I.
440 µ PD78214 Sub-Series IE-78112-R Note 2 IE-78220-R Note 2 IE-78310-R Note 2 IE-78310A-R IE-75000-R IE-75001-R IE-78000-R IE-78130-R IE-78140-R IE-78230-R IE-78230-R-A IE-78240-R IE-78240-R-A IE-78.
441 C APPENDIX C SOFTWARE FOR EMBEDDED APPLICATIONS C.1 FUZZY INFERENCE DEVELOPMENT SUPPORT SYSTEM OS µ S5A10FE9000 µ S5A13FE9000 µ S7B10FE9200 µ S7B13FE9200 Part number 5.25-inch 2HD 3.5-inch 2HD 5.25-inch 2HC 3.5-inch 2HC Distribution medium MS-DOS (Ver.
442.
443 D APPENDIX D REGISTER INDEX D.1 REGISTER INDEX 16-bit capture register (CR02) ... 111 16-bit compare register (CR00,CR01) ... 111 16-bit timer 0 (TM0) ... 111 8-bit capture/compare register (CR11) ... 142 8-bit capture register (CR22) ... 161 8-bit compare register (CR10) .
444 µ PD78214 Sub-Series Port 3 (P3) ... 66 Port 4 (P4) ... 75 Port 5 (P5) ... 80 Port 6 (P6) ... 84 Port 7 (P7) ... 92 Port 0 buffer register (P0L, P0H) ... 97 Port 0 mode register (PM0) ... 61 Port 3 mode control register (PMC3) ... 72 Port 3 mode register (PM3) .
445 Appendix D Register Index D D.2 REGISTER SYMBOL INDEX A ADCR: A/D conversion result register ... 227 ADM: A/D converter mode register ... 229, 304 ASIM: Asynchronous serial interface mode register ... 245 ASIS: Asynchronous serial interface status register .
446 µ PD78214 Sub-Series PM0: Port 0 mode register ... 61 PM3: Port 3 mode register ... 72 PM5: Port 5 mode register ... 80 PM6: Port 6 mode register ... 89 PMC3: Port 3 mode control register ... 72 PR0: Priority specification flag register ... 306 PRM0: Prescaler mode register 0 .
447 E APPENDIX E INDEX E.1 INDEX 0 parity ... 247, 248 16-bit timer 0 ... 111, 114 16-bit timer/counter ... 109 1M-byte expansion function ... 348 4-bit counter ... 251 4-bit separate real-time output port ... 97 64-pin ceramic shrink DIP with window .
448 µ PD78214 Sub-Series Clock synchronous serial interface mode register ... 262, 273 Command ... 279 Command detection flag ... 274 Command signal ... 278 Command trigger bit ... 274 Compare operation ... 117, 148, 176, 210 Compare register ... 111, 161, 142, 148, 206 Controlling multiple-interrupt handling .
449 Appendix E Index E Interrupt status register ... 304, 307 Interval timer ... 129, 151, 190, 192, 210, 211 Interval ... 109, 139, 159, 205 L Local bus interface function ... 345 Loop counter ... 49 M Macro service ... 301, 319 Macro service channel .
450 µ PD78214 Sub-Series Port 3 mode control register ... 72 Port 3 mode register ... 71 Port 4 ... 75 Port 5 ... 80 Port 5 mode register ... 80 Port 6 ... 84 Port 6 mode register ... 89 Port 7 ... 92 Port mode ... 346, 367 Prescaler ... 142, 163, 206 Prescaler mode register 0 .
451 Appendix E Index E Special function register ... 43, 50 Specifying 1M-byte expansion mode ... 346 Specifying the operation of the capture/compare register ... 144 Stack pointer ... 46 Standby control register ... 379 Standby function ... 377 Standby mode .
452 µ PD78214 Sub-Series E.2 SYMBOL INDEX A A ... 48 A0 ... 31 A1 ... 31 A2 ... 31 A3 ... 31 A4 ... 31 A5 ... 31 A6 ... 31 A7 ... 31 A8 ... 29, 31, 345 A9 ... 29, 31, 345 A10 ... 29, 31, 345 A11 ... 29, 31, 345 A12 ... 29, 31, 345 A13 ... 29, 31, 345 A14 .
453 Appendix E Index E CE2 ... 163, 167 CE3 ... 207, 208 CHT0 ... 323 CHT1 ... 323 CHT2 ... 323 CI ... 28, 161, 170 CIF00 ... 305 CIF01 ... 305 CIF10 ... 305 CIF11 ... 305 CIF20 ... 305 CIF21 ... 305 CISM00 ... 306 CISM01 ... 306 CISM10 ... 306 CISM11 .
454 µ PD78214 Sub-Series ES00 ... 294 ES01 ... 294 ES10 ... 294 ES11 ... 294 ES20 ... 294 ES21 ... 294 ES30 ... 295 ES31 ... 295 ES40 ... 295, 303 ES41 ... 295, 303 ES50 ... 295 ES51 ... 295 ESNMI ... 294 EXTR ... 97 F f CLK ... 55 FE ... 247 FR ... 229 H H .
455 Appendix E Index E µ PD78210 ... 20 µ PD78212 ... 1 µ PD78213 ... 1 µ PD78214 ... 1 µ PD78p214 ... 1, 399 N NC ... 31, 32 NMI ... 428, 302, 303 NMIS ... 307 O OE ... 31 OVE ... 247 OVF0 ... 112 OVF1 ... 143 OVF2 ... 163 P P0H ... 97 P0L ... 97 P0HM .
456 µ PD78214 Sub-Series PRS2 ... 207 PRS3 ... 207 PRS10 ... 144 PRS11 ... 144 PRS12 ... 144 PRS20 ... 164 PRS21 ... 164 PRS22 ... 164 PRS23 ... 164 PS0 ... 246 PS1 ... 246 PSW ... 45, 304, 308 PUO ... 65, 74, 78, 82, 91 PUO2 ... 65 PUO3 ... 74 PUO4 .
457 Appendix E Index E SO ... 29, 265 SO pin ... 267 SO latch ... 261 SP ... 46 Specifying HALT mode ... 379 Specifying STOP mode ... 382 SRIF ... 305 SRISM ... 306 SRMK ... 306 SRPR ... 307 STBC ... 379 STIF ... 305 STISM ... 306 STMK ... 306 STOP mode .
458.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté NEC PD78P214 c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du NEC PD78P214 - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation NEC PD78P214, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le NEC PD78P214 va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le NEC PD78P214, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du NEC PD78P214.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le NEC PD78P214. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei NEC PD78P214 ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
