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Desktop 4th Generation Intel ® Core ™ Processor Family, Desktop Intel ® Pentium ® Processor Family, and Desktop Intel ® Celeron ® Processor Family Datasheet – Volume 1 of 2 December 2013 Order No.
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Contents Revision History.................................................................................................................. 9 1.0 Introduction.............................................................................................
4.2.3 Requesting Low-Power Idle States...............................................................53 4.2.4 Core C-State Rules.................................................................................... 54 4.2.5 Package C-States.............
7.0 Electrical Specifications.............................................................................................. 90 7.1 Integrated Voltage Regulator.................................................................................. 90 7.2 Power and Ground Lands .
Figures 1 Platform Block Diagram ........................................................................................... 11 2 Intel ® Flex Memory Technology Operations................................................................. 21 3 PCI Express* Related Register Structures in the Processor.
Tables 1 Terminology........................................................................................................... 13 2 Related Documents.................................................................................................. 16 3 Processor DIMM Support by Product.
54 GTL Signal Group and Open Drain Signal Group DC Specifications................................ 102 55 PCI Express* DC Specifications................................................................................ 103 56 Platform Environment Control Interface (PECI) DC Electrical Limits.
Revision History Revision Description Date 001 • Initial Release June 2013 002 • Added Desktop 4th Generation Intel ® Core ™ i7-4771, i5-4440, i5-4440S, i3-4340, i3-4330, i3-4330T, i3-4130, and i3-4130T processors • Added Desktop Intel ® Pentium ® G3430, G3420, G3220, G3420T, G3220T processors • Updated Section 4.
1.0 Introduction The Desktop 4th Generation Intel ® Core ™ processor family , Desktop Intel ® Pentium ® processor family, and Desktop Intel ® Celeron ® processor family are 64-bit, multi-core processors built on 22-nanometer process technology.
Figure 1. Platform Block Diagram Processor PCI Express* 3.0 Digital Display Interface (DDI) (3 interfaces) System Memory 1333 / 1600 MT/s 2 DIMMs / CH CH A CH B Intel ® Flexible Display Interface (Intel ® FDI) (x2) Direct Media Interface 2.0 (DMI 2.
• PCLMULQDQ Instruction • Intel ® Secure Key • Intel ® Transactional Synchronization Extensions - New Instructions (Intel ® TSX- NI) • PAIR – Power Aware Interrupt Routing • SMEP – Supervisor Mode Execution Protection Note: The availability of the features may vary between processor SKUs.
Thermal Management Support • Digital Thermal Sensor • Adaptive Thermal Monitor • THERMTRIP# and PROCHOT# support • On-Demand Mode • Memory Open and Closed Loop Throttling • Memory Thermal .
Term Description ECC Error Correction Code eDP* embedded DisplayPort* EPG Electrical Power Gating EU Execution Unit FMA Floating-point fused Multiply Add instructions FSC Fan Speed Control HDCP High-b.
Term Description MLC Mid-Level Cache MSI Message Signaled Interrupt MSL Moisture Sensitive Labeling MSR Model Specific Registers NCTF Non-Critical to Function.
Term Description TAP Test Access Point T CASE The case temperature of the processor, measured at the geometric center of the top- side of the TTV IHS. TCC Thermal Control Circuit T CONTROL T CONTROL is a static value that is below the TCC activation temperature and used as a trigger point for fan speed control.
Document Document Number / Location LGA1150 Socket Application Guide 328999 Intel ® 8 Series / C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet 328904 Intel ® 8 Series / C220 Serie.
2.0 Interfaces System Memory Interface • Two channels of DDR3/DDR3L Unbuffered Dual In-Line Memory Modules (UDIMM) or DDR3/DDR3L Unbuffered Small Outline Dual In-Line Memory Modules (SO- DIMM) with a maximum of two DIMMs per channel.
System Memory Technology Supported The Integrated Memory Controller (IMC) supports DDR3/DDR3L protocols with two independent, 64-bit wide channels each accessing one or two DIMMs. The type of memory supported by the processor is dependent on the PCH SKU in the target platform.
Raw Card Version DIMM Capacity DRAM Device Technology DRAM Organization # of DRAM Devices # of Physical Devices Ranks # of Row / Col Address Bits # of Banks Inside DRAM Page Size B 2 GB 1 Gb 128 M X 8.
Note: System memory timing support is based on availability and is subject to change. System Memory Organization Modes The Integrated Memory Controller (IMC) supports two memory organization modes – single-channel and dual-channel.
be on opposite channels. Use Dual-Channel Symmetric mode when both Channel A and Channel B DIMM connectors are populated in any order, with the total amount of memory in each channel being the same.
Data Scrambling The system memory controller incorporates a Data Scrambling feature to minimize the impact of excessive di/dt on the platform system memory VRs due to successive 1s and 0s on the data bus.
• PCI Express* extended configuration space. The first 256 bytes of configuration space aliases directly to the PCI Compatibility configuration space. The remaining portion of the fixed 4-KB block of memory-mapped space above that (starting at 100h) is known as extended configuration space.
Figure 3. PCI Express* Related Register Structures in the Processor PCI-PCI Bridge representing root PCI Express ports (Device 1 and Device 6) PCI Compatible Host Bridge Device (Device 0) PCI Express*.
Figure 4. PCI Express* Typical Operation 16 Lanes Mapping 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 X 16 Co ntroller Lane 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Lane 1 Lane 2 Lane 3 Lane 4 Lane 5 Lane .
• 5 GT/s point-to-point DMI interface to PCH is supported. • Raw bit-rate on the data pins of 5.0 GB/s, resulting in a real bandwidth per pair of 500 MB/s given the 8b/10b encoding used to transmit data across this interface. Does not account for packet overhead and link maintenance.
Processor Graphics The processor graphics contains a generation 7.5 graphics core architecture. This enables substantial gains in performance and lower power consumption over previous generations. Up to 20 Execution Units are supported depending on the processor SKU.
Figure 5. Processor Graphics Controller Unit Block Diagram 3D and Video Engines for Graphics Processing The Gen 7.5 3D engine provides the following performance and power-management enhancements. 3D Pipeline The 3D graphics pipeline architecture simultaneously operates on different primitives or on different portions of the same primitive.
Vertex Shader (VS) Stage The VS stage performs shading of vertices output by the VF function. The VS unit produces an output vertex reference for every input vertex reference received from the VF unit, in the order received. Geometry Shader (GS) Stage The GS stage receives inputs from the VS stage.
Logical 128-Bit Fixed BLT and 256 Fill Engine This BLT engine accelerates the GUI of Microsoft Windows* operating systems. The 128-bit BLT engine provides hardware acceleration of block transfers of pixel data for many common Windows operations.
• The HDMI* interface supports HDMI with 3D, 4K, Deep Color, and x.v.Color. The DisplayPort* interface supports the VESA DisplayPort* Standard Version 1, Revision 2. • The processor supports High-bandwidth Digital Content Protection (HDCP) for high-definition content playback over digital interfaces.
• Organizing pixels into frames • Optionally scaling the image to the desired size • Re-timing data for the intended target • Formatting data according to the port output standard DisplayPort*.
make up the TMDS data and clock channels. These channels are used to carry video, audio, and auxiliary data. In addition, HDMI carries a VESA DDC. The DDC is used by an HDMI Source to determine the capabilities and characteristics of the Sink. Audio, video, and auxiliary (control/status) data is transmitted across the three TMDS data channels.
embedded DisplayPort* embedded DisplayPort* (eDP*) is an embedded version of the DisplayPort standard oriented towards applications such as notebook and All-In-One PCs. Digital Port D can be configured as eDP. Like DisplayPort, embedded DisplayPort also consists of a Main Link, Auxiliary channel, and an optional Hot-Plug Detect signal.
Table 9. Valid Three Display Configurations through the Processor Display 1 Display 2 Display 3 Maximum Resolution Display 1 Maximum Resolution Display 2 Maximum Resolution Display 3 HDMI HDMI DP 4096.
Intel ® Flexible Display Interface (Intel ® FDI) • The Intel Flexible Display Interface (Intel FDI) passes display data from the processor (source) to the PCH (sink) for display through a display interface on the PCH. • Intel FDI supports 2 lanes at 2.
Figure 9. PECI Host-Clients Connection Example V TT Host / Originator Q1 nX Q2 1X PECI C PECI <10pF/Node Q3 nX V TT PECI Client Additional PECI Clients Processor—Interfaces Desktop 4th Generation.
3.0 Technologies This chapter provides a high-level description of Intel technologies implemented in the processor. The implementation of the features may vary between the processor SKUs. Details on the different technologies of Intel processors and other relevant external notes are located at the Intel technology web site: http://www.
• More reliable: Due to the hardware support, VMMs can now be smaller, less complex, and more efficient. This improves reliability and availability and reduces the potential for software conflicts.
• Descriptor-Table Exiting — Descriptor-table exiting allows a VMM to protect a guest operating system from an internal (malicious software based) attack by preventing relocation of key system data structures like IDT (interrupt descriptor table), GDT (global descriptor table), LDT (local descriptor table), and TSS (task segment selector).
Figure 10. Device to Domain Mapping Structures Root entry 0 Root entry N Root entry 255 Context entry 0 Context entry 255 Context entry 0 Context entry 255 (Bus 255) (Bus N) (Bus 0) Root entry table (.
• Memory controller and processor graphics comply with the Intel VT-d 1.2 Specification • Two Intel VT-d DMA remap engines — iGFX DMA remap engine — Default DMA remap engine (covers all device.
Another aspect of the trust decision is the ability of the platform to resist attempts to change the controlling environment. The Intel TXT platform will resist attempts by software processes to change the controlling environment or bypass the bounds set by the controlling environment.
Intel recommends enabling Intel HT Technology with Microsoft Windows* 8 and Microsoft Windows* 7 and disabling Intel HT Technology using the BIOS for all previous versions of Windows* operating systems. For more information on Intel HT Technology, see http://www.
digital signal processing software. FMA improves performance in face detection, professional imaging, and high performance computing. Gather operations increase vectorization opportunities for many applications.
extensions to achieve the performance of fine-grain locking while actually programming using coarse-grain locks. Details on Intel TSX-NI are in the Intel ® Architecture Instruction Set Extensions Programming Reference.
• The semantics for accessing APIC registers have been revised to simplify the programming of frequently-used APIC registers by system software. Specifically, the software semantics for using the In.
4.0 Power Management This chapter provides information on the following power management topics: • Advanced Configuration and Power Interface (ACPI) States • Processor Core • Integrated Memory Controller (IMC) • PCI Express* • Direct Media Interface (DMI) • Processor Graphics Controller Figure 11.
Advanced Configuration and Power Interface (ACPI) States Supported This section describes the ACPI states supported by the processor. Table 11. System States State Description G0/S0 Full On Mode. G1/S3-Cold Suspend-to-RAM (STR). Context saved to memory (S3-Hot state is not supported by the processor).
Table 15. Direct Media Interface (DMI) States State Description L0 Full on – Active transfer state. L0s First Active Power Management low-power state – Low exit latency. L1 Lowest Active Power Management – Longer exit latency. L3 Lowest power state (power-off) – Longest exit latency.
• Multiple frequency and voltage points for optimal performance and power efficiency. These operating points are known as P-states. • Frequency selection is software controlled by writing to processor MSRs. The voltage is optimized based on the selected frequency and the number of active processor cores.
Figure 13. Thread and Core C-State Entry and Exit C 1 C 1 E C 7 C 6 C 3 C 0 M WAIT (C 1 ), HLT C 0 M WAIT (C 7 ), P_ LV L4 I/O R e ad M WAIT (C 6 ), P_ LV L3 I/O R e ad M WAIT (C 3 ), P_ LV L2 I/O R e.
Note: When P_LVLx I/O instructions are used, MWAIT sub-states cannot be defined. The MWAIT sub-state is always zero if I/O MWAIT redirection is used. By default, P_LVLx I/O redirections enable the MWAIT 'break on EFLAGS.IF’ feature that triggers a wakeup on an interrupt, even if interrupts are masked by EFLAGS.
Core C6 State Individual threads of a core can enter the C6 state by initiating a P_LVL3 I/O read or an MWAIT(C6) instruction. Before entering core C6 state, the core will save its architectural state to a dedicated SRAM. Once complete, a core will have its voltage reduced to zero volts.
— For package C-states, the processor is not required to enter C0 state before entering any other C-state. — Entry into a package C-state may be subject to auto-demotion – that is, the processor.
Figure 14. Package C-State Entry and Exit C 0 C 1 C 6 C 7 C 3 Package C0 State This is the normal operating state for the processor. The processor remains in the normal state when at least one of its cores is in the C0 or C1 state or when the platform has not granted permission to the processor to go into a low-power state.
Package C2 State Package C2 state is an internal processor state that cannot be explicitly requested by software. A processor enters Package C2 state when: • All cores and graphics have requested a .
Note: Package C6 state is the deepest C-state supported on discrete graphics systems with PCI Express Graphics (PEG). Package C7 state is the deepest C-state supported on integrated graphics systems (or switchable graphics systems during integrated graphics mode).
Number of Displays 1 Native Resolution Deepest Available Package C- State Single 2880x1620 60 Hz PC3 Single 2880x1800 60 Hz PC3 Single 3200x1800 60 Hz PC3 Single 3200x2000 60 Hz PC3 Single 3840x2160 6.
• Reduced possible overshoot/undershoot signal quality issues seen by the processor I/O buffer receivers caused by reflections from potentially un- terminated transmission lines. When a given rank is not populated, the corresponding chip select and CKE signals are not driven.
Selection of power modes should be according to power-performance or thermal trade-offs of a given system: • When trying to achieve maximum performance and power or thermal consideration is not an i.
assertion with all pages closed). Pre-charge power-down provides greater power savings, but has a bigger performance impact since all pages will first be closed before putting the devices in power-down mode. If dynamic power-down is enabled, all ranks are powered up before doing a refresh cycle and all ranks are powered down at the end of refresh.
Graphics Power Management Intel ® Rapid Memory Power Management (Intel ® RMPM) Intel Rapid Memory Power Management (Intel RMPM) conditionally places memory into self-refresh when the processor is in package C3 or deeper power state to allow the system to remain in the lower power states longer for memory not reserved for graphics memory.
5.0 Thermal Management This chapter provides both component-level and system-level thermal management. Topics covered include processor thermal specifications, thermal profiles, thermal metrology, fan.
Table 21. Desktop Processor Thermal Specifications Product PCG 8 Max Power Packag e C1E (W) 1, 2, 5, 9 Max Power Packag e C3 (W) 1, 3, 5, 9 Min Power Package C3 (W) 9 Max Power Packag e C6 (W) 1, 4, 5.
Processor (PCG 2013D) Thermal Profile Figure 15. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013D) 40 45 50 55 60 65 70 75 80 0 20 40 60 80 100 TTV Case Tem perature (° C) TTV Power (W) T CASE = 0.33 * Po wer + 45.0 See the following table for discrete points that constitute the thermal profile.
Processor (PCG 2013C) Thermal Profile Figure 16. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013C) See the following table for discrete points that constitute the thermal profile. Table 23. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013C) Power (W) T CASE_MAX (°C) Y = 0.
Power (W) T CASE_MAX (°C) 62 70.12 64 70.94 65 71.35 Processor (PCG 2013B) Thermal Profile Figure 17. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013B) See the following table for discrete points that constitute the thermal profile. Table 24.
Processor (PCG 2013A) Thermal Profile Figure 18. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013A) See the following table for discrete points that constitute the thermal profile. Table 25. Thermal Test Vehicle Thermal Profile for Processor (PCG 2013A) Power (W) T CASE_MAX (°C) Y = 0.
Thermal Metrology The maximum Thermal Test Vehicle (TTV) case temperatures (T CASE-MAX ) can be derived from the data in the appropriate TTV thermal profile earlier in this chapter. The TTV T CASE is measured at the geometric top center of the TTV integrated heat spreader (IHS).
The Ψ CA point at DTS = -1 defines the minimum Ψ CA required at TDP considering the worst case system design T AMBIENT design point: Ψ CA = (T CASE-MAX – T AMBIENT-TARGET ) / TDP For example, for a 95 W TDP part, the T case maximum is 72.6 °C and at a worst case design point of 40 °C local ambient this will result in: Ψ CA = (72.
Table 26. Digital Thermal Sensor (DTS) 1.1 Thermal Solution Performance Above T CONTROL Processor TDP Ψ CA at DTS = T CONTROL 1, 2 At System T AMBIENT- MAX = 30 °C Ψ CA at DTS = -1 At System T AMBIENT-MAX = 40 °C Ψ CA at DTS = -1 At System T AMBIENT-MAX = 45 °C Ψ CA at DTS = -1 At System T AMBIENT- MAX = 50 °C 84 W 0.
Figure 21. Digital Thermal Sensor (DTS) Thermal Profile Definition Table 27. Thermal Margin Slope PCG Die Configuration (Native) Core + GT TDP (W) TCC Activation Temperature (°C) MSR 1A2h 23:16 Temperature Control Offset MSR 1A2h 15:8 Thermal Margin Slope (°C / W) 2013D 4+2 (4+2) 84 100 20 0.
Adaptive Thermal Monitor The Adaptive Thermal Monitor feature provides an enhanced method for controlling the processor temperature when the processor silicon exceeds the Thermal Control Circuit (TCC) activation temperature. Adaptive Thermal Monitor uses TCC activation to reduce processor power using a combination of methods.
after 1 ms the processor is still too hot (the temperature has not dropped below the TCC activation point, DTS still = 0 and PROCHOT is still active), then a second frequency and voltage transition will take place.
If TM1 and TM2 have both been active for greater than 20 ms and the processor temperature has not dropped below the TCC activation point, the Critical Temperature Flag in the IA32_THERM_STATUS MSR will be set. This flag is an indicator of a catastrophic thermal solution failure and that the processor cannot reduce its temperature.
a backup in case of system cooling failure. The system thermal design should allow the power delivery circuitry to operate within its temperature specification even while the processor is operating at its Thermal Design Power.
have the capability of generating interrupts using the core's local APIC. Refer to the Intel ® 64 and IA-32 Architectures Software Developer’s Manual for specific register and programming details. Digital Thermal Sensor Accuracy (Taccuracy) The error associated with DTS measurements will not exceed ±5 °C within the entire operating range.
• Uncharacterized workloads may exist that could result in higher turbo frequencies and power. If that were to happen, the processor Thermal Control Circuitry (TCC) would protect the processor. The TCC protection must be enabled by the platform for the product to be within specification.
Figure 22. Package Power Control Turbo Time Parameter Turbo Time Parameter is a mathematical parameter (units in seconds) that controls the Intel Turbo Boost Technology algorithm using an average of energy usage. During a maximum power turbo event of about 1.
6.0 Signal Description This chapter describes the processor signals. The signals are arranged in functional groups according to the associated interface or category.
Signal Name Description Direction / Buffer Type SA_RAS# RAS Control Signal: This signal is used with SA_CAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands. O DDR3/DDR3L SA_CAS# CAS Control Signal: This signal is used with SA_RAS# and SA_WE# (along with SA_CS#) to define the SRAM Commands.
Signal Name Description Direction / Buffer Type SB_CK[3:0] SDRAM Differential Clock: Channel B SDRAM Differential clock signal pair. The crossing of the positive edge of SB_CK and the negative edge of its complement SB_CK# are used to sample the command and control signals on the SDRAM.
Reset and Miscellaneous Signals Table 33. Reset and Miscellaneous Signals Signal Name Description Direction / Buffer Type CFG[19:0] Configuration Signals: The CFG signals have a default value of '1' if not terminated on the board. • CFG[1:0]: Reserved configuration lane.
PCI Express*-Based Interface Signals Table 34. PCI Express* Graphics Interface Signals Signal Name Description Direction / Buffer Type PEG_RCOMP PCI Express Resistance Compensation I A PEG_RXP[15:0] P.
Phase Locked Loop (PLL) Signals Table 37. Phase Locked Loop (PLL) Signals Signal Name Description Direction / Buffer Type BCLKP BCLKN Differential bus clock input to the processor I Diff Clk DPLL_REF_.
Error and Thermal Protection Signals Table 39. Error and Thermal Protection Signals Signal Name Description Direction / Buffer Type CATERR# Catastrophic Error: This signal indicates that the system has experienced a catastrophic error and cannot continue to operate.
Processor Power Signals Table 41. Processor Power Signals Signal Name Description Direction / Buffer Type VCC Processor core power rail. Ref VCCIO_OUT Processor power reference for I/O. Ref VDDQ Processor I/O supply voltage for DDR3. Ref VCOMP_OUT Processor power reference for PEG/Display RCOMP.
7.0 Electrical Specifications This chapter provides the processor electrical specifications including integrated voltage regulator (VR), V CC Voltage Identification (VID), reserved and unused signals, signal groups, Test Access Points (TAP), and DC specifications.
Table 45. Voltage Regulator (VR) 12.5 Voltage Identification B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 0 0 0 0 0 0 0 0 00h 0.0000 0 0 0 0 0 0 0 1 01h 0.5000 0 0 0 0 0 0 1 0 02h 0.5100 0 0 0 0 0 0 1 1 03h 0.5200 0 0 0 0 0 1 0 0 04h 0.
B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 0 1 0 0 0 0 1 0 42h 1.1500 0 1 0 0 0 0 1 1 43h 1.1600 0 1 0 0 0 1 0 0 44h 1.1700 0 1 0 0 0 1 0 1 45h 1.1800 0 1 0 0 0 1 1 0 46h 1.1900 0 1 0 0 0 1 1 1 47h 1.2000 0 1 0 0 1 0 0 0 48h 1.
B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 1 0 0 0 0 1 1 0 86h 1.8300 1 0 0 0 0 1 1 1 87h 1.8400 1 0 0 0 1 0 0 0 88h 1.8500 1 0 0 0 1 0 0 1 89h 1.8600 1 0 0 0 1 0 1 0 8Ah 1.8700 1 0 0 0 1 0 1 1 8Bh 1.8800 1 0 0 0 1 1 0 0 8Ch 1.
B i t 7 B i t 6 B i t 5 B i t 4 B i t 3 B i t 2 B i t 1 B i t 0 Hex V CC 1 1 0 0 1 0 1 0 CAh 2.5100 1 1 0 0 1 0 1 1 CBh 2.5200 1 1 0 0 1 1 0 0 CCh 2.5300 1 1 0 0 1 1 0 1 CDh 2.5400 1 1 0 0 1 1 1 0 CEh 2.5500 1 1 0 0 1 1 1 1 CFh 2.5600 1 1 0 1 0 0 0 0 D0h 2.
Reserved or Unused Signals The following are the general types of reserved (RSVD) signals and connection guidelines: • RSVD – these signals should not be connected • RSVD_TP – these signals sh.
Signal Group Type Signals DDR3 / DDR3L Data Signals 2 Single ended DDR3/DDR3L Bi- directional SA_DQ[63:0], SB_DQ[63:0] Differential DDR3/DDR3L Bi- directional SA_DQSP[7:0], SA_DQSN[7:0], SB_DQSP[7:0],.
Signal Group Type Signals Test Point RSVD_TP Other SKTOCC#, PCI Express* Graphics Differential PCI Express Input PEG_RXP[15:0], PEG_RXN[15:0] Differential PCI Express Output PEG_TXP[15:0], PEG_TXN[15:.
• AC tolerances for all DC rails include dynamic load currents at switching frequencies up to 1 MHz. Voltage and Current Specifications Table 47. Processor Core Active and Idle Mode DC Voltage and Current Specifications Symbol Parameter Min Typ Max Unit Note 1 Operational VID VID Range 1.
Symbol Parameter Min Typ Max Unit Note 1 I CC 2013A PCG I CC — — 48 A 4, 8 P MAX 2013D PCG P MAX — — 153 W 9 P MAX 2013C PCG P MAX — — 121 W 9 P MAX 2013B PCG P MAX — — 99 W 9 P MAX 2013A PCG P MAX — — 83 W 9 Notes: 1.
Table 49. VCCIO_OUT, VCOMP_OUT, and VCCIO_TERM Symbol Parameter Typ Max Units Notes VCCIO_OUT Termination Voltage 1.0 — V ICCIO_OUT Maximum External Load — 300 mA VCOMP_OUT Termination Voltage 1.0 — V 1 VCCIO_TERM Termination Voltage 1.0 — V 2 Notes: 1.
Symbol Parameter Min Typ Max Units Notes 1 R ON_DN(CTL) DDR3/DDR3L Control Buffer pull-down Resistance 19 25 31 Ω 5, 11, 13 R ON_UP(RST) DDR3/DDR3L Reset Buffer pull-up Resistance 40 80 130 Ω — R ON_DN(RST) DDR3/DDR3L Reset Buffer pull-up Resistance 40 80 130 Ω — I LI Input Leakage Current (DQ, CK) 0V 0.
Table 52. embedded DisplayPort* (eDP*) Group DC Specifications Symbol Parameter Min Typ Max Units V IL HPD Input Low Voltage 0.02 — 0.21 V V IH HPD Input High Voltage 0.84 — 1.05 V V OL eDP_DISP_UTIL Output Low Voltage 0.1*V CC — — V V OH eDP_DISP_UTIL Output High Voltage 0.
Symbol Parameter Min Max Units Notes 1 V IH Input High Voltage (other GTL) V CCIO_TERM * 0.72 — V 2, 4 R ON Buffer on Resistance (CFG/BPM) 16 24 Ω — R ON Buffer on Resistance (other GTL) 12 28 Ω — I LI Input Leakage Current — ±150 μA 3 Notes: 1.
Symbol Definition and Conditions Min Max Units Notes 1 V n Negative-Edge Threshold Voltage 0.275 * V CCIO_TERM 0.500 * V CCIO_TERM V — V p Positive-Edge Threshold Voltage 0.550 * V CCIO_TERM 0.725 * V CCIO_TERM V — C bus Bus Capacitance per Node N/A 10 pF — C pad Pad Capacitance 0.
8.0 Package Mechanical Specifications The processor is packaged in a Flip-Chip Land Grid Array package that interfaces with the motherboard using the LGA1150 socket.
mechanical system or component testing should not exceed the maximum limits. The processor package substrate should not be used as a mechanical reference or load- bearing surface for thermal and mechanical solution.
Table 59. Processor Materials Component Material Integrated Heat Spreader (IHS) Nickel Plated Copper Substrate Fiber Reinforced Resin Substrate Lands Gold Plated Copper Processor Markings The following figure shows the top-side markings on the processor.
Figure 26. Processor Package Land Coordinates Processor Storage Specifications The following table includes a list of the specifications for device storage in terms of maximum and minimum temperatures and relative humidity. These conditions should not be exceeded in storage or transportation.
Parameter Description Minimum Maximum Notes RH sustained storage The maximum device storage relative humidity for a sustained period of time. 60% @ 24 °C 5, 6 TIME sustained storage A prolonged or extended period of time; typically associated with customer shelf life.
9.0 Processor Ball and Signal Information This chapter provides processor ball information. The following table provides the ball list by signal name. Note: References to SA_ECC_CB[7:0] and SB_ECC_CB[7:0] are for processor SKUs that support ECC. These signals are reserved on the Desktop 4th Generation Intel ® Core ™ processor family.
Signal Name Ball # DPLL_REF_CLKN W6 DPLL_REF_CLKP W5 EDP_DISP_UTIL E16 FC_K9 K9 FC_Y7 Y7 FDI_CSYNC D16 FDI0_TX0N0 B14 FDI0_TX0N1 C13 FDI0_TX0P0 A14 FDI0_TX0P1 B13 IST_TRIGGER C39 IVR_ERROR R36 PECI N3.
Signal Name Ball # RSVD J17 RSVD J40 RSVD J9 RSVD L10 RSVD L12 RSVD M10 RSVD M11 RSVD M38 RSVD N35 RSVD P33 RSVD R33 RSVD R34 RSVD T34 RSVD T35 RSVD T8 RSVD U8 RSVD W8 RSVD Y8 RSVD_TP A4 RSVD_TP AV1 R.
Signal Name Ball # SA_DQ53 AL3 SA_DQ54 AJ2 SA_DQ55 AJ1 SA_DQ56 AG1 SA_DQ57 AG4 SA_DQ58 AE3 SA_DQ59 AE4 SA_DQ6 AF37 SA_DQ60 AG2 SA_DQ61 AG3 SA_DQ62 AE2 SA_DQ63 AE1 SA_DQ7 AF40 SA_DQ8 AH40 SA_DQ9 AH39 S.
Signal Name Ball # SB_DQ3 AH35 SB_DQ30 AP29 SB_DQ31 AP28 SB_DQ32 AR12 SB_DQ33 AP12 SB_DQ34 AL13 SB_DQ35 AL12 SB_DQ36 AR13 SB_DQ37 AP13 SB_DQ38 AM13 SB_DQ39 AM12 SB_DQ4 AD34 SB_DQ40 AR9 SB_DQ41 AP9 SB_.
Signal Name Ball # VCC A24 VCC A25 VCC A26 VCC A27 VCC A28 VCC A29 VCC A30 VCC B25 VCC B27 VCC B29 VCC B31 VCC B33 VCC B35 VCC C24 VCC C25 VCC C26 VCC C27 VCC C28 VCC C29 VCC C30 VCC C31 VCC C32 VCC C33 VCC C34 VCC C35 VCC D25 VCC D27 VCC D29 VCC D31 VCC D33 VCC D35 VCC E24 VCC E25 VCC E26 VCC E27 VCC E28 continued.
Signal Name Ball # VCC L28 VCC L29 VCC L30 VCC L31 VCC L32 VCC L33 VCC L34 VCC M13 VCC M15 VCC M17 VCC M19 VCC M21 VCC M23 VCC M25 VCC M27 VCC M29 VCC M33 VCC M8 VCC P8 VCC_SENSE E40 VCCIO_OUT L40 VCO.
Signal Name Ball # VSS AG40 VSS AG5 VSS AG8 VSS AH1 VSS AH2 VSS AH3 VSS AH33 VSS AH36 VSS AH4 VSS AH5 VSS AH8 VSS AJ11 VSS AJ14 VSS AJ16 VSS AJ18 VSS AJ19 VSS AJ22 VSS AJ23 VSS AJ26 VSS AJ27 VSS AJ30 VSS AJ31 VSS AJ32 VSS AJ33 VSS AJ34 VSS AJ35 VSS AJ36 VSS AJ37 VSS AJ40 VSS AJ5 VSS AJ8 VSS AK1 VSS AK10 VSS AK11 VSS AK12 VSS AK13 continued.
Signal Name Ball # VSS AP24 VSS AP27 VSS AP30 VSS AP36 VSS AP4 VSS AP5 VSS AR11 VSS AR14 VSS AR16 VSS AR17 VSS AR18 VSS AR19 VSS AR20 VSS AR21 VSS AR22 VSS AR23 VSS AR24 VSS AR27 VSS AR30 VSS AR31 VSS AR32 VSS AR33 VSS AR34 VSS AR35 VSS AR36 VSS AR37 VSS AR38 VSS AR39 VSS AR40 VSS AR5 VSS AT1 VSS AT10 VSS AT11 VSS AT12 VSS AT13 VSS AT14 continued.
Signal Name Ball # VSS C6 VSS D11 VSS D13 VSS D15 VSS D17 VSS D2 VSS D23 VSS D24 VSS D26 VSS D28 VSS D30 VSS D32 VSS D34 VSS D36 VSS D37 VSS D5 VSS D6 VSS D7 VSS D9 VSS E10 VSS E18 VSS E20 VSS E22 VSS E23 VSS E3 VSS E36 VSS E38 VSS E6 VSS E7 VSS E8 VSS F1 VSS F12 VSS F14 VSS F16 VSS F19 VSS F21 continued.
Signal Name Ball # VSS K40 VSS K7 VSS L11 VSS L13 VSS L14 VSS L3 VSS L35 VSS L36 VSS L38 VSS L6 VSS L7 VSS L8 VSS L9 VSS M1 VSS M12 VSS M14 VSS M16 VSS M18 VSS M20 VSS M22 VSS M24 VSS M26 VSS M28 VSS M30 VSS M32 VSS M34 VSS M35 VSS M37 VSS M4 VSS M40 VSS M5 VSS M6 VSS M7 VSS M9 VSS N1 VSS N2 continued.
Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Intel CM8064601466200 c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Intel CM8064601466200 - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Intel CM8064601466200, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Intel CM8064601466200 va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Intel CM8064601466200, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Intel CM8064601466200.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Intel CM8064601466200. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Intel CM8064601466200 ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
