Manuel d'utilisation / d'entretien du produit 41110 du fabricant Intel
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Intel® 41 1 10 Serial to Parallel PCI Bridge Design Guid e March 2006 Order Num ber: 31033 5-001.
ii Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide INFORMA TION IN THIS DOCUM ENT IS PROVIDE D IN CONNECTION WIT H INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTO PPEL OR OTHERWISE, T O ANY INTELLECTUAL PROPERTY RIG H TS IS GRANTED BY THIS DOCUMENT .
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide iii Contents Contents 1 About This Document ................... ............. ................... ............. ................... ............. ................... 7 1.1 Terminology and Defin itions .
iv Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Contents 10.2 41110 Refe rence and Co mpensati on Pins ........ ............ .................... ............. ................... . 48 11 41110 Customer Reference Boards ............. ...
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide v Contents 10 Embedd ed PCI-X 133 MHz Routing Re commenda tions ........... ................... ............. ................. 36 11 Embedd ed PCI-X 100 MHz Routing Re commenda tions .......
vi Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Contents Revision History Date Revision Description March 2006 001 Initial release..
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 7 About This Document 1 Thi s d ocu m ent provi des l a you t inf orma tion a nd gu idel ines for de sign ing p latf orm o r add- in bo ard applications with the Intel® 411 10 S erial to Parallel PCI Bridge (also called the 4 1 1 10 Bridge).
8 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide About This Document PCB Printed circuit board. Example manufacturing process consists of the following steps: • Consists of alt ernating layers of core and prepreg stacked • The finished PCB is heated and cured.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 9 Introduction 2 The Intel® 41 1 10 Serial to Parallel PCI Bridge integrates a PCI Express-to-PCI bridge. The bridge follows the PCI-to-PCI Bridge pr ogramming model. The PCI Express po rt is compliant to th e PCI Expr ess Specification , Revision 1.
10 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Introduction • Up to two downstream delayed (memory read, I/O read/write and configuration read/write) transaction.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 11 Introduction Figur e 1. Microc ont rol ler Blo ck Diagra m 2.4.2 Micro control ler Connections to the 41 1 10 Figu re 2 shows the SMB interface from th e 41 1 10 to the microcontr oller .
12 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Introduction Figure 2. 41 1 1 0 M icr ocontroller Connections 2.5 JT AG • Compliant with IEEE S tandar d T est Access Port and Bo undary Sca n Ar chitectur e 1 149.1a 2.6 Related Documents • .
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 13 Introduction 2.7 Intel® 41 1 10 Serial to Parallel PCI Bridge Applications This section provides a block diag ram for a typical the 41 1 10 application. This appl ication shows a PCI-E adapter card with two Dual 2Gb Fibre Chann e l controllers.
14 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Introduction Figure 4. 41 1 10 Adapter Card Block Diagram Seri a l to Pa ra lle l PCI Bridge.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 15 Package Information 3 3.1 Package Specification The 41 1 10 Bridge is in a 5 67-ball F CBGA package, 31mm X 31mm i n size, with a 1.27mm bal l pitch (see Figure 5 and Fi gur e 6 ). Figure 5.
16 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Package Information Figure 6. 41 1 10 Bridge Package Dimensions (Side V iew) Note: Primary datum -C- and s eating plane are defin ed by the spherical crowns of the solder balls. Note: Al l dime n si on s and t oler ance s con f orm t o A NSI Y14.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 17 Power Plane Layout 4 This chapt er provid es details on the decoup ling and v oltage planes needed to b ias the 41 1 10 package. 4.1 41 1 10 Deco upling Gu idelines Ta b l e 2 lists the decoup ling guidelines for the 41 1 10.
18 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Power P lane Layout Figure 8 . D ecoupling Placement for PCI/P CI-X 1.5V an d 3.3V V oltage Planes B2714-01 Capacitor Legend 0603-0.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 19 Power Plan e La yout T abl e 2. 41 1 10 Decoupling G uidelines 4.2 S plit V oltage Planes There are two 1.5V volt age planes that supply pow er to the 41 1 10: • VCC15:1 .5V ±5% (1.5V core vol tage) • VCCPE:1.
20 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Power P lane Layout Note: Linear voltage r egulators ar e recommend ed when using 1.5 V olt pow er suppli es.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 21 41 1 10 Reset and Power Timing Considerations 5 This chapter describes the 411 1 0 reset timing considerations. 5.1 A_RST# and PERST# T iming Requirements The PCI-X Specification req uires that there i s a 100ms delay from valid power (PER ST # ) to reset deassertion (A_RST#).
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Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 23 General Routing Guidelines 6 This chapter pr ovides some basi c routing gu idelines for layou t and design of a print ed circuit board using the 41 110 . The high-sp eed clockin g requir ed when designi ng with the 41 110 requir es speci al attention to signal integrity .
24 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide General Routing Guidelines • A void slots in the gro und plane. S lots increas es mutual inductance th us increas ing crosstalk. • Make sure th at ground pl ane surro unding connect or pin fields are n ot completely cleared out.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 25 General Routing Guidelines 6.4 Power Distribution and Decoup ling Have ample deco upling to g round, for the power p l anes, to minimize the ef fects of the switching currents. Thr ee types of decoupling are: th e bulk, the high- frequency ceramic, and th e inter-plan e capacitors.
26 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide General Routing Guidelines Note: Using stripline transmiss ion lines may give better results than microst rip.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 27 Board Layout Guidelines 7 This chapter pr ovides details on adap ter card stack up suggestions. It is highly r ecommended that signal integrity simulations be run to verify each 41 1 10 PCB layou t especially if it deviates from the recommendations list ed in these design guidelines.
28 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Board Layout Guide lines Note: Each interface will set the trace spacing bas ed on its signal integrity of d ifferential imp edance requirements. For the purposes of the building the transmission line models, it is assum ed the artwork is very accurate and therefore a constant.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Gu ide 29 PCI-X Layout Guidelines 8 This chapter describes several factors to be co nsidered wi th a 41 1 10 PCI/PCI-X desi gn. These include the PCI IDSEL, PCI RCOMP , PCI Interrupts and PCI arbitration.
30 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide PCI-X Layo ut Guidelines Note: PCI Express A ssert_IN Tx/Deassert _INTx messag es are not i nhibited by the BME bi t.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 31 PCI-X Layout Guidelines • Bus parking on last PCI agent or the bridge. By defaul t, the arbit er parks the b us on the br idge and drives the A/D, C/BE# and P AR lines to a known value while the bus is idle.
32 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide PCI-X Layo ut Guidelines T able 7. PCI/PCI-X Frequency/Mode Stra ps Note: All signals s ampled on the rising ed ge of PERST # .
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 33 PCI-X Layout Guidelines distributed to each PCI device. The 41 110 provides seven buf fered clocks o n t he PCI bus t o conn ect to multip le PCI-X devi ces. The Figure 16 shows the use of fo ur PC I “A” clock output s and len gth matching requirements.
34 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide PCI-X Layo ut Guidelines T able 8. PCI-X Clock Layout Requirement s Summary Paramet e r Routing Gui delines Signal Group PCI Clocks A_CLK[.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 35 PCI-X Layout Guidelines 8.5 PCI-X T o pology Layo ut Guidelines The PCI-X Addendum to the PCI Local Bus Specification , R evision 1.0a compliant, recommends the foll owing guide lines f or th e number of loads for yo ur PC I-X de signs.
36 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide PCI-X Layo ut Guidelines 8.6.1 Embedded PCI-X 133 MHz This section l ists the routing recommendations fo r PCI-X 133 MHz wi thout a slot. Figure 1 7 shows the block di agram of thi s topol ogy and Ta b l e 1 0 describe s the rou ting recommen dations.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 37 PCI-X Layout Guidelines 8.6.2 Embedded PCI-X 100 MHz This section lists th e embed ded rou ting recommendations for PCI-X 100 MHz. Figur e 18 shows the bl ock diagr am of this t opol o gy and Ta b l e 1 1 describes the ro uting recomm endations.
38 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide PCI-X Layo ut Guidelines 8.6.3 PCI -X 66 MHz Embedded T op olo gy Figur e 19 an d Ta b l e 1 2 provide routi ng details f or a topolo gy with an emb edded PCI- X 66 MHz application. Figure 19.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 39 PCI-X Layout Guidelines 8.6.4 PCI 66 MHz Embedded T op ology Figu re 20 and Ta b l e 1 3 provi de routing det ails for a topology w ith an embedded P CI 66 MHz design. P Figure 20. PCI 66 MHz Embedded T opology T able 13.
40 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide PCI-X Layo ut Guidelines 8.6.5 PCI 33 MHz Embedded Mod e T o pology Figur e 21 an d Ta b l e 1 4 provide routi ng details f or a topolo gy with an emb edded PCI 33 MHz design. Figure 21. PCI 33 MHz Embedded Mode Routing T opology T able 14.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 41 PCI Express Layout 9 This section provid es an overview of the PC I-Express stackup r ecommended based o n Intel presimulation results.
42 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide PCI Express Layo ut 9.2 PCI-Express Layout Guidelin es The layout guidel ines for PCI-Express were deve loped for an adapter card topologies.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 43 PCI Ex press Layou t Receive Tr ace Length (Card edge finger to 41 1 10 re ceiver pin 1.0” min - 6.0” max Length Matching Requirements: T otal allowable intra-pair length mis-m atch must not ex ceed 25 mi ls.
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Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 45 Circuit Implementations Circuit Implementations 10 This chapter describes 411 10 circuit implementations.
46 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Circuit Implementations 10.1.1 PCI Analog V olt age Filters The following filter circuit is recommended fo r the PCI interface. Three separate, identical versions of this circuit should be placed on the system board, one for each VCCAPCI[2:0] pin on the 41 1 1 0.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 47 Circuit Implementations Figure 23. PCI Express Analog V oltage Filter Circuit Additional No tes : • Place C as close as possible to p ackage pin. • R must be placed between VC C 15 and L.
48 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Circuit Implementations Figure 24. B andgap Analog V olt age Filter Circuit Ad dition al Note s : • Place C as close as pos sible to package p in. • R must be placed between the 2.5 V supply and L.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 49 Circuit Implementations Figure 25. Reference and Compensation Circuit Implement ations 10.
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Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 51 41 1 10 Customer Reference Boards 11 This chapt er describes the 41 1 10 Customer Reference Board (CRB).
52 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide 41 1 1 0 Customer Reference Boards 11 . 2 M a t e r i a l The following materials are us ed with the 41 110 CRB: • FR-4, 0.0 62 in. +/- .007, 1.0 oz Copper Power/G ND. • Full len gth PCI Raw C ard (3.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 53 41 1 1 0 Custome r Reference Bo ards 1 1.4 Bo ard Outline Figu re 26 provides the mechanical outline of the 41 11 0 CRB.
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Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 55 Design Guide Checklist 12 This checkl ist highlight s design consideratio ns that s hould be review ed prior t o manufacturing an adapter card that implemen ts the 41 110 product.
56 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Design Guide Checklist T able 20. PCI/PCI-X Interface Signals (Sheet 1 of 2) Signals Recomm endations Reason/Impact A_AD[63:32] A_CBE[7:4].
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 57 Design Guide Checklist A_M66E N Controls frequency of the PCI segment when running in conventional PCI mode (33 MHz or 66 MHz): 0 = 33 MHz PCI 1 = 66 MHz PCI • Pull-up using a 8.2K Ω resistor when the P CI bus is to operate at 66 MH z and not already pulled up by system board.
58 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Design Guide Checklist CFGRETRY Input pin to configure 41 1 10 to retry configuration accesses on it's PCI Express interf ace. • T o retry configu ration accesses to the 4 111 0 , pul l high to 3.
Intel® 411 10 Serial to Pa rallel PCI Bridge Design Guide 59 Design Guide Checklist T abl e 23. Reset Pins Ballout Pin Name Usag e E6 STR AP_V_ 1 Pull u p to V CC33 B5 STR AP_V_ 2 Pull u p to V CC33 .
60 Intel® 41 110 Serial to Parallel PCI Bri dge Design Guide Design Guide Checklist T able 24. Power and Ground Signals Signal Re commendat ions Reason/Im pac t RCOMP 100 Ω ±1% (1/4 W) pul ldown resistor to ground. The trace impedance of this signal should be < 0.
T abl e 25. JT AG Signals Signal Recommendati ons R eason/Imp act TCK If not used for JT A G , leave as No Connect Internal pull-up TDI If not used for JT AG , leave as No Connect Internal pull-up TDO.
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Un point important après l'achat de l'appareil (ou même avant l'achat) est de lire le manuel d'utilisation. Nous devons le faire pour quelques raisons simples:
Si vous n'avez pas encore acheté Intel 41110 c'est un bon moment pour vous familiariser avec les données de base sur le produit. Consulter d'abord les pages initiales du manuel d'utilisation, que vous trouverez ci-dessus. Vous devriez y trouver les données techniques les plus importants du Intel 41110 - de cette manière, vous pouvez vérifier si l'équipement répond à vos besoins. Explorant les pages suivantes du manuel d'utilisation Intel 41110, vous apprendrez toutes les caractéristiques du produit et des informations sur son fonctionnement. Les informations sur le Intel 41110 va certainement vous aider à prendre une décision concernant l'achat.
Dans une situation où vous avez déjà le Intel 41110, mais vous avez pas encore lu le manuel d'utilisation, vous devez le faire pour les raisons décrites ci-dessus,. Vous saurez alors si vous avez correctement utilisé les fonctions disponibles, et si vous avez commis des erreurs qui peuvent réduire la durée de vie du Intel 41110.
Cependant, l'un des rôles les plus importants pour l'utilisateur joués par les manuels d'utilisateur est d'aider à résoudre les problèmes concernant le Intel 41110. Presque toujours, vous y trouverez Troubleshooting, soit les pannes et les défaillances les plus fréquentes de l'apparei Intel 41110 ainsi que les instructions sur la façon de les résoudre. Même si vous ne parvenez pas à résoudre le problème, le manuel d‘utilisation va vous montrer le chemin d'une nouvelle procédure – le contact avec le centre de service à la clientèle ou le service le plus proche.
